Higher Grade Computing

Computer Systems

Unit 2

Computer Structure

Computer Organisation

• Most computers still use the Von Neumann architecture.

• Computing problems are defined as a sequence of instructions (program) stored in main memory.

–these are fetched in turn, decoded and executed by a processor.

Memory with program stored in it

10110100 10101101 01011011 10101001 01101010 ...

Processor fetches, decodes and executes each program instruction

Structure of the CPU

• Any program being executed is stored in the main memory of the computer.

• Each program instruction (there may be millions) is fetched from memory, decoded then executed.

• Each memory location has a unique address.

Main Memory

Processor

Backing Storage

Output Input

Block Diagram of a Computer System

B

Block Diagram of a Computer

= Data Flow

The Structure of the Processor

Main Memory

OtherRegisters

ALU

MAR

MDR

CU

Electronic Clock

Control ‘Bus’ (read and write)

Data Bus

Address Bus

Clock Pulses

The Processor

• The processor contains:

– the ALU

– the registers

– the control unit

The ALU

• The ALU (Arithmetic Logic Unit)–carries out arithmetic operations

such as add and subtract.

–carries out logical operations such as ‘AND’ and ‘OR’.

The Control Unit

• The control unit controls the fetching, decoding and executing of program instructions.

• It is connected to the control ‘bus’.

• It sends and receives control signals to/from other parts of the computer.

The Registers

• The registers are temporary storage locations inside the processor itself which can be accessed much faster than locations in main memory.

• They are used for holding data, addresses or instructions.

Structure of the CPU

• The CPU consists of the processor and memory.

• The two are connected by three collections of wires called ‘buses’.

• These are the address bus, the data bus and the control ‘bus’.

The CPU

Memory

Processor

Address bus

Data bus

Control ‘bus’

Address bus

• The address bus carries signals from the processor to memory.

• These signals specify which address in memory is to be read from or written to.

• It is a one-way (‘uni-directional’) bus.

Memory

Processor

Address bus

Address signal sent on address bus..

..’opens up’ specified memory

location

Data bus

• The data bus carries signals both ways between the processor and memory.

• These signals are either program instructions or data.

• The data bus is two-way (‘bi-directional’).

Control ‘bus’

• The control ‘bus’ is not a true bus.

• It carries different lines each with their own separate functions.

• Examples are:– read, write, clock, interrupt, reset

Control ‘bus’ lines

• write–initiates a write to memory

operation.

• read–initiates a read from memory

operation.

Control ‘bus’ lines

• clock–carries signals from the clock chip

which are used to synchronise events.

• reset–clears processor registers and starts

fetching from a pre-defined location.

Control ‘bus’ lines

• IRQ (Interrupt Request)–carries signals from peripheral

devices which require to be serviced.

• NMI (Non-Maskable Interrupt)–carries urgent signals from

peripherals which cannot be ignored.

Interrupts• An interrupt is a signal to the processor from an input or

output device.• The interrupt system allows peripheral devices to

communicate with the processor.• An interrupt:

– Causes a break in the execution of the processors current program.– The processor saves a copy of what it is doing, runs a program to

deal with the interrupt, then reloads its original task and continues.

• A non-maskable interrupt behaves in the same way as an interrupt except that the processor cannot mask or ignore the interrupt.

Interrupts

• Software can be used to make the processor ignore or mask the interrupt signal from a peripheral.

• You would want to ensure that the processor ignored (masked) the fact that a printer had ran out of paper and not cause the processor to ‘hang’ waiting for paper to be added to the printer.

Read from memory

Memory

Processor

Address put on address bus

Data sent on data bus from specified memory address

Read line on control ‘bus’ set

Write to memory

Memory

Processor

Address put on address bus

Data sent on data bus to specified memory address

Write line on control ‘bus’ set

Stack Pointer

Program Counter

Memory Address Register

Arithmetic Logic Unit

Instruction Register

Memory Data

Register

Control Unit

A

B

C

D

AddressBus

DataBus

Control‘Bus’

Fetch Execute Cycle

• Address of the next instruction to be fetched is transferred from the program counter and placed in the MAR and hence the address bus.

Program Counter

Memory Address Register

AddressBus

Fetch Execute Cycle

• The program counter is incremented to give the address of the next instruction in memory.

0000111000001111

• The read line on the control bus is activated.

Fetch Execute Cycle

• The program instruction is read from the specified memory address and is transferred on the data bus to the MDR.

Memory Data

Register

Instruction sent along data bus to

MDR

Fetch Execute Cycle

• The program instruction is transferred from the MDR to the instruction register (IR) to be decoded and executed.

Instruction Register

Memory Data

Register

Read Operation from Memory

1. Processor sets up the address bus with the required memory address. It does this by placing a value in the MAR.

2. The Control Unit activates the READ line on the control bus.

3. The contents of the storage location in memory are released onto the data bus and placed into the MDR.

4. If this is an instruction it is decoded and executed.

Write Operation to Memory

1. Processor sets up the address bus with the required memory address. It does this by placing a value in the MAR.

2. The processor sets up the data bus with the value to be written to memory. It does this by placing the value in the MDR.

3. The Control Unit activates the WRITE line on the control bus.

4. The contents of the MDR are transferred to the storage location in memory.

Summary of the Fetch –Execute cycle

1. Processor sets up the address bus with the required address.

2. Processor activates the read line.3. Instruction is transferred from

memory to the processor by using the data bus (fetch).

4. The instruction is decoded.5. The instruction is executed.

1 PC holds address of next instruction to be executed

6 (0110)

1010 0100

0000 1111

2. Put contents of PC into MAR

6 (0110)

6 (0110)

1010 0100

0000 1111

3. Read line is set (control bus)

6 (0110)

6 (0110)

1

1010 0100

0000 1111

4. Clock pulse now causes Memory to place contents of that memory location onto data bus

6 (0110)

6 (0110)

1

1

1010 0100

0000 1111

1010 0100

5. Therefore that now appears in the MDR

6 (0110)

6 (0110)

1010 0100

1010 0100

0000 1111

6. This is a program instruction, so this is now placed into the IR

It is known that this is a program instruction as this came originally from the PC

6 (0110)

6 (0110)

1010 0100

1010 0100

1010 0100

0000 1111

7. The PC is now incremented

7 (0111)

6 (0110)

1010 0100

1010 0100

1010 0100

0000 1111

Memory/Storage

• There are four main types of computer storage:–backing storage (largest)

–main memory

–cache memory

–registers (smallest)

1 Backing storage

• Backing storage is where programs and data are stored permanently until required.

• Backing storage allows backup copies of data to be kept.

• Examples are hard drives, CD-R, CD-R etc.

2 Main Memory

• Main memory is where:– programs are held while being run.

–data created by programs or entered by the user is stored .

• Main memory consists of:–ROM and RAM.

2 Main Memory

• ROM (Read Only Memory)•holds system programs needed at start up (e.g. bootstrap loader).

•contents are permanent.

•user cannot change contents of ROM.

2 Main Memory

• RAM (Random Access Memory)•Holds programs and data loaded in from backing storage.

•Holds data typed in by user.•User can change contents of RAM.•Contents disappear at power off.•DRAM and SRAM.

– Dynamic – has to have its data consistently refreshed or it is lost.– Static – does not need to have its contents constantly refreshed.

3 Cache memory

• Special very fast access memory between the rest of the main memory and the processor.

• Frequently used program instructions and data are copied there to speed up processing.

• There are usually 2 levels of Cache memory:– Level 1 – usually built into the processor chip

(ultra close to the ‘action’).– Level 2 – may be on the chip as well but more

often very close to it.– It is much faster for the processor to access data

held in Cache than in main memory.

3 Cache memory

Processor

Cache memory

Main memory

fast accessvery fast access

4 Registers

• Registers are fast access temporary storage within the processor which can hold:–data (MDR).

–an instruction being executed (the instruction register (IR)).

–the address to be accessed (MAR).

Stack Pointer

Program Counter

Memory Address Register

Arithmetic Logic Unit

Instruction Register

Memory Data

Register

Control Unit

A

B

C

D

AddressBus

DataBus

Control‘Bus’

Summary of memory/ storage

• In ascending order of speed of access:–Backing storage (slowest)

–Main memory

–Cache memory

–Internal processor registers (fastest)

Addressability of memory

• The place where each item is stored in a computers memory is important because the computer has to be able to find any given item of data.

• An item is stored in memory in a storage location.• Each location in main memory is identified by a

unique binary number called its address. The method a computer uses to identify storage locations is called its addressability.

• Addresses start at zero and go up to a number which is determined by the width of the address bus.

E.g. with an 8-bit address bus:

Address Contents

00000000 10101101

00000001 11010111

00000010 00110101

…. ….

00000011 10101001

11111111 01101010

Addressability of memory

• 16 bit address bus (16 wires)

• Range is: 0000000000000000up to: 1111111111111111

• from 0 .. 65535

• from 0 .. 216 -1

• 216 distinct addresses

Addressability of memory

• 24 bit address bus (24 wires).• Range is: 000000000000000000000000

up to:111111111111111111111111

• from 0 .. 167772125

• from 0 .. 224 -1

• 224 distinct addresses.

Addressability of memory

• n bit address bus (n wires).• range is 0 .. 2n -1• 2n distinct addresses.• The quantity of memory which can be

addressed, can be calculated using the formula:–Total addressable memory = Number of

storage locations x size of each storage location.

Word length

• The number of bits which can be manipulated in a single unit by the processor is called the word length of the computer.

• The word length is determined by the size of the data bus.

Memory and bus widths

• The wider the data bus the more data can be transferred between the processor and memory at a time. Widening the data bus will improve PC performance as more data can be sent at one time.

• This means a bigger word length.

• e.g. a 32 bit data bus = 32 bit word length.

How much memory can a computer with a 32 bit address bus and a 16 bit data bus

address?

No of locations = 232 = 4294967296

Each location has 16 bits = 2 bytes

Total memory = 2 * 4294967296

= 8589934592 bytes

dividing by 1024 = 83888608 KB

dividing by 1024 = 8192 Mb = 8GB

An alternate way to work it out

• Address bus is 32 bits.• Data bus is 16 bits.• Number of storage locations = 232 because the

address bus is 32 bits wide.• Size of each storage location = 2 bytes because

the data bus is 16 bits wide.• Total addressable memory is 232 x 2 bytes = 233

bytes.• 233 bytes = 230 x 23 = 23 x 1 Gigabyte = 8

Gigabytes.

Measuring Computer Performance• In order to tell how fast a computer system can process data,

it is necessary to measure its performance.

• A number of measures have been developed:– Clock Speed– MIPS– FLOPS– Application Based Tests

Clock Speed• The computers clock signal is carried by one of the lines on

the control ‘bus’. • The clock generates a series of pulses at a constant rate.• The rate is the frequency at which the clock generates

pulses and is usually (now) measured in Gigahertz.• Everything that the processor does is kept precisely in time

with the clock.• A processors clock rate is always quoted as that of the

processor however this alone is not sufficient to determine performance. Buses will have their own clock speed and this is generally lower than that of the processor.

• It’s useful to remember that data can only be processed as fast as the speed of its slowest step!

MIPS

• Millions of Instructions per Second is a measure of performance based on the average number of machine code instructions executed.

• Again it is only useful if in all other respects the rest of the test conditions remain the same.

FLOPS

• Floating Point Operations Per Second is a measure of the arithmetical calculating speed of the computer.

• One Megaflop is one million Flops and one Gigaflop is a billion Flops.

• Supercomputers can only get their name if they can operate at speeds of at least one Gigaflop.

Application-based Tests

• Benchmarks provide a standard set of computer tasks designed to allow a computers performance to be measured (think about Windows 7).

• A series of tests produce a set of benchmark scores to measure performance against.

• The performance is generated by the lowest score from all the tests carried out.

• For example, Windows 7 uses a benchmark score of 7.9 to measure performance against. It shows what tasks score well and where performance can be improved.

Factors Affecting System Performance• Data Bus Width.

– Width of the bus determines the quantity of data which the bus can carry.

– A 32 bit data bus can carry 32 bits of data or instructions at a time. Its ‘WORD LENGTH’ is 32 bits.

• Use of Cache Memory.– System performance can be seriously improved by the use of cache memory.

– It is much faster to access data/instructions held in cache memory than in main memory.

– Cache memory is made up of fast static RAM rather than slower dynamic RAM.

• Rate of Data Transfer to and from peripheral devices.– The rate of data transfer to and from peripherals can have a major effect on

system performance.

– The type of interface (connection between PC and peripheral) controls the rate of data transfer. Peripherals ALWAYS work more slowly than the processor.

– USB1, USB2, USB3, IEE 1394, Firewire400, Firewire800.

What's the best way to improve System Performance?

• Increase clock speed.– Over clocking as its known may not be the answer alone due to other factors

outside the processors control.

• Adding More memory.– More data can be held in immediate access (more programs can be open) than

stored in backing storage. The data in main memory can be accessed faster.

• Increasing the Video Random Access Memory.– Memory that is dedicated to graphics and usually found on the graphics ‘card’.

• Adding more Processors.– More processors mean more things can be executed at one time. Most modern

computers come with 2 or more processors per chip now.

• Increasing the address bus width?– Every time a bit is added to the width of the address bus, the range doubles.

Increasing the address bus width increased the range of addresses but has NO effect on system performance.

Current Trends• Increasing Clock Speeds (Over clocking).

– Helps and does work but the increase cannot go on indefinitely and can lead to heat problems (fire!) and increased power consumption.

• Increasing Memory.– Its always a good idea to add more memory where it’s possible.

– Memory requirements for individual applications continue to rise and increased requirement for multiprogramming as well as more memory to hold the computers operating system all continue to rise.

• Increasing backing storage capacity.– This trend also continues to grow. The use of more digital devices continues to

the need for more storage and as photos are taken using hi-resolution cameras, the need for adequate storage grows

– Digital Video uses (in compressed format) around 13 Gigabytes per hour.

Higher Grade Computing

Computer Systems

Unit 2

Computer Structure