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7/24/2019 High Voltage Pspice Manual.pdf
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1
Simulation of High Voltage DC Using PSPICE
SUBMITTED BY:
KUNTAL SATPATHI (07/EE/02)INDRANIL DEBNATH (07/EE/08)SUVRA KANTI PAL (07/EE/18)SOURAV BISWAS (07/EE/22)
SUPRIYO MONDAL (07/EE/35)
HALDIA INSTITUTE OF TECHNOLOGY
SUBMITTED FOR THE DEGREE OF
BACHELOR OF TECHNOLOGY IN THE DEPARTMENT OF
ELECTRICAL ENGINEERING
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2
CONTENTS
Topic Page No.
CHAPTER 1
1.1 Abstract 3
1.2 Half Wave Rectifier Circuit 4
1.3 Full Wave Rectifier Circuit 7
1.4 Voltage Doubler Circuit 9
1.5 Cockcroft Walton Voltage Multiplier Circuit 10
1.5.1 Operation of two stage Cockcroft Walton Multiplier
Circuit
11
1.5.2 Operation of multiple stage Cockcroft Waltonmultiplier circuit
12
CHAPTER 2
2.1 Variation Of Off-load Steady State Voltage Profile
with change in number of stages using schematics.
20
2.1.1 Variation Of Offload Steady State Voltage Profile for
three stage voltage multiplier circuit.
20
2.1.2 Variation Of Offload Steady State Voltage Profile fortwo stage voltage multiplier circuit.
21
2.1.3 Variation Of Offload Steady State Voltage Profile for
single stage circuit.
22
2.2 Miscellaneous Results 23
CHAPTER 3
3.1 PSPICE Simulation Of Cockcroft Walton Circuit (3-
Stage)
24
3.2 Simulation results 25
3.3 Observations for Various types of Loads 26
CHAPTER 4
4.1 CASE STUDY: A 3-Stage Cockcroft Walton Circuit
for a practical load (C=20pF & R=10k)27
4.2 Simulation results 28
4.2.1 Voltage waveform pattern in smoothing capacitor. 29
4.2.2 Voltage waveform pattern in oscillating capacitor 30
4.3 Analysis and discussion 31
4.5 Conclusions 34
4.6 References 35
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3
ABSTRACT
One of the cheapest and popular ways of generating high voltages at relatively low
currents is the classic multistage diode/capacitor voltage multiplier, known as Cockcroft
Walton multiplier, named after the two men who used this circuit design to be the first to
succeed in performing the first nuclear disintegration in 1932. James Douglas Cockcroft and
Ernest Thomas Sinton Walton, in fact have used this voltage multiplier cascade for the
research which later made them winners of the 1951 Nobel Prize in physics for
"Transmutation of atomic nuclei by artificially accelerated atomic particles". Less known is
the fact that the circuit was first discovered much earlier, in 1919, byHeinrich Greinacher, a
Swiss physicist.
For this reason, this doubler cascade is sometimes also referred to as the Greinacher
multiplier.
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4
CHAPTER: 1
HALF WAVE RECTIFIER CIRCUIT
Theory:During the positive half cycle the diode is forward biased and the capacitor gets
charged with the application of the voltage. And during the negative half cycle the diode is
reverse biased and thus the capacitor discharges through the load resistance R. The output
voltage is shown in the figure given.
Circuit Diagram:
In this circuit,
D: diode
R: load resistanceC: smoothing (or reservoir) capacitance
Assumptions:o The leakage reactance of the transformer is negligibleo The internal impedance of the diode is very small during conduction
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Operation:
When the load is absent(R=)During conduction of diod
of the AC voltage Va(t) of the
remains constant at +Vmax, wher
The diode must be dimenif the H.T. transformer is groun
taken across the diode the D.C
known as Voltage Doubler Circu
When the circuit is loaded:
The output voltage does not rem
During conduction period (T=1/
which is represented by,
Q=
I: the mean value of
v(t): the d.c. voltage w
This charge is supplied by the
from Vmax to Vmin over approx
diode (tc=T) show in Figure.
e D, the capacitor is charged to the maxi
HT transformer and the D.C. voltage
as Va(t) oscillates between +Vmaxand
ional, therefore to withstand reverse voled at the terminal B instead of A, and t
. voltage oscillates between 0 and +2
it by Villard.
in constant.
) of the AC voltage a charge Q is transf
=
v(t)dt = IT =
the DC output iL(t),
hich includes a ripple as shown.
apacitor over the period T when the v
mately period T, neglecting the condu
5
um voltage +Vmax
cross the capacitor
max.
tage of 2Vmax. Alsoe output voltage is
max. This circuit is
rred to the load RL,
(1)
oltage v(t) changes
tion period of the
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This charge is also supplied from the transformer within the short conduction period (tc=T).
Therefore
Q= = (2)
As
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FULL WAVE RECTIFIER CIRCUIT
Theory:
A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc voltage
using both half cycles of the applied ac voltage. It uses two diodes of which one conducts
during one half cycle while the other conducts during the other half cycle of the applied AC
voltage.
During the positive half cycle of the input voltage, diode D1 becomes forward biased and
D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The load current
flows through D1 and the voltage drop across RLwill be equal to the input voltage.
Circuit Diagram:
Operation:During the negative half cycle of the input voltage, diode D1becomes reverse biased and
D2becomes forward biased. Hence D1remains OFF and D2conducts. The load current
flows through D2and the voltage drop across RLwill be equal to the input voltage.
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Calculation of Ripple Factor:
= /
= /
=
1.11
1 =0.482
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VOLTAGE DOUBLER CIRCUIT (Developed by Greinacher in 1990):
Both full wave and half wave rectifier circuits produced DC voltage less than AC maximum
voltage. For higher DC voltage, voltage doubler circuit is used.
Circuit Diagram:
During negative half cycle, the capacitor C1is charge through diode D1to voltage Vmax.
During the next half cycle the terminal Y of the capacitor C1 rises to Vmax and hence the
terminal X attains a potential 2Vmax. Thus, capacitor C2 is charged to 2Vmaxthrough D2.
Normally, the voltage across the load is less than 2Vmaxdepending upon the time constant of
the circuit, capacitor C2and the load RLwhich would be discussed in the following chapters.
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10
COCKCROFT WALTON MULTIPLIER CIRCUITS
Introduction
One of the cheapest and popular ways of generating high voltages at relatively low
currents is the classic multistage diode/capacitor voltage multipler, known as Cockcroft
Walton multiplier, named after the two men who used this circuit design to be the first to
succeed in performing the first nuclear disintegration in 1932. James Douglas Cockcroft and
Ernest Thomas Sinton Walton, in fact have used this voltage multiplier cascade for the
research which later made them winners of the 1951 Nobel Prize in physics for
"Transmutation of atomic nuclei by artificially accelerated atomic particles". Less known is
the fact that the circuit was first discovered much earlier, in 1919, byHeinrich Greinacher, a
Swiss physicist.
For this reason, this doubler cascade is sometimes also referred to as the Greinacher
multiplier.
Advantages of Cockcroft Walton Circuit:
Unlike transformers this method eliminates the requirement for the heavy core and the
bulk of insulation required.
By using only capacitors and diodes, these voltage multipliers can step up relatively
low voltages to extremely high values, while at the same time being far lighter and
cheaper than transformers.
The biggest advantage of such circuit is that the voltage across each stage of this
cascade is only equal to twice the peak input voltage, so it has the advantage ofrequiring relatively low cost components and being easy to insulate.
One can also tap the output from any stage, like a multi-tapped transformer. They
have various practical applications and find their way in laser systems, CRT tubes,
HV power supplies, LCD backlighting, power supplies, x-ray systems, travelling
wave tubes, ion pumps, electrostatic systems, air ionizers, particle accelerators, copy
machines, scientific instrumentation, oscilloscopes, and many other applications that
utilize high voltage DC.
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Operation of 2-Stage Cockcroft Walton Circuit:
The Cockcroft Walton or Greinacher design is based on the Half-Wave Series
Multiplier, or voltage doubler. In fact, all multiplier circuits can be derived from its
operating principles. It mainly consists of a high voltage transformer TS, a column of
smoothing capacitors (C2, C4), a column of coupling capacitors (C1, C3), and a series
connection of rectifiers (D1, D2, D3, D4). The following description for the 2 stage CW
multiplier assumes no losses and represents sequential reversals of polarity of the source
transformer TSin the figure shown below. The number of stages is equal to the number of
smoothing capacitors between ground and OUT, which in this case capacitors are C2and C4.
Operation:
1. Ts=Negative Peak: C1charges through D1to Epkat current ID12. Ts=Positive Peak: Epkof Tsadds arithmetically to existing potential C1, thus C2charges to 2Epk
through D2at current ID2
3. Ts=Negative Peak:C3is charged to 2Epkthrough D3at current ID3
4. Ts=Positive Peak: C4is charged to 2Epkthrough D4at current ID4.Output is then 2n*Epkwhere N = number of stages.
CW:stands for Cockcroft-Walton
.
.
,
.
,
.
.
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Operation of n stage Cockcro
When the HV output terminal isWhen B is positive w.r.t A, C1
point attains a voltage of 2Vmax
In the next half cycle , when B i
N falls and becomes less than p
half cycle, A is +ve w.r.t B and
Finally, all the capacitors C1, C2
t Walton Circuit:
open circuited (I=0):is charged to Vmax through D1 and wh
nd C1is charged to 2Vmaxthrough D1
.
s again +ve w.r.t A, potential of A falls
tential of M. Hence C2 is charged thro
potential of M and N rise. Thus chargi
Cn and C1, C2...Cn are charged.
12
n A is +ve, the M
and so, potential of
gh D2 . In the next
g C2through D2.
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13
Let us consider the operation of the 3-stage Cockcroft Walton Circuit (n=3):
Circuit Diagram:
Voltage profiles of the Oscillating capacitors C1, C2, C3are v(C1), v(C2), v(C3):
For 3 cycles (0-60ms):
Where:
v(1): input voltage
v(2), v(3), v(4) are voltage across smoothing capacitors C1, C2, C3respectively.
Time
0s 10ms 20ms 30ms 40ms 50ms 60ms
V(2) V(3) V(4) V(1)
-1.0KV
0V
1.0KV
2.0KV
-1.5KV
2.5KV
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For 100 cycles (steady state operation)
Where:
v(2), v(3), v(4) are voltage across smoothing capacitors C1, C2, C3respectively.
Voltage profiles of the Smoothing capacitors C1, C2, C3are v(C1), v(C2), v(C3):
For 3 Cycles:
Where:
v(1): input voltage
v(5), v(6), v(7) are voltage across smoothing capacitors C1, C2, C3respectively.
Time
0s 0.2s 0.4s 0.6s 0.8s 1.0s 1.2s 1.4s 1.6s 1.8s 2.0s
V(2) V(3) V(4)
-4.0KV
0V
4.0KV
8.0KV
Time
0s 10ms 20ms 30ms 40ms 50ms 60ms
V(1) V(5) V(6) V(7)
-1.0KV
0V
1.0KV
2.0KV
-1.5KV
2.5KV
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For 100 cycles:
Where:
v(5), v(6), v(7) are voltage across smoothing capacitors C1, C2, C3respectively.
It is seen that:
The potential across C1, C2Cn are oscillatory due to the supply voltage
oscillation, this column is known as oscillating column.Here in this case the
potential at node 2 varies from 0 to 2.2 kV, at node 3 from 2.2kV to 4.4kV and at node
4 from 4.4kV to 6.6kV.
The potential across C1, C2
..Cn
remain constant with reference to ground
potential; this column is known as smoothening column.Here in this case the
potential at node 5 is fixed at 6.6kV, at node 6 is fixed at 4.4kV and at node 7is fixed
at 2.2kV.
The voltage across all capacitors is of DC type, the magnitude of which is 2V max (in
this case 2.2kV)across each stage, except capacitor C1where it is Vmaxonly.
Every diode D1, D2Dn , D1, D2
,Dn is stressed with 2Vmax or
twice of AC peak voltage.
The H.V output will reach a maximum voltage of 2nVmax (in this case 6.6kV across
node 5).
Time
0s 1.0s 2.0s 3.0s 4.0s 5.0s 6.0s
V(5) V(6) V(7)
-4.0KV
0V
4.0KV
8.0KV
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1
When the H.V output terminal is loaded (I>0):If the generator supplies a load current I, the output voltage will never reach the value
2nVmax ; the output voltage will have ripples. Therefore, we have to calculate two quantities-
Ripple Voltage(V)
Voltage Drop(V0)
Calculation of Ripple Voltage (V):-
The output voltage on loaded condition is shown:
At time instant t1, when v(t) is at +Vmax,the rectifiers D1,D2
.,Dn
just stopped to
transfer charge to the smoothing column, C1,C2
..Cn
. The charging of the
smoothing column takes place during the positive half-cycle.
During the negative half-cycle, the rectifiers D1, D2
.. Dn
conduct and the
oscillating column is charged.
Let,
q=charge transferred to the load per cycle, thus charge comes from smoothing column;
f=supply frequency;
T=time period;
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I=load current;
q=I/f=IT
If no charge would be transferred during T from this stack via D1, D2,Dnto the
oscillating column, the peak to peak ripple will be
V= 2
q
=
n
iC
1)'/1(
However, as the charge is transferred by D1, D2..Dnand the smoothing column is
discharged, the total ripple will be
V=f
I
2(
'
1
Cn+
'1
2
Cn+..+
'1C
n)
From this, we can see that lowest capacitors are responsible for most ripple and it would be
desirable to increase the capacitance in the lower stages.
However, this is very inconvenient, as a voltage breakdown at the load would completely
overstress the smaller capacitors within column.
So, equal capacitance values are used i.e. C1=C2==Cn-1=Cn=C; & the ripple is
V=f
I
2[
C
1+
C
2++
C
n]
V= fCI
2 2
)1( +nn
V=fC
nIn
4
)1( +
Calculation of Voltage Drop (V0)
In order to find the voltage drop, we have to understand the charge transfer process. We
consider two cycles of operation:-
(a)Charging cycle: charging of smoothing column through oscillating side.
(b)Transfer cycle: charging of oscillating column through smoothing side.
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1
(a)Charging cycle: During the positive half-cycle, the voltage at o is 2nVmax.This
discharges through RL and say the charge lost is q=IT over the cycle. This must be
regained during the charging cycle for stable operation. So, Cnmust be supplied a
charge q from Cn-1. For this, Cn-1must acquire a charge 2q from Cn-2and in this way
C1must have a charge of nq. In this cycle, diodes D1, D2,Dn conduct.
(b)Transfer cycle: During the negative half cycle, the diodes D1, D2Dn conduct.
Here Cn-1transfer q charge to Cn
, Cn-2
transfer 2q charges to Cn-1
and in this way, the
supply provides nq charges.
To calculate the voltage drop, we have to find the difference between the no-load
voltage 2nVmaxand the on-load voltage.
Let C1=C2=..=Cn-1=Cn=C
Now capacitor C1is charged upto
(2nVmax-C
nq)= 2nVmax-
fC
nI
Vn=fC
nI=
C
nq= (2n-n )q/C (i)
Capacitor C2 is charged up to (2nVmax-C
nq)-(n-1)q/C-
C
nq
Vn-1= fC
I
[2n+ (n-1)] = C
q
[2n +(n-1)] (ii)
Similarly,Vn-2=C
q[2n+2(n-1) + 2(n-2) ](iii)
V1=C
q[2n+2(n-1)+2(n-2)+.+2.3+2.2+2.1] (iv)
By summation the voltage drop becomes,
V0= (Vn+Vn-1++V2+V1)
V0=C
q/3n
3+n
2/2-n/6)=
fC
I(2/3n
3+n
2/2-n/6)0
C
q
+ nnn
6
1
2
1
3
2 23 fC
I
+ nnn
6
1
2
1
3
2 23
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1
Here also it is seen that most of the voltage drop is due to the lowest stage capacitors
C1, C2etc. Hence, it is advantageous to increase their values proportional to the no. of
stages from the top.
For large values of n>=5,2
2n&
6
nterms will become small compared to
3
2 3nand may
be neglected.
V0=fC
I
3
2 3n
So, the maximum output voltage is given by,
Vomax=2nVmax-fC
I
3
2 3n
From this it is seen that for a given n,f and C. The output voltage decreaseslinearly with load current I.
However, for a given load, the output voltage rises initially with the no. of stages n,
reaches a maximum value and even decays if n is too large. This optimum no. of
stages can be found as
Vomax=2nVmax-fC
I
33
2n
For maximum Vomax,dn
d[ Vomax]=0
2Vmax-fC
I* 23*
3
2n =0
nopt=I
fCVmax
So the maximum output voltage,
(Vomax)max=I
fCVmax4Vomax)max=
I
fCVmax4/3 Vmax
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20
CHAPTER-2
VARIATION OF OFFLOAD STEADY STATE VOLTAGE PROFILE WITH
CHANGE IN NUMBER OF STAGES (Using SCHEMATICS)
1.
Number Of Stages =3
v(1)= input voltage, v(10)= output voltage
Input voltage: 50V
Theoretical value of steady state output voltage: 300V
Practical Value of Steady state output voltage: 296.761V
% Error=.
*100=1.08%
Time required to reach steady state= 1.748s
Time Constant= 241.74 ms
Time
0s 0.2s 0.4s 0.6s 0.8s 1.0s 1.2s 1.4s 1.6s 1.8s
V(10) V(1)
-100V
0V
100V
200V
300V
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2.
Number Of Stages=2
v(1)=input voltage , v(8)=output voltage
Input voltage: 50V
Theoretical value of steady state output voltage: 200V
Practical Value of Steady state output voltage: 197.85V
% Error=.
*100=1.072%
Time required to reach steady state= 1.0249s
Time Constant= 103.42 ms
Time
0s 100ms 200ms 300ms 400ms 500ms 600ms 700ms 800ms
V(8) V(1)
-100V
0V
100V
200V
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3.
Number Of Stages=1
v(1)= input voltage, v(6)= output voltage
Input voltage: 50V
Theoretical value of steady state output voltage: 100V
Practical Value of Steady state output voltage: 98.93V
% Error=.
*100=1.07%
Time required to reach steady state= 186.61ms
Time Constant= 23.83 ms
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms
V(6) V(1)
-50V
0V
50V
100V
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MISCELLANEOUS RESULTS:
1.
Percentage Steady State error v/s Number of stages
Percentage Steady State Error Number of Stages1.07 1
1.072 2
1.08 3
2.
Time Constant v/s Number of stages
Time Constant (ms) Number of Stages
23.83 1
103.42 2
241.74 3
1.05
1.0
1.05
1.0
1.05
1 2 3
0
50
100
150
200
250
300
1 2 3
()
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CHAPTER-3
PSPICE SIMULATION OF COCKCROFT WALTON CIRCUIT (3-Stage):
Circuit Diagram:
Program:Cockcroft-Walton Circuit
V 2 0 sin(0 220 50 0 0)R1 1 2 0.3
L1 1 0 20mHL2 3 0 500mHK L1 L2 0.98
R2 3 4 0.3
C1 4 5 500u
C2 5 6 500uC3 6 7 500u
C4 8 9 500u
C5 9 10 500uC6 10 0 500u
D1 0 5 DMOD
D2 5 10 DMODD3 10 6 DMOD
D4 6 9 DMOD
D5 9 7 DMODD6 7 8 DMOD.MODEL DMOD D(Is=2.2e-15 BV=8000)
.tran 1s 50s uic
.probe V(1) V(3,0) V(8,0)
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.end
Output:
Observations:
v(8,0)=output voltage
Input Voltage: 220V
Stepped up Voltage at Transformer secondary: 1.1kV
Theoretical Value of Steady State output Voltage: 6.6kVPractical Value of Steady State output Voltage: 6.298kV
% Error=
*100=4.57%Time Constant=185 ms
Time required reaching steady state: 1.414s
Time
0s 5s 10s 15s 20s 25s 30s 35s 40s 45s 50s
V(8,0)
0V
2.0KV
4.0KV
6.0KV
8.0KV
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2
Observations for Various types of Loads:
Type of Load Value of
Capacitor
Value of
Resistor
()
Steady State
Output
Voltage (kV)
Time
Required to
reach Steady
State (s)
Remarks
(at steady
state )
1. Purely Resistive - 100k 6.28 1.48 Heavy
Ripples
present
2. Purely Capacitive
i) Line Insulators 20pF - 6.353 1.6 No Ripples
ii) Bushings 300pF - 6.3221 1.16 No Ripples
iii) Power
Transformers
(1MVA)
10000pF
-
6.2481 1.08 No Ripples
v)Underground
Cables (per m)
a) ImpregnatedPaper
Insulators
250pF
-
6.2425 1.183 No Ripples
b)GaseousInsulators 75pF - 6.2853 1.408 No Ripples
3.Practical Load
a) Line Insulators
20pF
10k 5.7181 1.970 High Ripples
100k 6.2628 1.885 Slightly Less
than Above
1000k 6.3473 1.780 Fewer
Ripples
b) Bushings
300pF
10k 5.6990 1.302 High Ripples
100k 6.2675 1.249 Slightly Less
Ripples
1000k 6.2968 1.181 Fewer
Ripples
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2
CHAPTER-4
CASE STUDY: A 3-STAGE COCKCROFT WALTON CIRCUIT FOR A
PRACTICAL LOAD (C=20pF & R=10k)
Circuit Diagram:
PSPICE Program:Cockcroft-Walton Circuit
V 2 0 sin(0 220 50 0 0)R1 1 2 0.3
L1 1 0 20mH
L2 3 0 500mHK L1 L2 0.98
R2 3 4 0.3
C1 4 5 500uC2 5 6 500uC3 6 7 500uC4 8 9 500u
C5 9 10 500uC6 10 0 500u
D1 0 5 DMOD
D2 5 10 DMOD
D3 10 6 DMODD4 6 9 DMOD
D5 9 7 DMOD
D6 7 8 DMODC7 8 0 20p
R3 8 0 10k
.MODEL DMOD D(Is=2.2e-15 BV=8000)
.tran 1s 5s uic
.probe V(1) V(3,0) V(8,0)
.end
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2
OUTPUT:
Terminal Voltage Profile:
v(8,0)= terminal voltage
Load Current Profile:
i(R3)=load current
Time
0s 0.5s 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 4.0s 4.5s 5.0
V(8,0)
0V
2.0KV
4.0KV
6.0KV
Time
0s 0.5s 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 4.0s 4.5s 5.0s
I(R3)
0A
200mA
400mA
600mA
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Voltage waveform pattern in the smoothing capacitorsFrom the circuit diagram of the 3-stage Cockcroft Walton circuit we see that
C1, C2, C3are oscillating capacitors &
C4, C5, C6are smoothing capacitors.
The Voltage waveform of the Smoothing Capacitors C4, C5, C6are v(C4), v(C5), v(C6) for 8-
input cycles (0-160ms) and input is v(3,0)
The Voltage Waveform of the Smoothing Capacitors C4, C5, C6is v(C4), v(C5), v(C6) at
steady state:
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms
V(3,0) V(C4) V(C5) V(C6)
-2.0KV
0V
2.0KV
V(C6)
V(C5)
Input Voltage
V(C4)
Time
0s 0.2s 0.4s 0.6s 0.8s 1.0s 1.2s 1.4s 1.6s 1.8s 2.0s
V(C4) V(C5) V(C6)
0V
0.5KV
1.0KV
1.5KV
2.0KV
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Voltage waveform pattern in the oscillating capacitorsThe Voltage Waveform across the Oscillating Capacitors C1, C2, C3are v(5,4), v(6,5), V
v(7,6) for 8-input cycles (0-160ms) and input is v(3,0)
The Voltage Waveform of the Oscillating Capacitors C1, C2, C3is v(5,4), v(6,5), v(7,6) at
steady state :
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms
V(3,0) V(5,4) V(6,5) V(7,6)
-2.0KV
-1.0KV
0V
1.0KV
2.0KV
Time
0s 0.2s 0.4s 0.6s 0.8s 1.0s 1.2s 1.4s 1.6s 1.8s 2.0s
V(5,4) V(6,5) V(7,6)
0V
0.5KV
1.0KV
1.5KV
2.0KV
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Observations:
Ripples : Heavy Ripples Present
Input Voltage : 220V
Stepped Up Voltage at Transformer secondary : 1.1kV
Theoretical Value of Steady State output Voltage : 6.6kV
Practical Value of Steady State output Voltage : 5.7181kV% Error :
. *100=13.36%
Time Constant : 1.970 ms
Time required reaching steady state : 165.9 ms
Steady State Current : 570.4mA
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Calculation of various factors:
1. Calculation of Output Voltage:
We know that the output voltage of the Cockcroft Walton circuit is given by:
Vout= 2nEp- Vdrop
Where,
o Ep is the input to the Cockcroft Walton Circuit (In this case the secondary of thetransformer),
o n is the number of stages,
o Vdropis the Voltage drop under load.
Vdropis given by,
Vdrop= ( )nnnfC
Iload+
23 346
Here,
Practical Value of the output voltage is:
Vout(practical)=5.7181kV
Theoretical Calculations:
n=3,
Ep=1.1kV,
C=500uF
f=50Hz
Iload=570.4mA
So,
Vdrop= 882.22 V (from VdropEquation)
Eout(theoretical)=6600-882.22=5717.78V or, 5.7178kV
%Error= %00525.0100*7178.5
7181.57178.5=
2. Calculation of Ripple Voltage (V):
The expression of the ripple voltage is given by,
V=fC
nIn
4
)1( +
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Here,
I=570.4mA
n=3
f=50Hz
C=500F
So, theoretical value of the ripple voltage is:
Vtheoretical=68.45VPractical Value of the ripple voltage:
For this the output voltage waveform in the steady state is to be considered.
The output voltage waveform at steady state is given by:
v(8,0)= steady state voltage profile
From the output waveform:
We see that,
Value of the voltage at crest Vcrest= 5.7743kV
Value of the voltage at trough Vtrough= 5.6422kV
The ripple voltage is given by:
Time
2.050s 2.100s 2.150s 2.200s 2.250s 2.300s2.008s
V(8,0)
5.625KV
5.750KV
5.875KV
5.536KV
(2.1226,5.6422K)
(2.1071,5.7743K)
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V=2
6422.57743.5 =0.06605kV=66.05V
So, Vpractical=66.05V
%Error=45.68
05.6645.68 *100=3.5%
CONCLUSIONS:
The PSPICE schematic is limited for the output voltage of the range up to 300V only,
after that the output is not satisfactory due to the low breakdown voltage of the diodes
used.
For getting the output voltage greater than the 300V rather in kVs the PSPICE
ORCAD is used where the breakdown voltage can be defined as per requirements.
At no load condition the output does not match with the prescribed theoretical output
because of the voltage drops in the diodes.
More is the output voltage the steady state error decreases due to negligible effect of
the diode voltage drops with respect to the output voltage.
Ripples are present (at steady state) for the resistive load and the capacitive load (with
less load resistance) due to less time constant and so lesser time required for charging
and discharging of the capacitors.
No load voltage is more than the terminal voltage on load due to voltage drop across
the load.
The steady state error increases slightly with number of stages due to increase in
number of diodes and hence voltage drops across them. The time constant increases with the number of stages as the number of capacitor in
parallel increases and hence the ripples decreases.
As the load capacitance value increases the ripples decrease and the time required to
reach the steady state also decrease.
When load capacitance value is kept fixed with the resistance varied the ripples
increase with decrease in resistance value, the steady state voltage increase with the
increase in resistance and time required to reach steady state reduces with increase in
resistance. In the case study the steady state error in the output voltage profile is very low and
accounts mainly for the voltage drops across the diodes.
In the case study the error in the ripple factor calculation is mainly due to the fact that
the transformer output voltage is not perfectly sinusoidal.
From the voltage profile of the oscillating and the smoothing capacitors we see that
all the capacitors are charged to 2*Emaxexcept C1which is an oscillating capacitor.
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REFERENCES
High Voltage Engineering by C.L. Wadhwa
High Voltage Engineering by M.S. Naidu, V. Kamaraju
www.wikipedia.com
www.blazelabs.com
www.google.com