High Voltage Power Supply - PhysicsNostalgiaphysicsnostalgia.com/HV/HVPS/1st300kvMarxPS.pdfU2 U1 100K VR1 C6 R3 R4 C7 C8 5 0.1 C9 R5 5 C 0 0.022 VR2 R6 C11 2.2K VR4 + Approximate Schematic-40

High Voltage Power Supply

1st 300KV Marx

Notes: Latest HV Power Supply for Mini-Marx 14 Feb. 01a Eliminate Sustained Arc

C112VDC IN R1L1

Q1

D1

D2

D3

C2 C3

C4

D4

MOV 1

Electronics Top View Component Physical Layout

R2U1U2U3

T1 Primary

T1 Primary

VR1Duty Cycle Adj

C5

L1 / Circuit RemovedCircuit Board Bottom View

C6

R3

R4

C7

C8

C9C10

VR2PRF adj.

R6

C11

C12

VR4VR3t- INH

R5

555

4 8

3

1 6 7

555

4 8

3

1 67

2.2K10K

DUTY CYCLE

0.01

2

10K

1000pf

10K0.01

2

2.2K

PRF

0.01

~ 12.5KHZ

80 to 95 %

12V @ .APWR IN

+

0.047 50µ f

L1

T1

Q1

D2

V14681U

10T

IRGPH40U

0.1

0.1C1

R122Ω

D18812

UF1007D3

C2 C3

MOV 1

630VDC

C4

D4UF1007R2 18Ω

U1U2555

4 8

3

1 67

100K2

100K

0.01

U3

VR1

+1µ fC5 C6

R3

R4

C7

C8 5

0.1C9

R5

5

C10

0.022

VR2R6

2.2KC11

C12

VR3

VR4

t - INHIBIT

To HV Multiplier

Switching (Flyback) PS Circuit Diagram


T1 HV Multiplier

-20 0 20 40 60 80 100msec U3 HV inhibit/ enable Waveform

-2

0

2

4

6

8

10

12

14

volts

U3

outp

ut

U3 pin 3 Waveform

Enables \ inhibits switchingoscillator U2

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec Switching Osc. U2 Waveform

-2

0

2

4

6

8

10

12

14

volts

U2

outp

ut

Switching Osc. Waveform( U2 pin 3) triggers U1

Waveforms of U1 - 3 / Circuit board only => not connected to Q1

-20 0 20 40 60 80 100µ sec U1

-2

0

2

4

6

8

10

12

14

16

volts

out

put U

1

Q1 gate drive @ pin 3 of U1which sets the duty cycle


Transformer Example # 27-sep-99a (Note that the transformer used in this PS is labeled: 4 Oct 99 and is not an exact copy)

Info from notebook 4 Oct. 99:

- ferrite from computer PS transformer (no markings on core). .. Appears to be type 3E8

- primary 10T => 20 gauge - secondary 210T => 28 gauge

- core E core top view

0.25”0.5”

0.75”

1.75”

Side View

Gap set by one viewgraph sheet thickness

- coil form bobbin

Removable core form for making coil form

Etc.Separation exaggerated

Super glue soaks between layers (care taken to ensure that removable core is not glued to sheet.

End view

1 X 12 “ high temperature viewgraph sheet

Crease edges to form

Coil form when dried


Insulator for HV output

1st layer => coat with super glue

40 T / layer

2 layers of viewgraph sheet soak with super -glue & fill all spaces

Etc until get ~210 TFill valleys till flush

Last layers

Primary 10T

Secondary ~ 210T


_ Typically have 40 - to - 43 T per layer & 5 layers to get ~ 210T for the secondary

Comment:As mentioned previously many of the ferrite cores experimented with were obtained from PC switching

PS. This involved removing the core from the winding which is very difficult to do. A limited number of used ferrites were used for the initial prototypes; as this supply diminished the above method was necessary. Consequently various transformers were constructed having various core size and types consequently U2 & 3 adjustments varied as well as performance.

- Another physical example (ferrite from PC switching PS):

primary

SecondaryHV out

Secondary GND

Note how super glue fills the coil

0.4375

1.5”

Note round core (easier to fabricate)


- Another example using an unused PQ core:Top View


Waveforms after Circuit Card was re-installed in the HVPS (20Feb.01):

-4 -2 0 2 4 6 8 10 12 14 16 18µ sec

-100

0

100

200

300

400

500

600

-20 0 20 40 60 80 100µ sec Q1 gate drive

-2

0

2

4

6

8

10

12

volts

-20 0 20 40 60 80 100µ sec U1 Pin 3

-2

0

2

4

6

8

10

12

volts

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec U2 pin 3

-2

0

2

4

6

8

10

12

volts

-20 0 20 40 60 80msec U3 pin 3

-2

0

2

4

6

8

10

12

volts

Flyback Counter EMF @ T1 primary

Waveform @ Q1 GATE

Waveform @ U1 pin 3

Waveform @ U2 pin 3Waveform @ U3 pin 3

Comment: For some reason after re-installing the circuit the waveform timing has changed

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec. HV Drive Off

-2

0

2

4

6

8

10

12

14

IGBT

Gat

e Dr

ive

Volts

-4 -2 0 2 4 6 8 10 12 14 16 18µ sec. (forgot to use short GND clip => tail ring?)

-10

-5

0

5

10

15

20

25

Seco

ndar

y O

utpu

t KV

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec note slope between pulses & noise "Miller effect"

-2

0

2

4

6

8

10

12

14

IGBT

Gat

e Dr

ive

(HV

activ

ated

) Vol

ts

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec. (Ch2 / CH1 => 27sep99c.txt)

-10

-5

0

5

10

15

20

25

Seco

ndar

y HV

Out

KV

Notes: Xformer #27-sep-99a \ Waveform of experimental circuit .

Gate drive to IGBT usedfor driving Xformer #27-sep-99a

Notes: HVPS #2\ Example of Small PS 21 Feb. 01a

555

4 8

3

1 6 7

555

4 8

3

1 67

2.2K10K

DUTY CYCLE

0.01

2

10K

1000pf

10K0.01

2

2.2K

PRF

0.01

~ 12.5KHZ

12V @ .APWR IN

+

L1

T1

Q1

10T

R110Ω

C2 C3

R2

U1U2

100K

VR1

C6

R3

R4

C7

C85

0.1C9

R5

5

C10

0.022

VR2R6

2.2KC11

VR4+

Approximate Schematic

-40 -20 0 20 40 60 80 100 120 140 160 180µ sec U1 pin3

-2

0

2

4

6

8

10

12

volts

-4 -2 0 2 4 6 8 10 12 14 16 18µ sec @ T1 primary

-100

0

100

200

300

400

500

600

700

volts

-4 -2 0 2 4 6 8 10 12 14 16 18µ sec T1 secondary

-4

-2

0

2

4

6

8

10

12

14

kv

With 2X Multipliernot loaded

Note: T1 ~ 21:1 ratio =>( pri = 650) * 21 = 13650

-2 -1 0 1 2 3 4 5 6µ sec T1 secondary

-4

-2

0

2

4

6

8

10

12

14

kv

Not much time to rectify here

Notes: HVPS #2\ Example of Small PS 21 Feb. 01a

Waveforms when the output is loaded

-2 0 2 4 6 8µ sec T2 secondary loaded with 33.3M resistor to GND

-4

-2

0

2

4

6

8

10

12

kvT1 Secondary w\ 33.3M resistor Load

-2 0 2 4 6 8µ sec T1 secondary with 2X Multiplier output loaded with 33.3M

-2

-1

0

1

2

3

4

5

6

7

8

9

kvT1 Secondary W\ 33.3M @ 2X output

Note core saturation = loss

-2 0 2 4 6 8µ sec T1 primary W\ 33.3M @ 2x output

-100

0

100

200

300

400

500

600

volts

T1 Primary W\ 33.3M @ 2X output

Note core saturation = loss

Loss mechanisms believed to be due to: - core saturation - small ∆t at peak (when not saturated) for 70nsec UF1007s

Possible improvements to increase efficiency - increase air gap in core - add caps @ primary & sec to increase width

Notes: 12 Jan. 00 Notes from Notebook\ PWR Measurements (HVPS & 16 Stage Marx) 26 Feb 01A P1

Purpose: The 2nd HVPS utilizing cyclic HV inhibit was initially tested, 12 Jan. 00, with a 16 stage Marx

generator; the experimental setup is shown below:

HVPS

Fluke measure V&A

12V battery

HV probemonitor V charge

16 stage Marx

HV probe monitor Marx output Tek 280

Close up of experiment:

To Ch 1

Ch 2

Close up of HVPS:


-40 -20 0 20 40 60 80 100 120 140 160 180nsec. New 16 Stage Marx / Direct Output (no peaking gap) FN12JAN00A

-350

-300

-250

-200

-150

-100

-50

0

50

Out

KV

-40 -20 0 20 40 60 80 100 120 140 160 180nsec FN12JAN00B

14

15

16

17

18

19

20

21

Cha

rge

Volta

ge K

V

Ch 1

Ch 2

1st Waveform Set:

Vcharge ~ 18KVV Marx ~ 280KV

18* 16 = 288

Note: although U3 was initially set for 90 ms on and 10 ms off the actual PRF for self breakdown was ~ 8 hz.

16 stages => 2700pf/4= 675pf/stage; equivalent C parallel = ~ 0.011µf

@ 18kv E = 0.5(CV2)= 1.782 J/pulse

1.782J* 8hz =14.256 W

HVPS input current = ~ 4.5A @ ~ 11.8V =>53.1W 27% PWR in -to - PWR to Marx

Photos\ experimental setup another view


2nd Waveform Set:

V ch ~= 17.6kv

V Marx ~= 280Kv

16 * 17.6 = 281kv

1.7J/pulse * 8hz = 13.6 W

-40 -20 0 20 40 60 80 100 120 140 160 180nsec.New 16 Stage Marx/ Direct Outout FN12JAN00C

-350

-300

-250

-200

-150

-100

-50

0

Out

KV

Ch 1

-40 -20 0 20 40 60 80 100 120 140 160 180nsec FN12JAN00D

13

14

15

16

17

18

19

20

21

char

ge v

olta

ge K

V

Ch 2

-100 -50 0 50 100 150 200 250 300 350 400 450msec Free Running Self Breakdown (no trigtron)

0

2

4

6

8

10

12

14

16

18

20

char

ge v

olta

ge K

V

Waveform \ Vch \ get PRF:

Notes: HVPS w/inhibit\ More info 26 Feb. 01B

12V in T1 primary 1

T1 primary 2

Top View \W\O top lid

IGBTCopper Heat Sink

Heat sink (electrical insulator)

Heat Sink Paste

Side View

Aluminum Case

Case: Hammond # 2699 Cast # 1590A 3.62X1.8X1.22 in

Copper Heat Sink: ~ dimensions 1.5X 1 X 0.25”

Actual T1 used ID 4OCT99 added information; core and primary; secondary is the same

Core Side ~ 1.6 X 0.56” Core Top 1.6 X 1.6”

Primary => 2 wire / turn => 10 turnswires connected @ each end

Voltage Multiplier:

2X output500pf.

Ea. Capacitor Philips Series DD High Voltage Disc CeramicType DD60-102 1000pf @ 6KV; two ea connected in series

Ea. Diode = 20 UZ1007connected in series

Top view UZ1007 diodes glued to view graph plastic

Super glue together& line up

Top diodes

Bottom diodes

**Note: surfaces must be covered with adequate insulation to prevent corona unbalancing series connection distribution.

**

**

To allow slack the low frequency was set at 10Khz for C fixed; hence:

Notes: HVPS\ NE555 Design U1,2, & 3 27 Feb. 01A P1

Fig. 1Fig. 2

The HVPS was initially designed and tested in a modular component fashion to facilitate troubleshooting. For example the IGBT was tested with a transformer using a function generator as the gate drive (PRF and duty cycle); which was replaced with two 555s. When used with a Marx it was discovered that cyclic enable/inhibit was necessary to prevent troublesome sustained arcing; resulting in an additional 555. Since most of the component functional parameters have been determined it would appear that U1,2, &3 could be replaced with a single switching PS IC controller chip in a future design.

U2 Switching Frequency Osc. : The active devices (U1,2,&3) used in the HVPS utilizes the 555 timer. Fig. 1 provides the pin out and Fig. 2

the functional block schematic. The two comparators have one of the sense inputs connected at 1/3 and 2/3 Vcc of the resistor divider 3R approximating the charge and discharge time constant (T=RC). Fig. 3 shows the 555 configured in osc. mode. The other comparator inputs (threshold & trigger) are used in the osc. timing; because the sense points are fixed (1/3 & 2/3 Vcc) the osc. frequency is independent of Vcc. The HVPS is designed to operate at 12VDC which is well within the maximum Vcc of ~ 16V.

The optimum operating switching frequency was experimentally determined to be in the 12 to 20Khz range. The value for RA + 2RB was determined using Fig. 4 to be ~ in the 2 to 10K range for C = 0.01µf. The frequency is given as:

Fig. 3

Fig 4

F = 1.44

(RA + 2RB )C

RA + 2RB =

1.44

(1E4)(1E-8) = 14.4ΚΩ

and the high frequency at 50Khz:

RA + 2RB = (5E4)(1E-8) = 2.88K

1.44

For the 1st iteration if RA varies from ~ 0 to 12K; then 2RB = ~ 3K; however some minimal RA resistance is needed to protect and isolate the discharge from Vcc. If the upper frequency is reduced to ~ 20 to 30Khz then RA + 2RB = ~ 6K.

D = RB

RA + 2RB

From the above equation to get trigger pulses from U2’s output @ pin 3 some D value is required; hence a finite RB is needed. The minimum value (that includes at least the pulse rise and fall time) was experimentally determined to be ~ 2K. The resultant circuit at the right indicates RB = R6 = 2.2K and RA = R5 + VR2

555

4 8

3

1 67

10K0.01

2

2.2K

PRF~ 12.5KHZ

U2

R5

5

C10

0.022

VR2R6

2.2KC11

enab/inh

out

Vcc

Notes: HVPS\ NE555 Design U1,2, & 3 27 Feb. 01B P1

After much experimentation for the particular system application decision was made to operate the switching PS in a cyclic manner (enable/ inhibit). The PS would run full blast charging the Marx generator to a certain value (for self breakdown charge to this value); after firing the PS would be inhibited long enough for the plasma to die sufficiently so that no sustained arcing occurred. This investigator measured these parameters using an early free run representative prototype PS and Marx.

..

~ 90ms

~ 11ms

expanded

The diagrams at the right are from this investigators notebook in order to determine U3’s duty cycle. The top indicated about 90msec to charge a representative 16 stage Marx bank. The DSO sweep was increased for viewing several msec/div resolution. Sustained SG arcing of the Marx was encouraged and discouraged in order to determine the plasma lifetime. The bottom expanded waveform drawing indicates that ~ 11msec inhibit is required. With these parameters at hand U3 components could be determined.

Design was started by letting C = 1µf and free run frequency in the 5 - to - 10 hz range; @ 5hz:

RA + 2RB = (5)(1E-6) =

1.44288K

@ 10 hz RA + 2RB = 144K

Copying the information from the notebook; the off time (T2) was assumed to be conservatively 15 - to - 100msec. And an on time (T1) of ~ 90msec. The equations for T1 & T2 are given:

T1 = 0.693(RA + RB )C T2 = 0.693( RB )C

T2 = 15msec. = 0.693(RB) 1µf => RB = 21.6K

T1 = 144.3K; total period T = T1 + T2 = 0.693(RA + 2RB )C

@ 10 hz Ra + 2(21.6E3) = 144E3 => RA = ~ 100K

RA +.RB = ~ 122K

@ 5hz RA + 2RB = 288K ; RB = 94K

To simplify the design both RA & .RB use 100K POTS as shown in the schematic below:

555

4 8

3

1 67

100K2

100K

0.01

U3

+1µ fC5

C12

VR3

VR4

t - INHIBIT

to U2 trig.

Vcc

Note that pin 3 out drives U2’s reset (not trig in ) pin 4 for enabling \ inhib. The switching frequency oscillator.

Notes: HVPS\ NE555 Design U1,2, & 3 27 Feb. 01B P2

U1 IGBT GATE Driver:

U1’s output drives the IGBT GATE; it provides the duty cycle timing which is adjusted (at a given PRF) to maximize I in the primary of T1. The circuit at the right illustrates the 555 configured as a monostable oscillator. The high output state time is given:

t = 1.1 RAC

Using the same value C as for U2 (0.01µf) and assuming t < T of U2 then:@ 50Khz => t = 20µsec : @ 10Khz t = 100µsec

then @ 50khz RA= ~ 2K; @ 10khz RA= ~ 10k; the circuit for U1 is:

555

4 8

3

1 6 7

2.2K10K

DUTY CYCLE

0.01

2

10K

1000pf

10K

0.01

80 to 95 %

U1

VR1

C6

R3

R4

C7

C85

0.1C9

VR2

IGBT Gatepin3 U2

Vcc

If VR1 is adjusted to 0 then RA = 2.2K => ~ 50khz; if VR1 is set @ max. 10k then RA = 12.2K => f ~ < 10khz.

The trigger input sets the internal 555 RS flip-flop causing C6 to discharge. If the trig. input doesn’t pulse then pin 3 out could remain high causing Q1 to stay on and quickly overheat and burn out. To prevent this from happening the trigger signal from U2 is capacitor coupled to pin 2; R4 provides the pull up.

Pin 5 is shunted AC wise to GND with C9 to prevent noise spikes entering and causing pre-triggering.

Documents

High Voltage Power Supply - PhysicsNostalgiaphysicsnostalgia.com/HV/HVPS/1st300kvMarxPS.pdfU2 U1 100K VR1 C6 R3 R4 C7 C8 5 0.1 C9 R5 5 C 0 0.022 VR2 R6 C11 2.2K VR4 + Approximate Schematic-40