High-speed Serial Interface - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/Lect11_CPPLL_2.pdf · – But in real PLLs, V fluctuates periodically due to non-ideal effects

High-speed Serial Interface

Lect. 11 – Charge-pump PLL 2

2013-1High-Speed Circuits and Systems Lab., Yonsei University1

CPPLL


• 2nd order vs. 3rd order

2nd-order CPPLL• VCO Control voltage with RC loop filter

– V = VC + VR


Ripples in V during locking process

2nd-order CPPLL• After locking, V should be constant

– But in real PLLs, V fluctuates periodically due to non-ideal effects– Example: Delay mismatch between UP and DOWN path


3rd-order CPPLL• Additional parallel capacitor

– Reduces fluctuation on the control voltage


= 2 ( + 1 ) ∥ 11 + 2 ( + 1 ) ∥ 1 1=> Additional Pole

ϕvco

PD +Charge pump

LoopFilter

VoltageControlledOscillator

MainDivider

ϕref

ICP KVCO

s

[rad]

[rad][I] [V] [rad]

1M

2π

1sC

R+( + 1 ) ∥ 1

3rd-order CPPLL• Phase margin for 3rd-order CPPLL


Magnitude [dB]

Phase [deg]

-90

-180

-40dB/dec

-20dB/dec

zLF

GB(

Gai

n=0d

B)Phase margin

pLF

without additional pole

3rd-order CPPLL• Design guide for 3rd-order CPPLL

– For initial damping factor analysis, use 2nd-order CPPLL– Rule of thumb: C1 > 10 x C2

– For more precise analysis including phase margin, use behavior simulator: MATLAB, CppSIM


Input Noise filtering• Input noise

– Noise transfer function

= = 2 ( + 1 )1 + 2 ( + 1 ) 1 = (2 + )/ + 2 + – Low pass filter for input noise


LoopFilter


MainDivider

ϕout

ϕnoise PD +Charge pump

Optimal PLL Bandwidth


• Clock generation– With clean reference clock small input noise High BW desired

• Clock recovery– Noisy input Low BW desired

VCO Noise• VCO is not ideal

– Oscillation frequency shifts with time Phase noise

• Single Sideband Noise Spectral Density


= 10

VCO Phase noise• Phase noise model for VCO

– Leeson's model: single-sideband phase noise in dBc/Hz

• where f0: output frequency, Ql: loaded Qfm: offset from the output frequency (Hz)fc: 1/f corner frequencyF: noise factor of the amplifierk: Boltzmann's constantT: absolute temperature in KelvinsPs: oscillator output power


= 10 12 2 + 1 + 1

Phase noise


• Phase noise model in VCO

L(f)

Noise floor

foffsetfo/2QLfc

VCO Noise filtering• VCO phase noise

– For noises added after VCO= = 11 + 2 ( + 1 ) 1 = + 2 + High pass filter


LoopFilter


MainDivider

ϕout

ϕref

ϕnoise

PD +Charge pump

Phase noise• VCO phase noise filtering

– Optimal PLL Bandwidth?


L(f)

foffset

VCO phase noise

Filteringby PLL

Filtered phase noise

Phase noise• Higher bandwidth is better for poor VCO


L(f)

foffset

VCO phase noise

Filteringby PLL

Filtered phase noise

Noise filtering• VCO supply noise

= = ,1 + 2 ( + 1 ) 1 = , + 2 + – 1 zero at DC and 2 poles Band-pass filter


VCO

LoopFilter

MainDivider

ϕout

ϕref

Vnoise

PD +Charge pump

,

Noise filtering• Noise filtering characteristics

• Many trade-offs for PLL design Lab project!


Frequency Synthesizer Design Example

High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

• Why do we need frequency synthesizer? Sometimes we want to change the clock speed. Multi-purpose device.

CPU overclocking Multi-purpose device



• How to generate a clock signal with a frequency of more than one?

Large power & chip area Low power & chip area



• Integer-N frequency synthesizer output clock frequency : N*fref, (N+1)*fref, (N+2)*fref, … Frequency resolution : fref Hard to have a high frequency resolution..

PFD Charge PumpRef.CK VCO

Vcont

%N,%2N,%3N,%4N,..

%N*fref

Ratioselect

Counter based frequency divider



• Fractional-N frequency synthesizer output clock frequency : N*fref, (N+0.01)*fref, (N+0.02)*fref, … Frequency resolution : 0.01*fref

Impossible to implement

PFD Charge PumpRef.CK VCO

Vcont

%N,%N+0.01,%N+0.02,..

%N*fref

Ratioselect



• Fractional-N frequency synthesizer output clock frequency : N*fref, (N+0.01)*fref, (N+0.02)*fref, … Frequency resolution : 0.01*fref

N=45454545…Navg=4.5

N=44454445…Navg=4.25

N=45554555…Navg=4.75



• Fractional-N frequency synthesizer

Output frequency range : 200MHz ~ 250MHzFrequency resolution : 12.5MHzReference clock frequency : 50MHz



• PFD (Phase and Frequency detector) design Ref.CK and VCO.CK, which one is faster? How fast?

Ref.CK

Lead

VCO.CK

Lag

Reset

Phase difference = Lead pulse area – Lag pulse area



• Charge pump designWith loop filter, it works as an integrator. UP & DOWN current should be same.

1 ( | |)(1 )2

PUP P sg thp sd

P

WI K V V VL

1 ( )(1 )2

NDown N gs thn ds

N

WI K V V VL

Vsg

Vgs

Vsd

Vds

Can not make them as same!



• Charge pump designWith loop filter, it works as an integrator. UP & DOWN current should be same.

1. Icp is determined by Mn1, Nbias.

2. According to KCL, Red up, down current must be same.

3. Pbias is determined to maintain same Red up,down current, even if Vsd of Mp2 and Vds of Mn1 is changed.

4. Blue up,down current is copy of Red up,downcurrent.



• VCO (voltage controlled oscillator) design Under all PVT condition, it must meet the target

frequency range. (200MHz ~ 250MHz)

1 0 11 0 1

A B C

TD TD TD TD

Period = 6*TD (gate delay)Frequency = 1/period



• VCO (voltage controlled oscillator) design Under all PVT condition, it must meet the target

frequency range. (200MHz ~ 250MHz)

A B C

TD TD TD TD

TD control

TD control

Fosc

200MHz

250MHz



• Frequency divider design 4, 4.25, 4.5, 4.75, 5 dividing ratio

0

4 dividing ratio

- TargetOutput frequency range : 200MHz ~ 250MHzFrequency resolution : 12.5MHzReference clock frequency : 50MHz



1

5 dividing ratio




4.5 dividing ratio N control implementation

0101010101…

Delta-sigma modulator




4.5 dividing ratio N control implementation

10


0

10

100

1001

1

-100 1

01 0001000100…11 0111011101…

DSM output is periodic!



Randomizing the division value!




• Chip_layout

PFD,CP,VCO Counter_based_frequency_divider,3rd_order_DSM

Input_frequency=12.5MHzOutput_frequency_range=100MHz~250MHzFrequency_resolution=0.05MHz



• Measurement setup

CrystalOscillator

FrequencySynthesizer

Oscilloscope

SpectrumAnalyzer

Ref.CK

N_control

Out.CK

Out.CK



• Measurement result frequency range

Center Frequency : 100 MHz Center Frequency : 250 MHz



• Measurement result frequency resolution

Center Frequency : 100 MHzFractional Code : 00000000

(12.5MHz X )

Center Frequency : 100.05 MHzFractional Code : 00000001

(12.5MHz X )



• Measurement resultclock waveform

Frequency : 100 MHzFrac. code : 00000000RMS Jitter : 49.68 psP2P Jitter : 350 ps RMS Jitter UI : 0.0049 UI

Documents

High-speed Serial Interface - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/Lect11_CPPLL_2.pdf · – But in real PLLs, V fluctuates periodically due to non-ideal effects