Student : Andrey KuyelSupervised by Mony Orbach

Spring 2011Midterm Presentation (One semestrial project)

High speed digital systems laboratory

High-Throughput FFT

Technion - Israel institute of technologydepartment of Electrical Engineering

Project goals

• The project goal is to design and implement on FPGA device FFT that capable to deal with data transmitted at the rates up to 10Ms/sec*.

• The design will be written on VHDL• The project has aspects of: signal processing

and logic design and high rate data processing.

*- 5Ms/sec for each of I and Q components .

FFT - Theoretic overviewThe DFT (N- length vector) definition is :

1

0

2;0 1 , expN

nk kN N

n

kX k x nW k N W iN

The time-complexity of the DFT is: 2N

The FFT algorithm (developed at first by J.W. Cooley and John Tukey at 1965) comes to reduce the time-complexity of DFT into logN N

This algorithm called: "The Cooley–Tukey radix-2 FFT algorithm". It is one of the most common FFT algorithms.

FFT radix-2 - Theoretic overviewThe Cooley–Tukey radix-2 FFT algorithm

The idea of algorithm is to compute in two parts:

1 .Calculation two series ,Y k Z k While:

1 1

2 2

0 02 2

,

N N

nk nkeven N odd N

n n

Y k x nW Z k x nW

: The first series is using all of the even components of the input vector -

12 , 0,1, 2...

2N

x n n

,and the second uses the odd components -

2 1 , 1, 2...2Nx n n This calculation takes 2log N

FFT radix-2 - Theoretic overviewCalculation of the twiddles: 2expk

NkW iN

The FFT (N- length vector) definition is:

;0 1 ;2

;0 1 ;2 2

kN

kN

NX k Y k Z k W k

N NX k Y k Z k W k

The FFT schematic Radix-2 diagram (for N=2) – called butterfly unit:

FFT radix-2 - Theoretic overview

The butterfly unit is used as a sub-unit in any Radix-2 FFT-N-size unit.

The "twiddle factor" is the sine/cosine imaginary/real factor : 2expkN

kW iN

4 real multipliersand 2 add/sub16*16 bit

2 (16bits)adders/substractors

The FFT (N=8) radix 2 data flow

C language program for creating FFT data flow for N points FFT

FFT core will have the following features:• Real and imaginary Inputs: 8 bits width each (for each of N point).• Real and imaginary outputs: 16 bits width each, where 8 MSB bits for integer part and 8

LSB bits for fractional part (for each N point).• Drop-in module for Virtex-6 (xc6vlx240T)• Forward complex FFT• Transform sizes N = 16,32,(possibly 64 and 128 )• Arithmetic type: Fixed-point • Truncation after the butterfly • Block RAM or/and Distributed RAM for data storage • Bit/digit reversed or natural output order • Input data at frequency 10 Gs/sec (total rate for real and image part of data )

FFT core features

Parallel N points radix 2 FFT

Input data (real). N points each of 8 bits width

Input data (imag). N points each of 8 bits width

clock

Controls signals

Output data (real). N points each of 16 bits width

Input data (imag). N points each of 16 bits width

Synchronization signals

Parallel N points radix 2 FFT – Block diagram

The FFT (N=16) radix 2 data flow – pipeline stages separation

FFT core

Data in

Controls in Controls out

Data out

Currently implementation will be made on Virtex-6 FPGA Family (xc6vlx240T), the devise contains 768 DSP slices, distributed RAM 3,650 Kb and block RAM of the size 14,976 Kb.See attached specification table at the end of document.

The FFT core will be tested on Virtex-6 FPGA (Ml605 based on xc6vlx240T)

FFT verification and performance measurement

Stimulus Memory

A2D@10Gs/sec *

MEM DATA@10Gs/sec

Virtex-6 FPGA

*- Primary verification will be done on the reference data from FPGA internal memory that will emulate data sampled at the rate 10Ms/sec

Test module

Output signals

Post synthesis report • Maximum operational frequency up to 350MHz (5.6

Gs/sec per component).

• The design have:

8*4*4=128 real (16*16 bits) multipliers. Where one 16*16 bits multiplier take 280 6LUTs

128 (16 bits) adders/subtractors each of the takes 16 of 6LUTS

Simulation and verification

• C program for generating radix 2 data flow • Radix 2 FFT N points parallel C language model

for verification VHDL implementation of design.

Weeks Tasks

1-2 Laboratory administrative issues Done

3 DFT , FFT Background studies Done

4 Studding different FFT algorithms and implimintations

Done

5 Studding hardware available for the project implementation

Done

6 Specification presentation, defining interface signals.

Done

7 Defining FFT core architecture. (Composing block diagram that take advantage of hardware that FFT core will be tested on )

Done

8 Defining FSM (controllers) of the design and implementing them on VHDL. (Testing their functionality)

In progress

9 Writing VHDL code for data path adapted for Virtex-6 architecture. (Virtex-6 DSP slices and memory available for the core)

Partial

Project Schedule

Weeks Tasks

10 Continuing task from week 9.Writing VHDL code for data path adapted for Virtex-6 architecture. (Virtex-6 DSP slices and memory available for the core)

In progress

11 Midterm presentation Done

12-15 Finishing VHDL implementation and beginning of verification

16-17 Writing final presentation and project book

Project Schedule (continued…)