High-speed A/D Converters for Telecom Applications

High-speed A/D Converters for Telecom Applications

High-speed A/D Converters for Telecom Applications

Rudy van de Plassche

Broadcom Netherlands B.V.

Bunnik

2Rudy van de Plassche, Broadcom Netherlands Bunnik

OutlineOutline

• Introduction

• Tuning System Description– Conventional Tuning System– Adaptive Digital IF Tuning System

• A/D Converter Wish List

• Technology Road Map– Matching of CMOS Devices– Supply Voltage Reduction

• A/D Converter Architectures


Outline ContinuedOutline Continued

• Bandpass Sigma-Delta Conversion– Loop Filter Design– 1-Bit AD/DA Converter

• Subranging Conversion– S/H Amplifier Design– Resistor Matching– Capacitive Interpolation

• Pipeline Conversion– Switched Capacitor Pipeline Stage

• Conclusion


“Old” Tuning System“Old” Tuning System


Conventional Tuning SystemConventional Tuning System

Tuner

flo

1-chipAnalog

Demodulator

SAWChannel

Filter

Audio Channels

Video Channel

• SAW Filter Fixes System Performance

• SAW has 12 to 15 dB In-Band Signal Attenuation

• SAW Needs Signal Booster in Tuner


Adaptive Digital IF Tuning SystemAdaptive Digital IF Tuning System

Tuner

flo

LinearA/DConv

DemodulatorDigital

Filters & DSP

SimpleChannel

Filter

• Digital Demodulator and Filters are Programmable to Adapt the System to Different Standards (QAM, QPSK, OFDM, PAL, NTSC etc)

• Simple Channel Filter (Integrated) Shows Limited Attenuation of Neighbor (Disturbing) Channels


A/D Intermodulation DistortionA/D Intermodulation Distortion

A

ffm

Vout = a0 + a1Vin + a2Vin2 + a3 Vin

3 + . .

frequency2f1-f2 f1 f2 2f2-f1

• f1 and f2 are Interfering Channels

• Third Order Distortion Product Interferes with Wanted Channel ffm

• High-linearity is Required


A/D Spurious Free Dynamic RangeA/D Spurious Free Dynamic Range

3

SFDR = 87.9 dB

2

0-10-20-30-40-50-60-70-80-90

-100-110-120-130-140

500450400350300250200150100500

SNR = 91.6 dB

f (kHz)

S/N(dB)

S/N = n 6.02 + 1.76 dBn = 12 >> S/N = 74 dB


A/D Converter Wish SpecificationA/D Converter Wish Specification

Technology0.09 µm Triple Well x Metal

ResolutionEffective Number of BitsResolution BandwidthMaximum Clock FrequencySFDRActive Chip AreaSupply Voltage (+/- 10%)Power DissipationAnalog Input RangeInput Capacitance Integral Non-Linearity (INL)Differential Non-Linearity (DNL)

MinimumSpecification

10 Bit9.5 ENOB45 MHz65 MHz72 dB 0.5 mm2

1.0 V25 mW1.0 V(differential)0.5 pf 0.5 LSB0.25 LSB

TargetSpecification

12 Bit11.5 ENOB65 MHz200 MHz85 dB 1.0 mm2

1.0 V100 mW1.0 V(differential)1.0 pf 0.5 LSB0.25 LSB


Technology Road MapTechnology Road Map2.5

1.8

1.2

0.9

0.6

0.5

0.3

98 00 02 04 06 08 10 12 14

0.25

0.18

0.13

0.10

0.07

0.05

Vdd(V)

Year

Max Vdd

Min Vdd

Minimum Gatelength(µm)

Technology


Threshold Mismatch versus Gate Oxide Thickness

Threshold Mismatch versus Gate Oxide Thickness

NMOS

PMOS30

20

10

10 20 30 40 50 Toxide (nm)

Avth

(mVµm)

Supply Voltage

Offset Voltage

Noise

1x1 µ Device Size


Bandpass Sigma-Delta ArchitectureBandpass Sigma-Delta Architecture

Bandpass

Loop Filter

Analog

Input

+

-

Digital

OutputADC

DAC

Clk


A/D and D/A ImplementationA/D and D/A Implementation

Digital

OutputADC

DAC

Clk"Zero" Comparator

Vref+

Vref-

Clk

ClkAnalog

Input

Analog

Output

Digital Output


1-Bit versus 2-Bit D/A Comparison1-Bit versus 2-Bit D/A ComparisonAnalogOutputVoltage

Digital Input

10

+Vref

-Vref

1-Bit Digital-to-Analog ConverterAnalogOutputVoltage

Digital Input1100

+Vref

-Vref

1001

2-Bit Digital-to-Analog Converter

OffsetVotage

-Vref +δV

• NO INL Requirement

• Large Out-of-Band Quantization Errors

• Only DC-Offset With Unequal Vref

• INL < ½ LSB of Total Converter Resolution

• Smaller Out-of-Band Quantization Errors


Amplifier/ComparatorAmplifier/Comparator

Vdd

Vss

Out

Nout

Clock

Vbias

Nin InM1 M2

M3M4 M5 M6

M7 M8

M9

M10


Loop Filter ArchitectureLoop Filter Architecture

+

+

+

+

Resonator Resonator

ResonatorVout

VinI I I I

I I

Q Q Q Q

Q Q

C1I C1Q C2QC2I C3I C3O


Balanced IntegratorBalanced Integrator

M1

M2

R

R

C

C

C

C

+

+-

-

R

R

C

C

C

C

+

+-

-InI InQ Out

Vadjust

Vadjust

• ftuning = 1/2πRC


Differential Resonator AmplifierDifferential Resonator Amplifier

Out Nout InNin

Vdd

Vss

Ibias

M5

M3 M1 M2 M4

M6


IM3 Measurements of BP SDIM3 Measurements of BP SD

Measurement Noise Floor

-30

-40

-50

-60

-70

-80

-90

Inte

rmod

ulat

ion

(dB

c)

Carrier Level Relative to D/A Power (dB)

-6-8-10-12-14-16-18-20-22-24-26-28

Carrier Separation: 9 kHz 100 kHz 200 kHz


Frequency Repsonse BP SDFrequency Repsonse BP SD


Bandpass Converter DataBandpass Converter Data

200 mVppMaximum Differential Input-82 dBcIM3 (relative to Carriers)13ENOB 9 kHz10.8ENOB 200 kHz86 dBDynamic Range (9 kHz)72 dBDynamic Range (200 kHz)9.15 MHzTuning frequency30 – 80 MHzSample frequency60 mW @ fs = 40 MHzPower Consumption

5 V Analog, 3.3 V DigitalSupply Voltage0.5 µm CMOSTechnology


Ideal Subrange ArchitectureIdeal Subrange Architecture

Coarse Bank

Fine Bank

0

0

0

1

1

1

VrefTop

VrefBot Multiplexer

Rtap

Rtap

Rtap

• Linearity Determined by Ladder Accuracy

• Multiplexer Controlled by Coarse Bank

• Fine Bank Interpolates between Coarse Levels

• Overrange in System Needed to Avoid “missing Codes”


10-Bit Subrange Architecture10-Bit Subrange Architecture

Analog Input

MSB

Coarse Encode Logic

31 Coarse Comparators (Differential)

Analog Multiplexor Analog Multiplexor

41 Fine Comparators (Differential)

Fine Encode Logic

Error Correction Logic and Output Register

Delay

10-bit Digital Output

ClockGenerator

CurrentReference

Absolute Value Circuit

Sample/ HoldAmplifier

VrefTop VrefBot

Fref+ Fref-

5 LSBs

(11) (11)

5 MSBs


Ladder Resistor Matching AccuracyLadder Resistor Matching Accuracy

1 1.5 2 2.5 3 3.5 4 4.5 57

7.5

8

8.5

9

9.5

10

10.5

11

11.5

Element Matching %

Enob

<B

its>

1 Sigma3 Sigma


Sample-and-Hold ArchitectureSample-and-Hold Architecture

Vin

RefTop

RefBot

C1a

C1a

C1b

C1b

Vout+

Vout-

cmi

cmo

cmo

cmi

cmiC3

C3

C2

C2

Hold Phase

Sample/Hold Phase2


Capacitive InterpolationCapacitive InterpolationR

RR

R

RR

R

RR

Compare

Compare

Compare

Clock

Clock

Clock

Vin-

Vin+

VRef-(n+1)

VRef+(n+1)

VRef+(n)

VRef-(n)

C

2C

C

C

2C

2C

2C


Interpolation Error CalculationInterpolation Error Calculation

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Number of Interpolated Zero Crossings

INLError(LSB)

0.2

0.15

0.1

0.05

0

-0.05

-0.1

-0.15

-0.2

VGT = 0.10 V0.15 V0.20 V

• The Interpolation Error Depends on the Linearity of the Input Pair– Large Vgt = Vgs-Vth Reduces the Error


Interpolated Linearity FunctionInterpolated Linearity Function

Output Code

Vin

InterpolatedSignals

Ladder Reference Levels

Zero to Full Scale INL Line

• Interpolation Improves DNL of Converter


Fine Converter BankFine Converter BankR

R

R

RR

R

R

RR

R

R

R

RR

R

Compare

Compare

Compare

Compare

Compare

Clock

Clock

Clock

Clock

Clock

Fine In- Fine In+

Fine Ref-(n+4)

Fine Ref+(n+4)

Fine Ref+(n)

Fine Ref-(n)


Subrange Converter DataSubrange Converter Data

1.75 VppNominal Input Voltage+/- 0.4 LSB, +/- 0.45 LSBINL, DNL77 dBSFDR 1 MHz9.7ENOB 1 MHz-74 dBTHD60 dBSNR60 dBSNDR30 MHzSample frequency120 mWPower Consumption

5 V AnalogSupply Voltage0.5 µm CMOSTechnology


Pipeline Converter ArchitecturePipeline Converter Architecture

Stage 1 Stage 2 Stage 9

2 bits 2 bits

10 bits

Analog

inputSample /Hold

Digital Correction

2 bits

2xResidue

Sample /Hold

ADC DAC

-+

Stage N

Digital

Output


Switched Cap. Pipeline StageSwitched Cap. Pipeline Stage

Sub-ADC DAC 2x Gain

Analog

Input

+VR

4

-VR

4

+

+

-

-

Multiplexer

Latc

h

-VR+VR 0

Residue

Output

-

+

Cs

Cf

S1

S2

S3

• Capacitor Matching Determines Accuracy


Pipeline Converter DataPipeline Converter Data

1.75 VppNominal Input Voltage+/- 0.7 LSB, +/- 0.5 LSBINL, DNL58.5 dBSNDR14.3 MHzSample frequency36 mW Power Consumption

1.5 V AnalogSupply Voltage0.6 µm CMOSTechnology


ConclusionConclusion

• Bandpass Sigma-Delta Conversion is an Excellent Technique for High-Linearity Band Limited Signal Conversion

• Subranging Conversion is an Excellent Wide-Band Conversion Technique Needing only a Well-Matched Reference Ladder

• Pipelined Conversion is a Modular Architecture Showing Excellent Performance. The First Stages Need Accurately Matched Capacitors


Conclusion (II)Conclusion (II)

• Auto-Zero Techniques to Avoid Offset Problems are Automatically Included in the Designs Provided

• Analog Signal Processing is the Limiting Factor in Scaled Down Converter Designs (Vdd < 1 V)

• Future Will Tell What Architecture is Most Promising for the Described Applications

• Scaling Down Converters is a Very Interesting Subject for Future ESSCIRC Papers

Documents

High-speed A/D Converters for Telecom Applications