HDL Lab Manual for VTU

8/13/2019 HDL Lab Manual for VTU

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PA T-A


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PROCEDURE FOR EXECUTION OF HDL CODE IN XILINX 9.2i

01. Double Click on the Project Navigator

02. To close the Existing Project.

File Close Project03. To create a new project

File New project. Give the project Name specify the Location.

o Click on Next. With the device properties Specified below

o Click on Next. Select New Source.

o Select the New source wizard, (Verilog Module or VHDL Module).o Give the file name.o Click on Next.

Type the Entity Name and Architecture, Specify the ports.o Click on Next Finish.

Click on Next NextFinish.04. Double Click on *.vhd file and type the Program

05. Double click on Check syntax in Synthesize.

06. Change the Sources for to Behavioral Simulation.

07. Go to Project New Source


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Select the Test Bench Waveform

Click on NextNextFinish

Enter the data according to the code(either Sequential or Combinational) And Click on Finish

08. Force the data by clicking on the Blue Color areas.

09. Save the file.

10.Change the source for to Behavioral.


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11. Double Click on Simulate behavioral model in the Process Window.

To synthesize the Code using Spartan 2 kit.

11. Change the source for to Synthesis/ Implementation.

12. Go to User constraints and double click on Assign Package pins and Enter the pin details

in LOC column.

Save it

Select the first option (XST Default) and click OK.13. Go to Generate Programming file and double click on Configure Device.

Click on finish. Load the *.bit file to the IC. Right click on the IC and Load the program.

14. Check the output using GPIO kit.


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1. Logic gatesAim:To realize all the logic gates using HDL Description.

Logic Diagram:

AND OR NAND NOR XOR NOT

Truth Table:

AND OR NAND NOR XOR NOT

a b y(0) y(1) y(2) y(3) y(4) y(5)

0 0 0 0 1 1 0 1

0 1 0 1 1 0 1 0

1 0 0 1 1 0 1 1

1 1 1 1 0 0 0 0

VHDL Description:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is

Port ( a,b : in STD_LOGIC;

y: out STD_LOGIC_VECTOR (5 downto 0));end gates;

architecture Behavioral of gates is

begin

y(0)


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endmodule

Output Graph:

Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________2. Binary to gray conversion

Aim:To realize binary to gray combinational Block using HDL Description.

Block Diagram

Truth Table:

b(3) b(2) b(1) b(0) g(3) g(2) g(1) g(0)0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 10 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0


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VHDL Description:

entity bin is

Port ( b : in STD_LOGIC_VECTOR (3 downto 0);

g : out STD_LOGIC_VECTOR (3 downto 0));

end bin;

architecture Behavioral of bin is

begin

g(3)


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________


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3.3-Bit comparator

Aim:To realize 3-Bit comparator combinational Block using HDL Description.

Block Diagram:

Truth Table:

a(2) a(1) a(0) b(2) b(1) b(0)x y z

ab a=b

0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 1 0

1 1 0 1 1 1 1 0 0

1 0 1 1 0 1 0 0 1

VHDL Description:

entity Comp is

Port ( a,b : in STD_LOGIC_VECTOR (2 downto 0);

x,y,z : out STD_LOGIC);

end Comp;

architecture Behavioral of Comp is

begin

process(a,b)

beginx


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Verilog Description:

module comp_3(a,b, x,y,z);

input [2:0] a,b;

output x,y,z;

regx,y,z;

always @ (a or b)

begin

x=0;y=0;z=0;

if(a==b)

x=1;

else if(a>b)

y=1;

elsez=1;

end

endmodule

Output Graph:


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Date: ____________

Observation


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Date: ____________

Review no ___

Marks AllotmentAttendance:

Conduction:

Write up:

Viva:

Lab coordinator:

Lab coordinator:


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4:2 Encoder without priority

Aim:To realize 4:2 encoder combinational Block using HDL Description.

Block Diagram:

Truth Table:

en a(3) a(2) a(1) a(0) y(1) y(0)

1 0 0 0 1 0 0

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 1 0 0 0 1 1

1 Others Z Z

0 X X X X X X

VHDL Description:

entity Encoder is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (1 downto 0);

en : in STD_LOGIC);

end Encoder;

architecture Behavioral of Encoder is

begin

process(a,en)

begin

if(en='0') then

y y y y y y


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end Behavioral;


module encoder(en, a, y);

input en;

input [3:0] a;

output [1:0] y;

reg [1:0] y;

always@(a,en)

begin

if(en==0)

y=2'bXX;

elsecase(a)

4'b0001:y=2'b00;

4'b0010:y=2'b01;

4'b0100:y=2'b10;

4'b1000:y=2'b11;

default y=2'bZZ;

endcase

end

endmodule

Output Graph:


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________


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8:3 Encoder with Priority

Aim:To realize 8:3encoder combinational Block using HDL Description.

Block Diagram:

Truth Table:

en x(7) x(6) x(5) x(4) x(3) x(2) x(1) x(0) y(2) y(1) y(0)

1 0 0 0 0 0 0 0 1 0 0 0

1 0 0 0 0 0 0 1 X 0 0 1

1 0 0 0 0 0 1 X X 0 1 0

1 0 0 0 0 1 X X X 0 1 1

1 0 0 0 1 X X X X 1 0 01 0 0 1 X X X X X 1 0 11 0 1 X X X X X X 1 1 01 1 X X X X X X X 1 1 11 Others Z Z Z

0 X X X X X X X X X X X

VHDL Description:

entity PE isPort ( e : in STD_LOGIC;

x : in STD_LOGIC_VECTOR (07 downto 0);y : out STD_LOGIC_VECTOR (02 downto 0));end PE;

architecture Behavioral of PE is

beginy


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module enc(x, y, en);input [7:0] x;output [2:0] y;

input en;reg [2:0] y;

always @(x)begin

if (en==1)begin

casex (x)8'b1XXXXXXX : y=3'd7;8'b01XXXXXX : y=3'd6;8'b001XXXXX : y=3'd5;

8'b0001XXXX : y=3'd4;8'b00001XXX : y=3'd3;8'b000001XX : y=3'd2;8'b0000001X : y=3'd1;8'b00000001 : y=3'd0;default: y=3'bZZZ;endcase

end

elsebegin

y=3'bXXX;

endend

endmodule

Output Graph:


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________


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2-4 Decoder

Aim:To realize 2-4 decoder combinational Block using HDL Description.

Block Diagram:

Truth Table:

a(1) a(0) y(3) y(2) y(1) y(0)0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

VHDL Description:

entity decoder is


y : out STD_LOGIC_VECTOR (3 downto 0));

end decoder;

architecture Behavioral of decoder is

begin

process(a)

begin

case a is

when "00"=>yyy y


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case(a)

2'b00: y=4'b0001;

2'b01: y=4'b0010;

2'b10: y=4'b0100;

2'b11: y=4'b1000;

default y=4'b0000;endcase

end

endmodule

Output Graph:


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________


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Date: ____________

TEST no ____Comments if any

Marks Allotment

Conduction:

Write up:

Viva:

Lab coordinator:

Lab coordinator:

Student Sign:


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5. 8:1 Multiplexer

Aim:To realize 8:1Multiplexer combinational Circuit using HDL Description.

Block Diagram:

Truth Table:

s(2) s(1) s(0) y

0 0 0 a(0)

0 0 1 a(1)

0 1 0 a(2)

0 1 1 a(3)

1 0 0 a(4)

1 0 1 a(5)

1 1 0 a(6)

1 1 1 a(7)

VHDL Description:

entity Muxx is


s : in STD_LOGIC_VECTOR (2 downto 0);

y : out STD_LOGIC);

end Muxx;

architecture Behavioral of Muxx isbegin

process(a,s)

begin

case s is

when "000" => y y y y y y y


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when others => y


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

6. 1:8 Demultipler

Aim:To realize 8:1Multiplexer combinational Block using HDL Description.

Block Diagram:

Truth Table:

s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0)

0 0 0 0

0

0

0

0

0

0a

0 0 1 0 0 0 0 0 0 a 00 1 0 0 0 0 0 0 a 0 00 1 1 0 0 0 0 a 0 0 01 0 0 0 0 0 a 0 0 0 01 0 1 0 0 a 0 0 0 0 01 1 0 0 a 0 0 0 0 0 01 1 1 a 0 0 0 0 0 0 0

VHDL Description:

3

1:8

Demultiplexer

s(2),s(1),s(0)select lines

y(7),y(6),,y(0)output lines

a, input line

8


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entity Demux_8 is

Port ( a : in STD_LOGIC;

s : in STD_LOGIC_VECTOR (2 downto 0);

y : out STD_LOGIC_VECTOR (7 downto 0));

end Demux_8;

architecture Behavioral of Demux_8 is

begin

process(a,s)

begin

y y(0) y(1) y(2) y(3) y(4) y(5) y(6) y(7)


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endmodule

Outut Graph:

Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________ARITHMETIC LOGIC UNIT

Aim:To realize an ALU using HDL Description.

Block Diagram:

4

en

y,outputy(0),y(1),y(2),y(3)

opcode

o(3),o(2),o(1),o(0)

4-bit ALU

a(3)a(0)

b(3)..b(0)

4

4

4


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Truth Table:

en opcode y

0 XXXX ZZZZ

1 0001 a+b

1 0010 a-b

1 0011 not a

1 0100 {a(1),a(0)} * {b(1),b(0)}

1 0101 a and b

1 0110 a or b

1 0111 a nand b;

1 1000 a xor b

1 1001-1111 XXXX

VHDL Description:

entity alu1 is

Port ( a,b,op : in std_logic_vector(3 downto 0);

en : in std_logic;

y : out std_logic_vector(3 downto 0));

end alu1;architecture Behavioral of alu1 is

begin

process(a,b,en,op)

begin

if(en='0') then yyyyyyyyyy


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module alu1(a, b, en,opcode,result);

input [3:0] a;

input [3:0] b;

input en;

output [3:0] result;input [3:0] opcode;

reg [3:0]result;

always@(a or b or en or opcode)

begin

if (en == 0)

result=4'bZZZZ;

else

case(opcode)

4'b0001:result=a+b;

4'b0010:result=a-b;4'b0011:result=~a;

4'b0100:result=a[1:0]*b[1:0];

4'b0101:result=a&b;

4'b0110:result=a|b;

4'b0111:result=~(a & b);

4'b1000:result=a^b;

default:result=4'XXXX;

endcase

end

endmodule


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Output Graph:

Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________Date: ____________

Review no ___


Conduction:

Write up:

Viva:

Lab coordinator:

Lab coordinator:


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FULL ADDER

Aim:To write a HDL code to describe the functions of a Full Adder Using three modeling

styles.

Logic Diagram:

Block Diagram:

Truth Table:

a b cin sum carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

i) Data flow ModelVHDL Description:

entity fa1 isPort (a,b,cin : in STD_LOGIC;

FullAdder

a

b

cin

carry

sum

ab

cinS

ab

acin

bcin

C


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s,cout : out STD_LOGIC);

end fa1;

architecture Behavioral of fa1 is

begin

s


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Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

COUNTERS

Aim:To write a HDL code to describe the functions of Different types of Counters.

Truth Table:

clk Q clk Q clk Q

Res Binary Counter Mod N Counter BCD counter

X 0 0 0

0 0000 0000 0000

0 0001 0001 00010 0010 0010 00100 0011 0011 00110 0100 0100 01000 0101 0101 01010 . . .0 . . .0 1111 N-1 10011

X 0000

X 0000

X 0000

Asyn Syn Asyn Syn Asyn Syn

ForUP counters take *** as x:=x+'1'; and ** asx=stp or xM]

Strt 0000 0000 M

Stp 1010 0000 N+1

Variable/ reg 0000 0000 M


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Initialisation

ForDOWNcounters take *** as x:=x-'1'; and ** asx=stp or x>strt

Parameters BCD Counter Binary CounterAny SequenceCounter [N>M]

Strt 1001 1111 NStp 1111 1111 M-1

Variable/ regInitialisation

1000 0000 N


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Synchronous CounterVHDL Description:

entity cntr isPort ( clk,rst : in STD_LOGIC;

strt,stp : in STD_LOGIC_VECTOR (3 downto 0);

q : out STD_LOGIC_VECTOR (3 downto 0));end cntr;

architecture Behavioral of cntr isbegin

process(clk,rst)variable x:std_logic_vector(3 downto 0):="1110";beginif (rising_edge(clk)) then

if (rst='1')thenx:="0000";else

x:= x+'1'; ---------***if (x=stp or x


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Asynchronous Counter

VHDL Description:

entity cntr isPort ( clk,rst : in STD_LOGIC;

strt,stp : in STD_LOGIC_VECTOR (3 downto 0);q : out STD_LOGIC_VECTOR (3 downto 0));end cntr;

architecture Behavioral of cntr is

beginprocess(clk,rst)variable x:std_logic_vector(3 downto 0):="1110";beginif (rst='1')then

x:="0000";

elsif (rising_edge(clk)) thenx:= x+'1'; ---------***

if (x=stp or x


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Output Graph:

Reset is synchronous with clk

Reset is Asynchronous with clk


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

FLIP FLOPS

T FLIP FLOP with Synchronous Reset-Preset

Aim:Towrite a HDL code to describe the functions of a T Flip flop.

Truth Table:

clk Res Pre T Q Qb

0 X X X Previous

1 X X 0 1

0 1 X 1 0

0 0 0 0 1

0 0 1 Toggle

VHDL Description:

entity tff is

Port ( clk,t,res,pre : in STD_LOGIC;

q,qb : out STD_LOGIC);

end tff;

architecture Behavioral of tff isbegin

process(clk)

variable qv:STD_LOGIC:='0';

begin

if(rising_edge(clk)) then

if(res='1') then qv:='0';

elsif(pre='1') then qv:='1';

elsif(t='1') then qv:=not qv;

end if;

end if;q


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end process;

end Behavioral;


module tff(t,clk,res,pre,q,qb);

input t,clk,res,pre;output q,qb;

reg q;initial q=1'b0;always@(posedge (clk))beginif(res==1)q=1'b0;else if(pre==1)q=1'b1;else if(t==0)q=t;else

q=~q;end

assign qb=~q;endmodule

Output Graph:

T FLIP FLOP with Asynchronous Reset-PresetAim:Towrite a HDL code to describe the functions of a T Flip flop.

Truth Table:

clk Res Pre T Q Qb

0 0 0 X Previous

X 1 X X 0 1

X 0 1 X 1 0

0 0 0 0 1

0 0 1 Toggle

VHDL Description:


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entity tff_asy isPort ( t,res,pre,clk : in std_logic;

q, qb : out std_logic);end tff_asy;architecture Behavioral of tff_asy is

beginprocess(res,pre,clk)variableqv:std_logic:='0';beginif (res='1')then qv:='0';

elsif(pre='1') then qv:='1';elsif(rising_edge(clk))then

if(t='0') then qv:=qv;elseqv:= not qv;

end if;end if;

q


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

D FLIP FLOP with Synchronous Reset-Preset

Aim:To write a HDL code to describe the functions of a D Flip flop.

Truth Table:

clk Res Pre D Q Qb

0 X X X Previous

1 X X 0 1

0 1 X 1 0

0 0 0 0 1 0 0 1 1 0

VHDL Description:

entity dff is

Port ( clk,res,pre,d : in std_logic;

q,qb : out std_logic);

end dff;

architecture Behavioral of dff is

begin

process(clk)

variableqv: std_logic:='0';

begin


if(res='1') then qv:='0';

elsif(pre='1') then qv:='1';

else qv:=d;

end if;end if;

qb


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q


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0 0 1 1 0

VHDL Description:

entity dff is

Port ( clk,res,pre,d : in std_logic;q,qb : out std_logic);

end dff;

architecture Behavioral of dff is

begin

process(clk,res,pre)

variableqs:std_logic:='0';

begin

if(res='1') then qs:='0';

elsif(pre='1') then qs:='1';elsif(rising_edge(clk)) then

qs:=d;

end if;

q


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

JK flip flops with Synchronous Reset-Preset

Aim:Towrite a HDL code to describe the functions of a SR Flip flop.

Truth Table:

clk Res Pre J K Q Qb

0 0 0 X X Previous

1 X X X 0 1

0 1 XX 1 0

0 0 0 0 Previous 0 0 0 1 0 1

0 0 1 0 1 0

0 0 1 1 Toggle

VHDL Description:

entity jksyff is

Port ( clk,res,pre,j,k : in std_logic;q,qb : out std_logic);

end jksyff;

architecture Behavioral of jksyff is

begin

process(clk)

variableqs:std_logic:='0';

begin


if(res='1') then qs:='0';elsif(pre='1') then qs:='1';

elsif(j='0' and k='1')then qs:='0';


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elsif(j='1' and k='1')then qs:=not qs;

else qs:=qs;

end if;

end if;

q


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Truth Table:

clk Res Pre J K Q Qb

0 0 0 X X Previous

X 1 X X X 0 1

X 0 1 X X 1 0

0 0 0 0 Previous 0 0 0 1 0 1

0 0 1 0 1 0

0 0 1 1 Toggle

VHDL Description:

entity jkasyff is

Port ( clk,res,pre,j,k : in std_logic;


end jkasyff;

architecture Behavioral of jkasyff is

begin

process(clk,res,pre)

variableqs:std_logic:='0';begin

if (res='1')then qs:='0';

elsif(pre='1') then qs:='1';

elsif(rising_edge(clk))then

if(j='0' and k='1')then qs:='0';


elsif(j='1' and k='1')then qs:= not qs;

end if;

end if;

q


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always@(posedge (clk), posedge pre,posedge res)

begin

if(res==1) q=1'b0;

else if(pre==1)q=1'b1;

else if(j==0 & k==1)q=1'b0;

else if (j==1 & k==0)q=1'b1;else if (j==1 & k==1)q=~q;

else q=q;

end

assign qb=~q;

endmodule


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Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

SR flip flops with Synchronous Reset-Preset


Truth Table:

clk Res Pre S R Q Qb

0 X X X X Previous

1 X X X 0 1

0 1 X X 1 0

0 0 0 0 Previous

0 0 0 1 0 1

0 0 1 0 1 0

0 0 1 1 Undetermined

VHDL Description:

entity sr_flipflop is

Port ( clk,res,pre,s,r : in std_logic;


end sr_flipflop;

architecture Behavioral of sr_flipflop is

begin

process(clk)

variableqs,qbs:std_logic:='0';

begin


if(res='1') then qs:='0';qbs:= '1';

elsif(pre='1') then qs:='1';qbs:= '0';


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Output Graph:

SR flip flops with Asynchronous Reset-Preset


Truth Table:

clk Res Pre S R Q Qb

0 0 0 X X Previous

X 1 X X X 01

X 0 1 X X 1 0

0 0 0 0 Previous 0 0 0 1 0 1

0 0 1 0 1 0

0 0 1 1 Undetermined

VHDL Description:

entity sr_flipflop is

Port ( clk,res,pre,s,r : in std_logic;


end sr_flipflop;

architecture Behavioral of sr_flipflop is

begin

process(res,pre,clk)

signal qs,qbs:std_logic:='0';begin

if (res='1')then qs:='0'; qbs:='1';


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Date: ____________

Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

Delay program for Flip-flop and Counters

VHDLentity tff isPort (clk,res,pre,t : in std_logic;

q : inoutstd_logic;qb : out std_logic);end tff;

architecture Behavioral of tff is

signal div:std_logic_vector(21 downto 0):= 0000000000000000000000;

signal clkd: std_logic;begin

process(clk)beginif(raising_edge(clk)) thendiv


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reg q=0;wire clkd;reg [21:0] div;initial

div = 22 d0;always @(posedge(clk))begin

div= div+1;endassign clkd


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Write up:

Viva:

Lab coordinator:

Lab coordinator:


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Date: ____________

TEST no ____Comments if any

Marks Allotment

Conduction:

Write up:

Viva:

Lab coordinator:

Lab coordinator:

Student Sign:


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PA T-B


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DC MOTOR

Aim:To run DC motor using VHDL code.

VHDL Description:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity dcmotor is

Port ( str,dir,clk : in std_logic;fx : out std_logic;

out1 : out std_logic_vector(1 downto 0));end dcmotor;architecture Behavioral of dcmotor isbeginprocess(clk)beginif(rising_edge (clk))thenif (str='0')thenout1


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end Behavioral;STEPPER MOTOR

Aim:To run Stepper motor using VHDL code.

VHDL Description:

entity stepper isPort ( clk,res,dir : in std_logic;

out_abcd : out std_logic_vector(3 downto 0));end stepper;

architecture Behavioral of stepper issignal div:std_logic_vector(21 downto 0);type state_type is (s0,s1,s2,s3);signal state: state_type;signal clka: std_logic;beginprocess(clk,res)beginif(res='1') thendiv state state state state null;end case;elsif(dir='1')thencase state iswhen s3=> state state state state null;end case;end if;end if;end process;with state selectout_abcd


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end Behavioral;


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Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

Date: ____________

Review no ___


Conduction:

Write up:


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Viva:

Lab coordinator:

Lab coordinator:


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DAC

Aim:To Write HDL Code To Generate different waveforms (Square, Triangle, Ramp etc.,) usingDAC change the frequency and amplitude.

VHDL Description To Generate SQUARE WAVE:entity squarewg isPort ( clk,rst : in std_logic;

dac : out std_logic_vector(7 downto 0));end squarewg;

architecture Behavioral of squarewg issignal clkd:std_logic_vector(3 downto0);signal cnt:std_logic_vector(7 downto 0);begin

process(clk)begin

if rising_edge(clk) thenclkd


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VHDL Description to generate TRIANGULAR WAVE

entity triwve isPort ( clk,rst : in std_logic;

dac : out std_logic_vector(7 downto 0));end triwve;

architecture Behavioral of triwve issignal clkd:std_logic_vector(3 downto0);signal cnt:std_logic_vector(7 downto 0);begin

process(clk)begin



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signal cnt:std_logic_vector(7 downto 0);begin

process(clk)begin



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end if;end process;

end Behavioral;

Wave form:

Frequency, F= _________ HzVoltage V=______ V

NET LIST FOR ALL DAC PGMS:

NET "dac" LOC = "p38" ;NET "dac" LOC = "p40" ;NET "dac" LOC = "p41" ;NET "dac" LOC = "p42" ;

NET "dac" LOC = "p43" ;NET "dac" LOC = "p44" ;NET "dac" LOC = "p46" ;NET "dac" LOC = "p47" ;NET "rst" LOC = "p86" ;NET "clk" LOC = "p18


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Observation


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Lab coordinator : ______________________

Lab coordinator: _______________________

SEVEN SEGMENT DISPLAY

Aim:ToWrite HDL code to display messages on the given seven segment display and LCD andaccepting Hex key pad input data.

VHDL Description:

entity sev isPort ( clk,rst : in std_logic;

row : out std_logic_vector(3 downto 0);

col : in std_logic_vector(3 downto 0);en1 : out std_logic;en2 : out std_logic;en3 : out std_logic;en4 : out std_logic;en5 : out std_logic;en6 : out std_logic;

seg_dis : out std_logic_vector(6 downto 0));end sev;

architecture Behavioral of sev istype state is (s0,s1,s2,s3);

signal st:state:=s0;signal clkdiv:std_logic;signal col1,col2:std_logic_vector(3 downto 0);signal clk_div:std_logic_vector(15 downto 0);beginen1


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null;end if;end if;end process;process(clkdiv)begin

if(clkdiv'event and clkdiv='1') then--col1rowseg_disseg_disseg_disseg_disst null;end case;when s2=>rowseg_disseg_disseg_disseg_disst null;end case;when s3=> rowseg_disseg_disseg_disseg_disst null;end case;end case;end if;end process;end Behavioral;

NET LIST:

NET "clk" LOC = "p18" ;NET "col" LOC = "p43" ;NET "col" LOC = "p44" ;NET "col" LOC = "p41" ;NET "col" LOC = "p42" ;NET "en1" LOC = "p56" ;

NET "en2" LOC = "p54" ;NET "en3" LOC = "p51" ;NET "en4" LOC = "p50" ;NET "en5" LOC = "p40" ;NET "en6" LOC = "p49" ;NET "row" LOC = "p30" ;NET "row" LOC = "p39" ;NET "row" LOC = "p28" ;NET "row" LOC = "p31" ;NET "rst" LOC = "p86" ;NET "seg_dis" LOC = "p62" ;NET "seg_dis" LOC = "p65" ;NET "seg_dis" LOC = "p60" ;NET "seg_dis" LOC = "p64" ;NET "seg_dis" LOC = "p59" ;NET "seg_dis" LOC = "p63" ;NET "seg_dis" LOC = "p57" ;


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Lab coordinator : ______________________

Lab coordinator: _______________________

Date: ____________

Final Internal Assessment Examination

Comments if any


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Conduction:

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Student Sign:

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HDL Lab Manual for VTU