Hardware/Software Codesign of Embedded Systems Power/Voltage Management Voicu Groza School of Information…

Hardware/Software Codesign

of Embedded Systems Power/Voltage

ManagementVoicu Groza School of Information Technology and Engineering

[email protected]

University of Ottawa, SITE, 2008

VOICU GROZA - HARDWARE/SOFTWARE CODESIGN OF EMBEDDED SYSTEMS

Embedded Systems

• Power/Energy Aware Embedded Systems

• Dynamic Voltage Scheduling

• Dynamic Power Management

Surpassed hot (kitchen) plate …? Why not use it?

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Processing unitsNeed for efficiency (power + energy):

„Power is considered as the most important constraint in embedded systems“[in: L. Eggermont (ed): Embedded Systems Roadmap 2002, STW]

Current smart phones can hardly be operated for more than an hour, if data is being transmitted.[from a report of the Financial Times, Germany, on an analysis by Credit Suisse First Boston; http://www.ftd.de/tm/tk/9580232.html?nv=se]

Why worry about energy and power?



The energy/flexibility conflict- Intrinsic Power Efficiency -

Technology

[H. de Man, Keynote, DATE‘02;T. Claasen, ISSCC99]

Operations/Watt[MOPS/mW]

Processors

Reconfigurable Computinghardwired muxed ASIC

1

0.1

0.01

0.13µ

Necessary to optimize HW/SW; otherwise the prize for software flexibility cannot be paid!

Ambient Intelligence

0.07µ

DSP-ASIPs

µPs

10

0.25µ0.5µ1.0µ

poor design techniques



Power and energy are related to each other

dtPE

t

P

E

In many cases, faster execution also means less energy, but the opposite may be true if power has to be increased to allow faster execution.

E'



Low Power vs. Low Energy Consumption

Minimizing the power consumption is important forthe design of the power supplythe design of voltage regulatorsthe dimensioning of interconnectshort term cooling

Minimizing the energy consumption is important due torestricted availability of energy (mobile systems)

limited battery capacities (only slowly improving)very high costs of energy (solar panels, in space)

coolinghigh costslimited space

dependability long lifetimes, low temperatures



Application Specific Circuits (ASICS)or Full Custom Circuits

Custom-designed circuits necessaryif ultimate speed orenergy efficiency is the goal andlarge numbers can be sold.

Approach suffers fromlong design times,lack of flexibility

(changing standards) andhigh costs

(e.g. Mill. $ mask costs).



Mask cost for specialized HWbecomes very expensive

[http://www.molecularimprints.com/Technology/tech_articles/MII_COO_NIST_2001.PDF9]

Trend towards implementation in Software



Power Consumption of a Gate



Fundamentals of dynamic voltage scaling (DVS)

Power consumption of CMOScircuits (ignoring leakage):

frequencyclock :tagesupply vol:

ecapacitanc load:activity switching:

2

fVC

fVCP

dd

L

ddL

) ( voltagethreshhold:

2

ddt

t

tdd

ddL

VVV

VVVCk

Delay for CMOS circuits:

Decreasing Vdd reduces P quadratically,while the run-time of algorithms is only linearly increased(ignoring the effects of the memory system).



Potential for Energy OptimizationfVCP ddL

2

CyclesVCtfVCE ddLddL #22

Saving Energy under given Time Constraints:

– Reduce the supply voltage Vdd

– Reduce switching activity α– Reduce the load capacitance CL

– Reduce the number of cycles #Cycles



ProcessorsAt the chip level, embedded chips include micro-controllers and microprocessors. Micro-controllers are the true workhorses of the embedded family. They are the original ’embedded chips’ and include those first employed as controllers in elevators and thermostats [Ryan, 1995].



Voltage Scaling and Power ManagementDynamic Voltage Scaling

Vdd

Energy / C

ycle [nJ]



Prescott: 90 W/cm², 90 nm [c‘t 4/2004]

Nuclear reactor

Power density continues to get worse



Need to consider CPU & System PowerMobile PC

Thermal Design (TDP) System Power

Note: Based on Actual Measurements

600/500 MHz uP37%

LCD 10"19%

HDD9%

Memory+Graphics12%

Power Supply10%

Other13%

Mobile PCAverage System Power

600/500 MHz uP13%

LCD 10"30%

HDD19%

Memory+Graphics15%

Power Supply10%

Other13%

CPU Dominates Thermal Design Power

Multiple Platform Components Comprise

Average Power [Courtesy: N. Dutt; Source: V. Tiwari]



New ideas can actually reduceenergy consumption

As published by Transmeta [www.transmeta.com]

Pentium Crusoe

Running the same multimedia application.



Dynamic power management (DPM)

RUN: operationalIDLE: a sw routine may stop the CPU when not in use, while monitoring interruptsSLEEP: Shutdown of on-chip activity

RUN

SLEEPIDLE

400mW

160µW50mW

90µs

90µs

10µs

10µs160ms

Example: STRONGARM SA1100

Power

fault

sig

nal

Power fault signal



Variable-voltage/frequency example: INTEL Xscale

From

Inte

l’s W

eb S

ite

OS should schedule distribution of the energy budget.



Key requirement #2: Code-size efficiency

CISC machines: RISC machines designed for run-time-,not for code-size-efficiency

Compression techniques: key idea



Code-size efficiencyCompression techniques (continued):

2nd instruction set, e.g. ARM Thumb instruction set:

• Reduction to 65-70 % of original code size• 130% of ARM performance with 8/16 bit memory• 85% of ARM performance with 32-bit memory

1110 001 01001 0 Rd 0 Rd 0000 Constant

16-bit Thumb instr.ADD Rd #constant001 10 Rd Constant

zero extendedmajoropcode minor

opcodesource=destination

[ARM, R. Gupta]

Same approach for LSI TinyRisc, …Requires support by compiler, assembler etc.

Dyn

amic

ally

de

code

d at

ru

n-tim

e



Dictionary approach, two level control store(indirect addressing of instructions)

“Dictionary-based coding schemes cover a wide range of various coders and compressors.Their common feature is that the methods use some kind of a dictionary that contains parts of the input sequence which frequently appear.The encoded sequence in turn contains references to the dictionary elements rather than containing these over and over.”

[Á. Beszédes et al.: Survey of Code size Reduction Methods, Survey of Code-Size Reduction Methods, ACM Computing Surveys, Vol. 35, Sept. 2003, pp 223-267]



Key idea (for d bit instructions)Uncompressed storage of a d-bit-wide instructions requires axd bits.

In compressed code, each instruction pattern is stored only once.

Hopefully, axb+cxd < axd.

Called nanoprogramming in the Motorola 68000.

instructionaddress

CPU

d bit

b « d bit

table of used instructions (“dictionary”)

For each instruction address, S contains table address of instruction.

S a

b

c ≦ 2b

small



Application: y[j] = i=0

x[j-i]*a[i]

i: 0i n-1: yi[j] = yi-1[j] + x[j-i]*a[i]

Key requirement #3: Run-time efficiency - - Domain-oriented architectures -

Architecture: Example: Data path ADSP210x

n-1

Application maps nicely onto architecture

MR

MFMX MY

*+,-

AR

AFAX AY

+,-,..

DP

yi-1[j]

x[j-i]

x[j-i]*a[i]

a[i]

Address generation unit (AGU)

Address- registersA0, A1, A2 ..i+1, j-i+1

ax

MR:=0; A1:=1; A2:=n-2; MX:=x[n-1]; MY:=a[0];for ( j:=1 to n) {MR:=MR+MX*MY; MY:=a[A1]; MX:=x[A2]; A1++; A2--}



Modulo addressingModulo addressing:Am++ Am:=(Am+1) mod n(implements ring or circular buffer in memory)

..x[t1-1]x[t1]x[t1-n+1]x[t1-n+2]..

Memory, t=t1 Memory, t2=t1+1

sliding windowx

t1t

n most recent values

..x[t1-1]x[t1]x[t1+1]x[t1-n+2]..



Returns largest/smallest number in case of over/underflows

Example:a 0111b + 1001standard wrap around arithmetic (1)0000saturating arithmetic 1111(a+b)/2: correct 1000

wrap around arithmetic 0000saturating arithmetic + shifted 0111

Appropriate for DSP/multimedia applications:• No timeliness of results if interrupts are generated for overflows• Precise values less important• Wrap around arithmetic would be worse.

Saturating arithmetic

„almost correct“



Fixed-point arithmetic

Shifting required after multiplications and divisions in order to maintain binary point.



Properties of fixed-point arithmetic

Automatic scaling a key advantage for multiplications.Example:

x= 0.5 x 0.125 + 0.25 x 0.125 = 0.0625 + 0.03125 = 0.09375For iwl=1 and fwl=3 decimal digits, the less significant digits are automatically chopped off: x = 0.093Like a floating point system with numbers [0..1),with no stored exponent (bits used to increase precision).

Appropriate for DSP/multimedia applications(well-known value ranges).



SlowModule

1.3V 50MHz StandardModules

1.8V100MHz

BusyModule

3.3V 200MHz

Spatial vs. DynamicSupply Voltage Management

Normal Mode1.3 V

50MHz

Busy Mode3.3 V

200MHz

Not all components requiresame performance.

Required performance may change over time

Analogy of biological blood systems: • Different supply to different regions• High pressure: High pulse count and High activity• Low pressure: Low pulse count and Low activity





Example: Processor with 3 voltagesCase a): Complete task ASAP

Task that needs to execute 109 cycles within 25 seconds.

Ea= 109 x 40 x 10-9

= 40 [J]



Case b): Two voltages

Eb= 750 106 x 40 x 10-9

+ 250 106 x 10 x 10-9

= 32.5 [J]



Case c): Optimal voltage

Ec = 109 x 25 x 10-9

= 25 [J]



Observations A minimum energy consumption is achieved for the ideal supply voltage of 4 Volts.

In the following: variable voltage processor = processor that allows any supply voltage up to a certain maximum.It is expensive to support truly variable voltages, and therefore, actual processors support only a few fixed voltages.

Ishihara, Yasuura: “Voltage scheduling problem for dynamically variable voltage processors”, Proc. of the 1998 International Symposium on Low Power Electronics and Design (ISLPED’98)



GeneralizationLemma [Ishihara, Yasuura]:• If a variable voltage processor completes a task before the deadline, then the energy consumption can be reduced.• If a processor uses a single supply voltage V and completes a task T just at its deadline, then V is the unique supply voltage which minimizes the energy consumption of T.• If a processor can only use a number of discrete voltage levels, then a voltage schedule with at most two voltages minimizes the energy consumption under any time constraint.• If a processor can only use a number of discrete voltage levels, then the two voltages which minimize the energy consumption are the two immediate neighbors of the ideal voltage Videal possible for a variable voltage processor.



The case of multiple tasks:Assigning optimum voltages to a set of tasks

N : the number of tasksECj : the number of execution cycles of task jL : the number of voltages of the target processorVi : the ith voltage, with 1 i LFi : the clock frequency for supply voltage Vi

T : the global deadline at which all tasks must have been completedSCj : the average switching capacitance during the execution of task j (SCi comprises the actual capacitance CL and the switching activity )Xi, j : the number of clock cycles task j is executed at voltage Vi



Designing an IP modelSimplifying assumptions of the IP-model include the following:• There is one target processor that can be operated at a limited number of discrete voltages.• The time for voltage and frequency switches is negligible.• The worst case number of cycles for each task are known.

Minimize

N

j

L

iijij VxSCE

1 1

2,

Subject to

L

ijji ECxj

1,: and T

FxL

i

N

j i

ji 1 1

,



Experimental Results



Voltage Scheduling Techniques• Static Voltage Scheduling

• Extension: Deadline for each task

• Formulation as IP problem (SS)

• Decisions taken at compile time

• Dynamic Voltage Scheduling

• Decisions taken at run time

• 2 Variants:

• arrival times of tasks is known (SD)

• arrival times of tasks is unknown (DD)



Dynamic Voltage Controlby Operating Systems

Voltage Control and Task Scheduling by Operating System to minimize energy consumptionOkuma, Ishihara, and Yasuura: “Real-Time Task Scheduling for a Variable Voltage Processor”, Proc. of the 1999 International Symposium on System Synthesis (ISSS'99)

Target:• single processor system• Only OS can issue voltage control instructions• Voltage can be changed anytime• only one supply voltage is used at any time• overhead for switching is negligible• static determination of worst case execution cycles



Task2

Task3

Task12.5V

5.0V

4.0V

deadlinearrival time

What is the optimum supply voltage assignment for each task in order to obtain

minimum energy consumption?

Problem for Operating Systems



The proposed Policy

task

Time slot: T

task

Consider a time slot the task can use

without violating real-time constraints

of other tasks executed in the future

Once time slot is determined:

• The task is executed at a frequency of WCEC / T Hz• The scheduler assigns start and end times of time slot



Two Algorithms

Two possible situations:• The arrival time of tasks is known:

SD Algorithm Static ordering and Dynamic voltage assignment

• The arrival time of tasks is unknownDD AlgorithmDynamic ordering and Dynamic voltage assignment

SD DDCPU Time AllocationStart Time AssignmentEnd Time Prediction

off-lineon-lineoff-line

on-lineon-lineon-line



Task1

Task2

• Arrival time of all tasks is known• Deadline of all tasks is known• WCEC of all tasks is known

CPU time can be allocated statically

CPU time is assigned to each task:• assuming maximum supply voltage• assuming WCEC

SD Algorithm (CPU Time Allocation)



Task1

Task2

Free timeCurrent time

SD Algorithm (Start Time Assignment)

Task2

Task1

Task2WCEC @Vmax

Current time

• In SD, it is possible to assign lower supply voltage toTask2 using the free time

• In SS, the scheduler can’t use the free time because it has statically assigned voltage



When the task’s arrival time is unknown, its end time can’t be predicted statically using the SD algorithm

No predetermined CPU time, start or end times

DD Algorithm

Task1

Current time

Task2

Start Time Assignment:

• New task arrives – it either:a)Preempts currently executing taskb)Starts right after currently executing taskStarting time is determined



DD Algorithm (cont.)

End Time Prediction: Based on the currently executing task’s end time

prediction, add the new task’s WCEC time at maximum voltage

Task1

Current time

Task2

Completion time assigned

at CPU time allocation



DD Algorithm (cont.)

If the currently executing task finishes earlier, then new task can start sooner and run slower at lower voltage

Task1

Current time

Task2

Task1

Task2



Task

End TimeStart Time

Task

End TimeStart Time

Comparison: SD vs. DD

SD Algorithm:

DD Algorithm:



Task Normal SS SD DD1 5.0V 4.0V 4.0V 5.0V2 5.0V 4.0V 4.0V 5.0V3 5.0V 5.0V 4.0V 5.0V4 5.0V 2.5V 2.5V 5.0V3 5.0V 2.5V 2.5V 4.0V5 5.0V 2.5V 2.5V 4.0V

Energy 1615J 702J 685J 1357J

Normal: Processor runs at maximum supply voltage

SS: Static SchedulingSD: Scheduling done by SD AlgorithmDD: Scheduling done by DD Algorithm

Experimental Results: Energy



Dynamic power management (DPM)Dynamic Power management tries to assign optimal

power saving statesRequires Hardware SupportExample: StrongARM SA1100

400mW

160uW50mW

90us

90us10us

10us160ms

RUN: operationalIDLE: a sw routine may stop

the CPU when not in use, while monitoring interrupts

SLEEP: Shutdown of on-chip activity

SLEEPIDLE

RUN



The opportunity:Reduce power according to workload

busy idle busy

shut down wake updevice states

Desired: Shutdown only during long idle times Tradeoff between savings and overhead

Tsd Twuworking workingsleeping

Tbs

Tsd: shutdown delay Twu: wakeup delay

Tbs: time before shutdown Tbw: time before wakeup

power states



The challenge

Questions:• When to go to a power-saving state?• Is an idle period long enough for

shutdown?

Predicting the future



Adaptive Stochastic Models

IB BB I………... I BB I I B B

time

Sliding Window (SW): [Chung DATE 99]

• Interpolating pre-computed optimization tables to determine power states

• Using sliding windows to adapt to non-stationarity



Algorithm P Nsd Nwdoff-line 0.33 250 0

Semi-Markov 0.40 326 76Sliding Window 0.43 191 28

Device-Specific Timeout 0.44 323 64Learning Tree 0.46 437 217

Exponential Average 0.50 623 427always on 0.95 - -

Comparison of different approaches

P : average powerNsd: number of shutdownsNwd : wrong shutdowns (actually waste energy)



What about multitasking?

user

device

programprogramprogram

operating system power manager

requesters

Coordinate multiple workload sources



Requesters

We use processes to represent requestersrequester = process

Concurrent processes– Created, executed, and terminated– Have different device utilization– Generate requests only when running

(occupy CPU)Power manager is notified when processes change state



Task Scheduling

Rearrange task execution to cluster similar utilization and idle periods

idle idleT

T: time quantum

time

t1

t2

t3

11

22

23

31

t1

t2

t3

11

22

23

3

idle

1



Power-aware OS implementations

• Windows APM and ACPIDevice-centric, shutdown based

• Power-aware LinuxGood research platform (several partial

implementations, es. U. Delft, Compaq, etc.)Quite high-overhead for low-end embedded systems

• Power-aware ECOS Good research platform (HP-Unibo implementation)Lower overhead than Linux, modular

• Micro OSes



Application Aware DPM –Example: Communication Power

NICs powered by portables reduce battery life

2.5 hours 8 hours• In general:

Higher bit rates lead to higher power consumption• 90% of power for listening to a radio channel Proper use of PHY layer services by MAC is critical!



Doze mode

Off mode Energy saving

Server

Buffering

Playback Playback

Buffer full Playing LWM reached

time

PowerClient

time

Refill

RequestRequestBeacons

Access Point

Low water mark

Off mode power savings



• Higher error probability• Exploits NIC off-state• Min. value to allow data acquisition

• lower error probability• Incurs NIC off-state overhead• Max. value: Buffer_length–1 block

LWM / Buffer characteristics

Where to put the LWM?

How long should the buffer be?

• Depends on memory availability• The longer the buffer, the higher

the NIC off-state benefits

Buffering Strategies should be Power Aware!



Comparison

• Low length buffers incur off mode power overhead• Good power saving for high length buffers



Exploiting application knowledge

Approximate processing [Chandrakasan98-01]Tradeoff quality for energy (es. lossy compression)Design algorithms for graceful degradation

Enforce power-efficiency in programmingAvoid repetitive polling [Intel98]Use event-based activation (interrupts)

Localize computation whenever possibleHelps shutdown of peripherals Helps shutdown of memories

Documents

Hardware/Software Codesign of Embedded Systems Power/Voltage Management Voicu Groza School of Information…