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Hardware Design Guide For Noise Immunity
Application Note
Version 1.00
Contents Hardware design guide for noise immunity
2
Contents
1 Introduction .................................................................................................................................... 5
2 Filter & bypass capacitor ................................................................................................................ 6
2.1 Filter capacitor: EC1 (electrolytic capacitor) ......................................................................... 6
2.2 Bypass capacitor: C1 and C2 ............................................................................................... 6
3 ADC input ....................................................................................................................................... 7
3.1 Power selection ..................................................................................................................... 7
4 Reset pin ........................................................................................................................................ 8
4.1 Filters used on a reset pin ..................................................................................................... 8
5 I2C lines ......................................................................................................................................... 9
5.1 Filters used on I2C Lines ...................................................................................................... 9
6 Unused pins ................................................................................................................................. 10
6.1 Filters used on the unused pins .......................................................................................... 10
7 Power lines ................................................................................................................................... 11
7.1 Filter circuit for power lines ................................................................................................. 11
7.2 Filters used on an MCU Power Input .................................................................................. 11
8 Via connection .............................................................................................................................. 12
8.1 Case 1: a via connection to power/ ground (GND) plane ................................................... 12
8.2 Case 2: via connection to Exposed Pad (EP) of an MCU .................................................. 13
8.3 Case 3: via fences .............................................................................................................. 14
9 Component placement ................................................................................................................. 15
9.1 Component placement guidelines....................................................................................... 15
10 Power line routing ........................................................................................................................ 16
10.1 Case 1: basic tracing for power lines (VDD & GND) .......................................................... 16
10.2 Case 2: when power lines are separately traced at multiple locations ............................... 18
10.3 Case 3: when traces overlap with power lines .................................................................... 19
11 External clock ............................................................................................................................... 20
11.1 Guideline 1: GND shielding ................................................................................................. 20
11.2 Guideline 2: increase current to reduce external noise ...................................................... 21
12 Debugging interface ..................................................................................................................... 22
12.1 Guideline 1: OCD/OCD II (On-Chip Debugger) interface - 8bit MCU ................................. 22
12.2 Guideline 2: JTAG interface – 32-bit MCU .......................................................................... 23
12.2.1 Example (A33G526) ............................................................................................... 24
12.3 Guideline 3: SWD (serial wire debugger) interface – 32-bit MCU ...................................... 25
12.4 Guideline 4: SWD (serial wire debugger) interface ............................................................. 26
Revision history ..................................................................................................................................... 27
Hardware design guide for noise immunity List of figures
3
List of figures
Figure 1. Filter & Bypass Capacitor Diagram.......................................................................................... 6
Figure 2. Power Selection Diagram ........................................................................................................ 7
Figure 3. Filters used on a Reset Pin Diagram ....................................................................................... 8
Figure 4. Filters used on an I2C Line Diagram ....................................................................................... 9
Figure 5. Filters used on Unused Pins Diagram (For only Push-Pull Output Low) ............................... 10
Figure 6. Power Lines Diagram ............................................................................................................ 11
Figure 7. Via Connection to Power/ Ground (GND) Plane ................................................................... 12
Figure 8. Via Connection to EP (Exposed Pad) of an MCU Diagram ................................................... 13
Figure 9. Via Fences Diagram .............................................................................................................. 14
Figure 10. Component Placement Diagram.......................................................................................... 15
Figure 11. Basic Tracing for Power Lines (VDD & GND) Diagram ....................................................... 16
Figure 12. Single-layer Board Design Diagram .................................................................................... 17
Figure 13. Power Lines are Separately Traced at Multiple Locations Diagram .................................... 18
Figure 14. Traces Overlap with Power Lines Diagram ......................................................................... 19
Figure 15. GND Shielding Diagram ...................................................................................................... 20
Figure 16. Increase Current to Reduce External Noise Diagram ......................................................... 21
Figure 17. OCD/OCD II (On-chip Debugger) Interface Diagram .......................................................... 22
Figure 18. JTAG Interface - Example (A33G526) ................................................................................. 24
Figure 19. JTAG Interface - Example (A31G213) ................................................................................. 26
List of tables Hardware design guide for noise immunity
4
List of tables
Table 1. Capacitor Component Value ..................................................................................................... 6
Table 2. Reset Pin Component Values ................................................................................................... 8
Table 3. I2C Line Component Value ....................................................................................................... 9
Table 4. Unused Pins Component Value .............................................................................................. 10
Table 5. Power Lines Component Value ............................................................................................... 11
Table 6. Increase Current to Reduce External Noise Component Value .............................................. 21
Table 7. JTAG Interface Resister value ................................................................................................. 23
Table 8. SWD Interface Resister value ................................................................................................. 25
Hardware design guide for noise immunity 1. Introduction
5
1 Introduction
This application note intends to give a brief overview of hardware implementation on the development
board, by providing information about various features of 8-bit/ 32-bit MCUs.
Specially, this document offers solutions for noise which may occur during hardware design through
eleven chapters as listed below:
Chapter 2. Filter & bypass capacitor
Chapter 3. ADC input
Chapter 4. Reset pin
Chapter 5. I2C lines
Chapter 6. Unused pins
Chapter 7. Power lines
Chapter 8. Via connection
Chapter 9. Component placement
Chapter 10. Power line routing
Chapter 11. External clock
Chapter 12. Debugging interface
2. Filter & bypass capacitor Hardware design guide for noise immunity
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2 Filter & bypass capacitor
2.1 Filter capacitor: EC1 (electrolytic capacitor)
1. External noise (e.g. EFT) is reduced first by a capacitor of a power source.
2. When an electrolytic capacitor with leads is used, values of ESL (Equivalent Series Inductance)
and ESR (Equivalent Series Resistance) are high, and thus SRF (Self Resonant Frequency)
value is low.
3. The filter capacitor EC1 is used to block low frequency noise. It should be placed close to a
Host (IC) or a connector (within 30mm) rather than to an MCU.
2.2 Bypass capacitor: C1 and C2
1. Chip ceramic capacitors are recommended to use.
2. Two capacitors are used often in a decoupling capacitor structure (Typ. use 100-fold
difference).
3. Since they block high frequency noise, the bypass capacitors should be placed close to an
MCU’s power pin (within 10mm).
Table 1. Capacitor Component Value
Item Component Value
Bypass capacitor
(decoupling)
C1 10nF (0.01uF) to 100nF (0.1uF)
C2 1uF
Filter capacitor EC1 Typ. 22uF
Figure 1. Filter & Bypass Capacitor Diagram
Hardware design guide for noise immunity 3. ADC input
7
3 ADC input
3.1 Power selection
1. If analog power (AVDD and AVSS) and digital power (VDD and VSS) are separated in an
MCU, analog power should be used for a circuit design.
2. If an MCU supports single power internally, single power should be used. It should be sure
that the analog power and the input trace are not affected by external noise.
3. Additionally, an RC filter (Low Pass Filter) can be used on the ADC input trace. When using
the RC Filter, RC Time Constant value should be 3-times the stabilization time.
Figure 2. Power Selection Diagram
4. Reset pin Hardware design guide for noise immunity
8
4 Reset pin
4.1 Filters used on a reset pin
1. Regardless of whether to use a reset pin, resistors and capacitors must be placed at the reset
pin for stability.
2. A circuit must be carefully selected depending on the reset pin’s characteristics.
Table 2. Reset Pin Component Values
Item Component Value
Pull-up/down resistor R1 10KΩ
Filter capacitor C1 Typ. 100nF (0.1uF, example)
Figure 3. Filters used on a Reset Pin Diagram
Hardware design guide for noise immunity 5. I2C lines
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5 I2C lines
5.1 Filters used on I2C Lines
1. Pull-up resistors, series resistors, and filter capacitors are available for the use of filters.
2. The order and the location of the filter parts are critical to performance.
→ A series resistor reduces noise and a filter capacitor bypasses the noise to GND.
3. Filter (R1 to R4, C1, C2) parts must be placed close to a host (IC) or a connector (within 30mm)
rather than to an MCU.
4. The same guideline is applied to SPI lines.
Table 3. I2C Line Component Value
Item Component Value
Pull-up Resistor R1, R2 4.7kΩ ~ 10kΩ
Series Resistor R3, R4 100Ω ~ 330Ω
Filter Capacitor C1, C2 NC or ~ 100pF
Figure 4. Filters used on an I2C Line Diagram
6. Unused pins Hardware design guide for noise immunity
10
6 Unused pins
6.1 Filters used on the unused pins
1. To terminate the unused pins, a user can connect pull-down resistors. This improves the noise
immunity.
2. Resistors should be placed close to an MCU (within 20mm).
3. NC pins must be set as a Push-pull Output Low (Recommended).
A. Alternatively, the Input and Pull-up (Internal) can be used. Please remember that the pull
down should not be used.
Table 4. Unused Pins Component Value
Item Component Value
Pull-down Resistor R1 1KΩ ~ 10KΩ
Figure 5. Filters used on Unused Pins Diagram (For only Push-Pull Output Low)
Hardware design guide for noise immunity 7. Power lines
11
7 Power lines
7.1 Filter circuit for power lines
Filters on power lines will enhance performance of the boards that failed tests.
7.2 Filters used on an MCU Power Input
Filter parts (L1 and L2) must be placed close to noise sources (e.g. within 30mm of the Connector)
rather than to an MCU.
Table 5. Power Lines Component Value
Item Component Value
Decoupling Capacitor C1 10nF(0.01uF) ~ 100nF(0.1uF)
C2 1uF
Series Inductor L1, L2 Typ. 4.7uH
Figure 6. Power Lines Diagram
8. Via connection Hardware design guide for noise immunity
12
8 Via connection
8.1 Case 1: a via connection to power/ ground (GND) plane
1. A user can use a via to connect a bypass & filter capacitor to the power or the GND of different
layer during a circuit board design.
2. At this point, traces connecting the capacitor through the via form a single inductance value.
3. The bigger the inductance value (unwanted) is, the more external noise affects.
4. Therefore, by widening the trace width while using multiple vias, the user can reduce the
inductance value and pass the filtered noise to GND easily.
Figure 7. Via Connection to Power/ Ground (GND) Plane
Hardware design guide for noise immunity 8. Via connection
13
8.2 Case 2: via connection to Exposed Pad (EP) of an MCU
1. Packages such as QFN have Exposed Pads (Bottom Pads). These pads are normally
connected to GND.
2. A user can place as many vias as possible on an EP pin.
E.g. For 16-pin QFN (3mm X 3mm), a user can place at least 2 vias in an EP.
Figure 8. Via Connection to EP (Exposed Pad) of an MCU Diagram
8. Via connection Hardware design guide for noise immunity
14
8.3 Case 3: via fences
1. Place GND vias in fixed intervals on boundaries of a board (typ. 5mm pitch).
2. Place GND vias in fixed intervals on internal GND pattern too.
3. External noise and EMI emission effects can be reduced by executing steps 1 and 2.
Figure 9. Via Fences Diagram
Hardware design guide for noise immunity 9. Component placement
15
9 Component placement
9.1 Component placement guidelines
1. Use a via to connect a bypass & filter capacitor to power or GND of different layer during a
circuit board design.
2. At this point, traces connecting the capacitor through the via form a single inductance value.
3. The bigger the inductance value (unwanted) is, the more external noise affects.
Figure 10. Component Placement Diagram
10. Power line routing Hardware design guide for noise immunity
16
10 Power line routing
10.1 Case 1: basic tracing for power lines (VDD & GND)
1. Trace wide in parallel without jumpers (Recommend filling GND with copper pattern).
2. VDD and GND power lines must be placed in vicinity and in parallel. Minimize the surface area
of a loop that VDD and GND created.
Figure 11. Basic Tracing for Power Lines (VDD & GND) Diagram
Hardware design guide for noise immunity 10. Power line routing
17
3. Example: single-layer board design
Figure 12. Single-layer Board Design Diagram
10. Power line routing Hardware design guide for noise immunity
18
10.2 Case 2: when power lines are separately traced at multiple locations
1. Power lines must be filtered first and then divided.
2. In Figure 13 showing the poor case, tracing without EC1 (Filter Capacitor) is not filtered
sufficiently and can be affected by external noise flowing into the power line.
Figure 13. Power Lines are Separately Traced at Multiple Locations Diagram
Hardware design guide for noise immunity 10. Power line routing
19
10.3 Case 3: when traces overlap with power lines
1. Traces should not overlap any parts if possible. However, in case of overlap with power lines,
they must be filtered before the overlap.
2. Figure 14 shows the poor case. When signal traces overlap unfiltered power lines, they can
be affected by external noise flowing into the power lines.
3. Overlapping traces account for not only the power lines but also the communication lines.
Figure 14. Traces Overlap with Power Lines Diagram
11. External clock Hardware design guide for noise immunity
20
11 External clock
11.1 Guideline 1: GND shielding
1. In case of using an external clock source (crystal oscillator or ceramic resonator)
2. Form GND shielding (ground guard) pattern around the clock source GND shielding (ground
guard).
A. It minimizes EMI emission, and in turn minimizes external noise effect.
B. A clock source GND pin and an MCU GND pin should be connected properly. If a GND
on a different layer is connected, the connection will be used as an inflow route of external
noise and unwanted oscillation and offset can be generated by the external noise.
Figure 15. GND Shielding Diagram
Hardware design guide for noise immunity 11. External clock
21
11.2 Guideline 2: increase current to reduce external noise
If a noise issue related to the XTAL pin is still existed, the following method may help to solve it.
Add a resistor between XIN pin and XOUT pin to reduce resistance on the oscillator feedback.
Table 6. Increase Current to Reduce External Noise Component Value
Item Component Value
External feedback resistor R1 330KΩ to 750KΩ
Figure 16. Increase Current to Reduce External Noise Diagram
12. Debugging interface Hardware design guide for noise immunity
22
12 Debugging interface
12.1 Guideline 1: OCD/OCD II (On-Chip Debugger) interface - 8bit MCU
Figure 17. OCD/OCD II (On-chip Debugger) Interface Diagram
Hardware design guide for noise immunity 12. Debugging interface
23
12.2 Guideline 2: JTAG interface – 32-bit MCU
1. JTAG interface is used for firmware update or debugging.
2. When using the JTAG interface, a pull-up/pull-down resistor must meet the specification
shown in Table 7:
Table 7. JTAG Interface Resister value
nTRST TDI TMS TCK TDO BOOT
AC33M4064 Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
1MΩ
Pull-up
10KΩ
AC33M8128 Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
1MΩ
Pull-up
10KΩ
A33G526 Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
10KΩ
Pull-up
1MΩ
Pull-down
10KΩ
3. After the development stage, if JTAG pins are left in unconnected state, they can be affected
by external noise. For this reason, the pull-up resistors and the pull-down resistors are required
in production boards.
4. As a reference, a device supporting both JTAG interface and SWD interface is introduced in
the following:
A. The device’s interface that is not used under the development state can be set to NC,
since the firmware can fix it to Output Low or Output High.
5. Resistors should be placed close to the JTAG pins (within 10mm).
6. Pull-up resistor power must be connected to MCU’s VDD power.
7. If power connection of the pull-up resistor is far from MCU’s VDD power (over 10mm), add a
bypass capacitor of 0.1uF between MCU’s VDD pin and GND. In addition, the bypass
capacitor’s GND pin and the MCU’s GND pin must be very well connected.
NOTE: When nTRST pin is connected to GND (using a 0Ω resistor), the JTAG is disabled.
12. Debugging interface Hardware design guide for noise immunity
24
12.2.1 Example (A33G526)
Figure 18. JTAG Interface - Example (A33G526)
Hardware design guide for noise immunity 12. Debugging interface
25
12.3 Guideline 3: SWD (serial wire debugger) interface – 32-bit MCU
1. SWD Interface is used for firmware update or debugging.
2. When using the SWD interface, a pull-up/pull-down resistor must follow the specification
shown in Table 8:
Table 8. SWD Interface Resister value
SWDIO SWCLK nRESET BOOT AC30M1x64 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ AC33Mx064 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ AC33Mx128 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ A31G11x Pull-up 10KΩ Pull-down 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ A31G12x Pull-up 10KΩ Pull-down 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ A31G213 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ A31G314 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-up 10KΩ A33G526 Pull-up 10KΩ Pull-up 10KΩ Pull-up 10KΩ with Shunt C Pull-down 10KΩ
3. Even after development stage, if the SWD pins are left in unconnected state, they can be
affected by external noise. For this reason, the pull-up resistors and the pull-down resistors
are required in production boards.
12. Debugging interface Hardware design guide for noise immunity
26
12.4 Guideline 4: SWD (serial wire debugger) interface
1. As a reference, a device supporting both JTAG interface and SWD interface is introduced:
A. The device’s interface that is not used under the development state can be set to NC.
B. Because the firmware can fix it to Output Low or Output High.
2. Resistors should be placed close to the SWD pins (within 10mm).
3. Pull-up resistor power must be connected to MCU’s VDD power.
4. If the power connection of the pull-up resistor is far from MCU’s VDD power (over 10mm), add
a bypass capacitor of 0.1uF between MCU’s VDD pin and GND. In addition, the capacitor’s
GND and the MCU’s GND pin must be connected very well.
5. Pull-up Resistor of 10KΩ and Shunt Capacitor (typical 0.1uF) must be placed on nRESET pin.
Figure 19. JTAG Interface - Example (A31G213)
Hardware design guide for noise immunity Revision history
27
Revision history
Version Date Description
1.00 20.02.05 Document created
Important notice Hardware design guide for noise immunity
28
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