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ENHANCED POWER SHARING IN MICROGRIDS USING THEMODIFIED DROOP AND VIRTUAL LINE IMPEDANCE SYSTEMS

Mohammad Ali Aghasafari, Luiz A.C. Lopes, and Sheldon Williamson

Power Electronics & Energy Research (PEER) GroupConcordia University, Montreal, Canada

Presented in 4th Canadian Solar Buildings ConferenceToronto, 2009

1

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Outline of the presentation

• Introduction

• Motivation

• Proposed approach.

2

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Elementary system used in this study

• Each “source” consists of a dc bus, a PWM inverter and an LC low pass

filter.

• Feeder lengths, and respective impedances, differ by a factor K.

6

Vload rated =120V RMS , Sload=2100VA, f rated =60Hz, S1=1400VA, S2=700VA, Zline1=(0.20 + jω* 0.00154)=(1/3)*Zline2, n1= 0.3/(2*3.2) (V/W), n2= 0.3(V/W) , m1=0.12/2 (Hz/VAR), m2= 0.012(Hz/VAR)

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Control System

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The control system consists of 4 levels which are mentioned below from the inside to outside:

1) Inverter current control loop; 2) Inverter voltage control loop; 3) Virtual resistance loop;

and 4) Droop control loop

DistributedGenerator

PWM Fullbridge

inverterL Filter ommon

Load

PWMGating

urrentontroller

Voltageontroller

Poweralculator

P DroopEquation

Q DroopEquation

ReferenceVoltage

Generator

LineImpedance

+ +

- -

VoIo

P

Q

Wref

E*

Vref*

Iref

Vo IoLPF

Vref PWM

DC Bus

Vref

Commonpoint

Vo

Io

VirtualImpedance

Io

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Control System Levels

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1) Inverter current loop: A PR (proportional resonant) controller has been used to

produce sinusoidal waveforms with very small distortions. The reference current is the

output of voltage controller. The current controller is faster than voltage controller so that

it could follow the changes in its reference fast enough.

2) Voltage control loop: Another PR controller is used to guarantee inverter voltage

waveforms with reduced distortion and steady-state errors. The voltage reference is

itself the output of virtual impedance system.

The DC source bus voltage should be greater than control voltage of inverters (aroundVref); otherwise there will be some harmonics in the voltage or even system instability

due to overmodulation in the inverters.

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3) Virtual impedance loop: The virtual impedance adds a virtual voltage drop to the voltageproduced by droop system (Vref*) and makes the actual voltage reference of the voltage controller.Large virtual impedances make the capability of more difference between the supplied powers of inverters (with different rated powers) without instability in transient state.

In the presented system, by putting large magnitude of virtual resistance (80 times of the actual firstline resistance) symmetrically for all sources lines, the total line impedances seen by the virtual ACsources will be almost balanced which improves the power sharing.

PowerStage

V Icontrollers

+

-

IoVref* Vref_PWMVref

VirtualImpedance

(Z ov )

Io.Z ov

Z0_inv1 Z0_inv2

Inverter 1 Inverter 2

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4) Droop system loop: The droop equations are: Eref*=E0*-nP , ω= ω0+mQ. Note that P & Q are

themselves dependent on Eref * and ω.

There is a trade-off between P/Q sharing precision and the output voltage amplitude/frequency

regulation.

According to the second droop equation above there is Qi = and since the inverters have

the same steady state and no load frequencies, one should choose the ms using the equation

S1*m1=S2*m2; thus there will be good Q sharing. Also the droop equations are in harmony with

power flow equations so these 4 equations end up with 4 stable results for the E, ω, P, and Q.

These are the reasons why the droop scheme according to the equations at the top is designed.

m

o

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Other System Elements

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The unipolar PWM inverters have f switching=18 kHz.

The values of Lfilter= 15mH and Cfilter= 20 uF have been chosen which will result in the

system -3db point of about 600 Hz = 3.3%*f switching.

These rather big magnitudes of LPF impedances are needed to have less circulating currents.

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Simulations Results

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The load has been full initially and has been decreased by 20% at t = 0.4s. One can see in figure below the

system frequency and virtual reference voltages settling times of about 0.12 sec, and very small oscillations.

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Simulation Steady State Results and the Effect of Droop Coefficients on them

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The steady state results of the system with modified mentioned droop coefficients at time t=0.39s are shown

below which show the great power sharing and acceptable frequency and voltage regulation.

For the system simulated above if the conventional ns of n1= , n2=0.3 are used there will be at

steady state (t=0.39s) which is far away from the desired ratio of 2.

Vload_RMS 123.3V

P1 1108.0Watt

P2 558.1Watt

Q1 891.6VAR

Q2 445.7VAR

Eref 1* 408.1V

Eref 2* 292.6V

f 60.05Hz

P1/P2 1.99

Q1/Q2 2.00

2

3.0

W

V

W

V 33.12

1

P

P

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The Effect of Virtual Resistance on Simulation Results

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If the virtual resistance is eliminated from the system simulated initially, the system will be unstable and if thevirtual resistance is reduced from 80*Rline1 (the original system) to 60*Rline1 the speed of system will decreaseand its oscillations will increase as shown below.

Response of the system with reduced virtual resistance Response of the original system

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Conclusion

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Improved power sharing and transient response have been achieved in droop controlled parallel

inverters of different ratings and connected to a common bus through feeders of different lengths.

The formula S1*n1=S2*n2 (as in conventional droop control) has been modified since it doesn’t

result in perfect P sharing especially when the rated powers of the sources are not equal.

The emulation of large “virtual” output resistances reduces the feeder impedances unbalance

thus it improves power sharing.

The voltage and current controllers and large virtual resistances make the system faster and less

oscillatory.

The enhanced performance of the proposed scheme has been demonstrated by means of simulations.

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Thank you for your attention

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