Fundamentals of Processor Design

Using figures from

Rapid Prototyping of Digital Systems by Hamblen and Furman

Spring 2014

EE 310 Course Topics

Digital

Hardware Design

Rapid Prototyping

with FPGAs

Computer

Organization

VHDL

Overview

Behavioral model is provided in HamblenYou will design a structural model over the course of the semester

ALU

Registers

Controller

mP3

The Framework

Computer organization; the role of the processorProcessor architecture vs. organizationProcessor organization in detailProcessor performanceWill learn about processor design and organization in general

one specific example

Building Blocks of a Computing System

Processor

Datapath

Registers (register file)

ALU

Interconnection structure

Interface with memory

Instruction path

Registers

Interface with memory

Control Unit

MemoryI/OA software-programmable computing system also needs

Compiler

Operating System

Middleware

Structural vs. dynamic description of a processorPure hardware vs. software-programmable system---and hybrids

Embedded vs. Desktop Processors

Embedded

Priority is predictable behaviorOriented toward interaction with the physical world

Desktop

Priority is computational speedBuffered interfaces to the external environment

Different types of computing systems

Transformational no time concept

Interactive its own speed

Reactive speed of environment

Computer Hardware Organization

Interconnection

Structure

Processor

I/O

Memory

The interconnection structure is normally one or more busses

Bus = multiple signals, going to the same places

Bus can have multiple drivers, need to worry about control

Architecture

The programmers view of the computer (usually the assembly language programmers view)What it doesAnalogy: The architect decides how the building will lookThe ISA (Instruction Set Architecture) - defines the meaning of the binary numbers that tell the processor what to do, and with whatDefines the hardware/software interfaceDefines the dynamic/static interface between the hardware and the compiler

Organization

The machinery or structure that underlies the architecture---the microarchitectureHow it does itAnalogy: The structural engineer defines the materials and the load-bearing frame structure---how the building is put togetherPrecisely, the collection of functional units (registers, ALU, and control unit) and how they are interconnected

Instruction Set Architecture (ISA):

Dynamic/Static Interface

Program

Machine

Architecture

D/SI

Static

Dynamic

The ISA defines the (dynamic/static) interface

between the program (HLL) and the machine

Components of the ISA

Opcodes

Defines what is to be done to the operands specified by the address field

Addressing modes

There are multiple ways to specify the data to use: either explicitly in the instruction (immediate), or by specifying its location (in various ways)

Data types

Defines how a number is represented and the number of bits for that representation

Multiple Descriptions of a Processors Organization

Structure

All the functional units and how they are interconnected

Block diagram

Dynamics temporal behavior

Instruction cycle and clocking methodology

State and flow diagrams

Basic Datapath

Register

File

ALU

To

Data Bus

To

Address Bus

From

Data Bus

Status to

Control Unit

Control Unit selects

Registers and ALU function

Structure of a Processor

Bus

Data

Register

Status

Register

ALU

Register

File

Address

Generation

Logic

Program

Counter

Stack

Pointer

Control

Circuitry

Instruction

Register

Address

Register

Control Unit

Data Processing Unit

Control

Signals

Basic Processor Design Steps

1. Establish datapath requirements from instruction set

each instruction is implemented by register transfers

datapath must include registers for ISA and control/status registers

datapath must support each register transfer via the interconnection structure

2. Select datapath components and establish clocking methodology

3. Design datapath meeting the requirements

4. Determine setting of control points that effects the register transfer

5. Design the control logic

Organization of a Simple Processor

Need to define

interconnection structure

Need to define control and

status lines for memory & I/O

Processor

Memory

Input/Ouput

Data Bus

Address Bus

PC

IR

AC

MDR

MAR

ALU

Control

Unit

Figure 8.7 Datapath. Values shown after applying reset.

MW is

Memory Write

control line

Register Definitions

Instruction-oriented registers

PC (Program Counter) points to the address of the (current/next) instruction

IR (Instruction Register) holds the current instruction

Data-oriented registers

AC (accumulator) holds one operand for ALU; receives result from ALU

MAR (Memory Address Register) holds location of information to be loaded from memory

MDR (Memory Data Register) holds data coming from/going to memory; other operand for ALU

Instruction Format

1. The width of the opcode is determined (in part)

by the number of instructions in the ISA.

2. In general, the number of operands will vary,

depending on the instruction

9.unknown

ADDI - add immediate, signed, sign extend address to 16 bits

SHL - use lower 4 bits of address field, unsigned. Other 4 bits are "0000".

Instruction Set

Instruction Mnemonic Operation PreformedOpcode Value

ADD addressAC

Processor Instruction Cycle

Fetch Next

Instruction

Decode

Instruction

Execute

Instruction

EXECUTE

MAR = PC*

IR = MDR

PC = PC + 1

Read Memory

MDR = AC

Write Memory

AC = MDR

AC = AC + MDR

MAR = IR

Read

Memory

FETCH

DECODE

Opcode=ADD

Opcode=LOAD

Opcode=STORE

MAR set in

EXECUTE step

Details of Instruction Cycle

Figure 8.7 Datapath. Values shown after applying reset.

MW is

Memory Write

control line

Figure 8.8 Register transfers in the ADD instructions Fetch State.

1. Read memory

2. IR = MDR

3. PC = PC + 1

Note: MAR=PC

is moved to

Execute state

to save a clock

cycle!

Figure 8.9 Register transfers in the ADD instructions Decode State.

1. Decode opcode

2. MAR = IR

3. Start memory

read

Figure 8.10 Register transfers in the ADD instructions Execute State.

1. AC = AC + MDR

2. MAR = PC

3. Go to FETCH

Figure 8.13 Simulation of the simple computer program.

-- Simple Computer Model scomp.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.ALL;

ENTITY SCOMP IS

PORT(clock, reset : IN STD_LOGIC;

program_counter_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );

register_AC_out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0 );

memory_data_register_out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0 ));

memory_address_register_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0 );

memory_write_out: OUT STD_LOGIC);

END SCOMP;

ARCHITECTURE a OF scomp IS

TYPE STATE_TYPE IS ( reset_pc, fetch, decode, execute_add, execute_load, execute_store,

execute_store2, execute_jump );

SIGNAL state: STATE_TYPE;

SIGNAL instruction_register, memory_data_register : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL register_AC : STD_LOGIC_VECTOR(15 DOWNTO 0 );

SIGNAL program_counter : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

SIGNAL memory_address_register: STD_LOGIC_VECTOR( 7 DOWNTO 0 );

SIGNAL memory_write : STD_LOGIC;

BEGIN

-- Use Altsyncram function for computer's memory (256 16-bit words)

memory: altsyncram

GENERIC MAP (

operation_mode => "SINGLE_PORT",

width_a => 16,

widthad_a => 8,

lpm_type => "altsyncram",

outdata_reg_a => "UNREGISTERED",

-- Reads in mif file for initial program and data values

init_file => "program.mif",

intended_device_family => "Cyclone")

PORT MAP (wren_a => memory_write, clock0 => clock,

address_a =>memory_address_register, data_a => Register_AC,

q_a => memory_data_register );

-- Output major signals for simulation

program_counter_out

PROCESS ( CLOCK, RESET )

BEGIN

IF reset = '1' THEN

state

-- Execute the ADD instruction

WHEN execute_add =>

register_ac

-- Execute the ADD instruction

WHEN execute_add =>

register_ac

-- memory address register is already inside synchronous memory unit

-- need to load its value based on current state

-- (no second register is used - not inside a process here)

WITH state SELECT

memory_address_register

Performance

Performance of a processor is determined by:

Instruction count (why?)

Clock cycle time

Clock cycles per instruction

Processor design (datapath and control) will determine:

Clock cycle time

Clock cycles per instruction

There is more

Design of the control unitMemory technology and organizationDesign of the I/O interfacesDesign of the ALU

Computer arithmetic and hardware implementations

Design of the languagesCommunication and networking

References

Computer Architecture and Organization, John P. Hayes, Third ed., 2002MCU datasheetsHamblen, Hall and Furman, Rapid Prototyping of Digital Systems, SOPC Ed.

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Opcode Address

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Instruction Mnemonic Operation Preformed Opcode Value

ADD address AC