GT 48310A Evaluation board &Inter Connectics (IS) evaluation

Student: ZIV HARELInstructors: Moni & Inna (digital lab)

Ilan levin (Galileo)

Description :

The first goal is to evaluate the Mentor-IS tool - by using it to design a fast , problematic board , which was logically designed in Orcad Capture.

The second goal is to design & check an Expandable 8 ports fast Ethernet switch.

2 board versions : 1. Galileo’s (“very best” tool)

2. Technion’s (Mentor tool)

The board (IS view)

Project status

Board : design : done. Installation : done. Checking : done.

IS evaluation : board design : done. Simulation : done. Synthesize : done.

(for critical lines)Pre-production : done.

Final simulation: now.

Contents :

What was evaluated .The data-flow .Notes .Where did I use it ?Comparison to real board.My impression about IS .

What was evaluated

IS installation -> stabilization.Design manager installation-

>stabilization .PC/Unix versions.

Work flow.IBIS models.The IS tool :

- Simulation Validity / synthesis power . - IS Interface .

Mentor’s Support .

ORCAD to MENTOR’S IS data-flow

1 2

Create the Design in Orcad Capture

3 4

Translate the

componentsfile to Mentorformat.

Validate thepackagingand geometry data.

packages,geometry.

5

Placement ,routing

6

Translate files to IS data-base ,simulate & synthesize .

Orcad IS

editordesigner Designer(?)

Mentor board station

Notes

Orcad ->edif ->Design-arch : failed . Orcad ->comp & Netlist -> Mentor :

format mismatch : solved .Back annotation to Orcad : failed.Stable -work -flow : solved.Designer / c.editor / IS relationship:

not sorted yet...

More - notes :IBIS Models :- non-monotonic models :

work around … - availability,accuracy :

partly solved. - models for capacitors :

work around … - models for Magnetics :

failed.Synthesis: - defining the real load :

work around … - handling skew capacitors :

work around …

Where did I use it ?Fast signals:

- 125Mhz clk to 2xSdram & GT48310A. Needed 0.05ns max skew , low noise. - 83.33Mhz clk to 2xSdram & Glink & GT48310A (same as 125M_clk ). - Sdram signals - addr/data - 0.5ns delay.

Differential lines: (couldn't use the IS) Needed 0.5ns max skew , low noise. - differential Tx/Rx lines :same length , needed low : noise - 50mv max.

Comparison to real board

The comparison can’t be accurate - the boards are not identical !

IS predicted correctly signal shape and levels .

IS was too pessimist - circuit is robust!

Fast clock circuits :

125Mhz oscillator

Clk distributor

GT48310A

2 x SDRAM

83.3Mhz source

Main Clk distributor

GT48310A

2 x SDRAM

GT48300

not all resistors are drown .

Alternative supply .

125Mhz clk - after routing

125Mhz clk - on board

Core clk after routing

Core clk - on board

My impression about IS

Work flow . User interface .Stability .Synthesis power/simulation validity . Was it right ???Other tools interfacing IS.Customer support .Notes from companies tour .