GRECO - CIn - UFPE 1

A Reconfigurable Architecture for Multi-context Application

Remy Eskinazi Sant´AnnaFederal University of Pernambuco – UFPEGRECO – Engineering Computer Group

GRECO - CIn - UFPE 2

Motivation

Hardware/Software Codesign platform for fast prototyping of digital systems

Education Hardware/Software Codesign Reconfigurable systems

Industrial prototyping of digital systems

GRECO - CIn - UFPE 3

Chameleon Design Flow

System Specification

Partitioning HW/SW

Vision/51Keil

debugging

Software algorithm

Compilation

Executable code

CHAMELEON board

Hardware description

Behavioural Synthesis

RT description

Logic Synthesis

(Netlist)

Mapping

VHDL C

simulation

GRECO - CIn - UFPE 4

Hw/Sw Configuration programs flow

KeilCompiler

KeilCompiler

Source - CSource - C

.hex.hex

.bin.bin

ParserParser

Source - vhdlSource - vhdl

XILINXtools

XILINXtools

.hex.hex

.bin.bin

ParserParser

softwarehardware

MergeMerge

.mrg.mrg

GRECO - CIn - UFPE 5

Codesign Architecture

BiosensorsImage ProcessSignal Process

Acoustic Biosensor

TemperatureReconfigurable

Core Interfaces

CHardware

FPGA

Core

Selector

Codesing Architecture

bitstream

PC (Database)

Serial

GRECO - CIn - UFPE 6

Chameleon Architecture

EPROM(64K)

host

Ser

ial

com

m.

Shared memory

data

address

FPGA(84 pins)

61 I/

O p

ort

s

XC4003E->XC4013

software hardware

Mic

roco

ntr

olle

r

80C3280C5187C51..........

8

16

RAM(64K)

RDWRINT0ALEPENWSBUSY/RDYINIT DONE PROG

GRECO - CIn - UFPE 7

Hardware Reconfigurable Component

XC4000 XILINX Architecture

I/O Blocks (IOBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

OutputBuffer

InputBuffer

Q D

Pad

D QSD

RD

EC

S/RControl

D QSD

RD

EC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

ConfigurableLogic Blocks (CLBs)

Component 40003E 4005 4006 4008E 4010E 4013ELogic Cells 238 466 608 770 950 1,368Max Logic Gates 3K 5K 6K 8K 10K 13K

GRECO - CIn - UFPE 8

Monitor Program

Another File?

Core Download

End File?

Yes

Yes

Ram

Not

Configure FPGA

NotSwitch Execute code

End

Software and hardware cores

Monitor transfer control to the application

Returns to monitor

Application

GRECO - CIn - UFPE 9

Monitor Program

2kbytes

2kbytes

56kbytes(Hardware Cores)

2kbytes

2kbytes

. . .

Core 2

Core 1

Monitor variables

monitor mirror

User program

Vectors

(Sofware Cores)

Core N

GRECO - CIn - UFPE 10

Chameleon Supervisory

GRECO - CIn - UFPE 11

Chameleon Board

GRECO - CIn - UFPE 12

Conclusions

A flexible low cost prototyping board has been developed;

The platform shows to able to implement small designs in a hardware/software codesign approach;

The board has shown to be able to reduce the time during the development process of digital systems ;

Academic case studies has been implemented on the platform.

GRECO - CIn - UFPE 13

(4) (5)

(7)

(6)

(9)

)Chameleon Platform

)Oscillator Circuit Board

)Circuit Power Board

)Reset System

)Power On/Off

)Serial Communication

)Crystal Resonant Reference

)Crystal Resonant Work

)FIA System

FIGURE 7 - Case study architecture

(8)(3)

AC /DC

(1) ChameleonI

FPGA

Oscillator (2)