Gpdk090 DRM

May 31, 2007 GPDK 90nm Mixed Signal Process Spec page i

revision 3.8

Table of Contents

Revision History 2

Generator Info 3

Global Parameters 3

Introduction 4

Terminology Definitions 5

Layer Descriptions 6

Table 1: Device Layers 6

Table 2: Interconnect Layers 7

Table 3: DRC/LVS Marker/Label Layers 8

Device Layer Table 9

Table 4: MOS Device Layers 9

Table 5: Diode Device Layers 9

Table 6: Resistor Device Layers 10

Table 7: Bipolar and Varactor Device Layers 11

Device Layout Examples 12

CMOS Digital Core Design Rules 15

N BURIED LAYER RULES 15

NWELL AND NWELL RESISTOR (under STI) RULES 17NWELL RESISTOR WITHIN OXIDE RULES 19

Figure 1: NWELL RESISTOR WITHIN OXIDE RULES 19

ACTIVE RULES 21

ACTIVE RESISTOR RULES (salicided/non-salicided) 23THICK ACTIVE (2.5V) RULES 25N+ HIGH VT RULES 27

P+ HIGH VT RULES 28

NATIVE NMOS ACTIVE RULES 29

May 31, 2007 GPDK 90nm Mixed Signal Process Spec page ii

revision 3.8

...contents...

POLY RULES 30

POLY RESISTOR RULES (salicided/non-salicided) 34N+ IMPLANT RULES 36

P+ IMPLANT RULES 38

CONTACT RULES 40

SALICIDE BLOCKING RULES 43

METAL 1 RULES 44

METAL k (k = 2, 3, 4, 5, 6, 7) RULES 45METAL k (k = 8, 9) RULES 46VIA k (k = 1, 2, 3, 4, 5, 6) RULES 54VIA 7, 8 RULES 55

LATCH-UP RULES 58

METAL k (k = 1, 2, 3, 4, 5, 6, 7, 8, 9) SLOT RULES 59Metal1-9 Slot Spacing Check & Width Check - with context 59

Metal1-9/Metal1-9 Slot Enclosure Check 60

ANTENNA RULES 61

CMOS I/O Design Rules 83

ESD Design Rules 83

Bond Pad Design Rules 86

CMOS Digital Electrical Parameters 93

Sheet Resistances 93

Contact/Via Resistances 93

Current Densities 94

Contact/Via Current Densities 94

Layer and Dielectric Thickness 95

DF2 Layer Tables 98

May 31, 2007 GPDK 90nm Mixed Signal Process Spec page iii

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...contents

DF2 Layer Purposes Tables 99

Connectivity Definition 100

Appendix A A1

Appendix B B1

May 31, 2007 GPDK 90nm Mixed Signal Process Spec page 1

revision 3.8

Cadence Design Systems

GPDK 90 nm Mixed Signal GPDK Spec

DISCLAIMER

The information contained herein is provided by Cadence on an "AS IS" basis without any warranty, and Cadence has no obligation to support or otherwise maintain the information. Cadence disclaims any representation that the information does not infringe any intellectual property rights or proprietary rights of any third parties. There are no other warranties given by Cadence, whether express, implied or statutory, including, without limitation, implied warranties of merchantability and fitness for a particular purpose.

STATEMENT OF USE

This information contains confidential and proprietary information of Cadence. No part of this information may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any human or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Cadence. This information was prepared for informational purpose and is for use by Cadence customers only. Cadence reserves the right to make changes in the information at any time and without notice.


revision 3.8

Revision HistoryRELEASE NOTES FOR THE 90nm GPDK

--------------------------------------------------------------------------------

VERSION v3.9--------------------------------------------------------------------------------

- gpdk090 OA22 library built natively with IC6.1.1.500.14 release code- gpdk090 CDB library built natively with IC5.10.41_USR4.54.77 USR4 release code- Updated gate to contact spacing for high voltage MOS with DFM (CCMS 439638)- Updated implant spacing on high voltage MOS with abuttment (CCMS 439659)- Added wide metal spacing support in MOS devices (CCMS 444271)- Added 1u maximum to source/drain metal width in MOS devices- Added wide metal spacing support to diode devices- Added contact array spacing support to MOS devices- Removed integrated body tie support for HVT MOS devices due to DRC issues- Updated minimum length to 1.2u for NW resistors due to DRC issues- Removed dummy device support for metal resistors due to wide metal issues- Updated MOSCAP devices to fix callback error when DFM option was chosen

--------------------------------------------------------------------------------

VERSION v3.8--------------------------------------------------------------------------------

- gpdk090 OA22 library built natively with IC6.1.1.64 Baseline release code- gpdk090 CDB library built natively with IC5.10.41_USR4.54.77 USR4 release code- Updated techfile via spacing check from .5 to .55 for VIA7&VIA8 (CCMS 399115)- Added gpdk090.lef (Technology only) LEF file to the PDK release- Update QX files and added sensitivity corner data file for QX (PCR 938680)- Updated process techfile by doing a LefIn of the process LEF file(CCMS 403244)- Updated DRC deck to Merge Metal purposes before non45 check (CCMS 403988)- Updated MOS abuttment code to allow renaming of butted devices (CCMS 387160)

--------------------------------------------------------------------------------

VERSION v3.7--------------------------------------------------------------------------------

- gpdk090 OA22 library built natively with IC6.1.1.56 preFCS code- Added parasitc AD/AS/PD/PS calculations to the Assura extract rules- Changed PD/PS calculations to include gate periphery- Added ignore of "simM" to the CPH lam file to solve back annotation problem- Recompiled OA22 library with IC611 to fix issue with OA2LEF (PCR 939362)- Added rcx corner files for Assura using Techgen in EXT62 (PCR 938680)- Updated Circuit prospector libInit settings to match new format (PCR 941231)- Updated libInit to resolve issue with gpdk090 version printing (PCR 943345)

--------------------------------------------------------------------------------

VERSION v3.6--------------------------------------------------------------------------------

- Gpdk090 OA22 library built natively with IC6.1.0 FCS code- Changed adjacent via 3x3 check halo from 0.22 to 0.21 (PCR 932720)- Updated Assura cumulative antenna checks to use the new CAR model (PCR 928771)- Removed default simulator setting from libInit for the IC61 PDK (PCR 939589)- Removed validLayer and validVia from foundry constraint group (PCR 931826)- Updated libInit print version to use relative paths (PCR 934335)- Updated hitlite display from solid to thickline (PCR 934336)...

DRC Revision History


revision 3.8

Generator InformationSample runset for 90 nmtechnology

Default Grid: 0.005Valid Angle: 45Flag Acute: trueFlag Self-intersecting: true

Generator Info

Global Parameters

global parameters$libName gpdk090 Primitive Library Name


revision 3.8

This document defines the Design Rules and Electrical Parameters for a generic,foundary independent 90nm CMOS Mixed-Signal process.

This document is divided into three sections:

* CMOS Digital Core Design Rules

describes the widths, spacings, enclosures, overlaps, etc. needed to create the physical layout of the core section of a digital CMOS design.

* CMOS I/O Design Rules

describes the widths, spacings, enclosures, overlaps, etc. needed to create the physical layout of the I/O section of a CMOS design.

* CMOS Digital Electrical Parameters

describes the electrical parameters of a digital CMOS design.

Introduction


revision 3.8

Spacing - distance from the outside of the edge of a shape to the outside of theedge of another shape.

Terminology Definitions

Enclosure - distance from the inside of the edge of a shape to the outside of theedge of another shape.

Overlap - distance from the inside of the edge of a shape to the inside of the edgeof another shape.

Butting - outside of the edge of a shape touching the outside of the edge of anothershape.


revision 3.8

LayerName

BondpadCapMetalNburiedNhvtNimpNwellNzvtOxideOxide_thkPhvtPimpPolySiProt

GDSIIStreamNumber361419184252124235372

GDSIIDataType0000000000000

DFIILSWNameBondpadCapMetalNburiedNhvtNimpNwellNzvtOxideOxide_thkPhvtPimpPolySiProt

DFIILayerNameBondpadCapMetalNburiedNhvtNimpNwellNzvtOxideOxide_thkPhvtPimpPolySiProt

DFIILayerPurposedrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawing

DFIILayerNumber95971811126152413141016

DFIIPurposeNumber252252252252252252252252252252252252252

Description

Bonding PadMiM capacitor metalN+ Buried LayerNMOS High VtN+ ImplantNwellNMOS Zero VtActive Area2.5V Active AreaPMOS High VtP+ ImplantPolySalicide Block

Layer DescriptionsThis table describes the layers used to create devices.

Table 1: Device Layers


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LayerName

ContMetal1Metal1_slotMetal2Metal2_slotMetal3Metal3_slotMetal4Metal4_slotMetal5Metal5_slotMetal6Metal6_slotMetal7Metal7_slotMetal8Metal8_slotMetal9Metal9_slotVia1Via2Via3Via4Via5Via6Via7Via8


GDSIIDataType002020202020202020200000000

DFIILSWNameContMetal1M1_slotMetal2M2_slotMetal3M3_slotMetal4M4_slotMetal5M5_slotMetal6M6_slotMetal7M7_slotMetal8M8_slotMetal9M9_slotVia1Via2Via3Via4Via5Via6Via7Via8

DFIILayerNameContMetal1Metal1Metal2Metal2Metal3Metal3Metal4Metal4Metal5Metal5Metal6Metal6Metal7Metal7Metal8Metal8Metal9Metal9Via1Via2Via3Via4Via5Via6Via7Via8

DFIILayerPurposedrawingdrawingslotdrawingslotdrawingslotdrawingslotdrawingslotdrawingslotdrawingslotdrawingslotdrawingslotdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawing



Description

Metal Contact to Oxide/Poly1st Metal for interconnect1st Metal stress relief2nd Metal for interconnect2nd Metal stress relief3rd Metal for interconnect3rd Metal stress relief4th Metal for interconnect4th Metal stress relief5th Metal for interconnect5th Metal stress relief6th Metal for interconnect6th Metal stress relief7th Metal for interconnect7th Metal stress relief8th Metal for interconnect8th Metal stress relief9th Metal for interconnect9th Metal stress reliefVia between 1st and 2nd MetalVia between 2nd and 3rd MetalVia between 3rd and 4th MetalVia between 4th and 5th MetalVia between 5th and 6th MetalVia between 6th and 7th MetalVia between 7th and 8th MetalVia between 8th and 9th Metal

This table describes the layers used to interconnect devices.

Table 2: Interconnect Layers


revision 3.8

LayerName

BJTdumVPNP2dumVPNP5dumVPNP10dumCapdumCap3dumDIOdummyINDdummy

IND2dummy

IND3dummy

ESDdummy

Metal1_textMetal2_textMetal3_textMetal4_textMetal5_textMetal6_textMetal7_textMetal8_textMetal9_textNPNdummyPNPdummyPsub

Resdum

ResWdum

text


17

70

74

7911313335384042202125

13

71

63

GDSIIDataType00000000

0

0

0

333333333000

0

0

0

DFIILSWNameBJTdumVPNP2dumVPNP5dumVPNP10dumCapdumCap3dumDIOdumINDdum

IND2dum

IND3dum

ESDdum

Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9NPNdumPNPdumPsub

Resdum

ResWdum

text

DFIILayerNameBJTdumVPNP2dumVPNP5dumVPNP10dumCapdumCap3dumDIOdummyINDdummy

IND2dummy

IND3dummy

ESDdummy

Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9NPNdummyPNPdummyPsub

Resdum

ResWdum

text

DFIILayerPurposedrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawing

drawing

drawing

drawing

drawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawingdrawing

drawing

drawing

drawing


88

114

115

303438424650545862868480

94

98

230


252

252

252

252252252252252252252252252252252252

252

252

252

Description

Marks BJT emittersMarks BJT vpnp2Marks BJT vpnp5Marks BJT vpnp10Marks capacitorsMarks capacitors 3 termMarks diodesMarks inductorterminalMarks inductorterminalMarks inductorterminalMarks ESD and I/OdevicesLabels Metal1 nodesLabels Metal2 nodesLabels Metal3 nodesLabels Metal4 nodesLabels Metal5 nodesLabels Metal6 nodesLabels Metal7 nodesLabels Metal8 nodesLabels Metal9 nodesMarks NPN devicesMarks PNP devicesMarks seperatesubstrate areasMarks Poly/Oxideresistor areaMarks Nwell resistorarea

Text for information

This table describes the layers used to mark/label shapes for DRC and/or LVS..

Table 3: DRC/LVS Marker/Label Layers


revision 3.8

NburiedNwellOxideOxide_thkPolyNimpPimpNzvtNhvtPhvtSiProt

NMOS(1.2V)

00101100000

PMOS(1.2V)

01101010000

LP NMOS(1.2V)

00101100100

LP PMOS(1.2V)

01101010010

NMOS(2.5V)

00111100000

PMOS(2.5V)

01111010000

NativeNMOS(1.2V)00101101000

NativeNMOS(2.5V)00111101000

Device Layer TableThis table describes the layers used in each device.

0: the layer must not touch the device structure 1: the layer must enclose or straddle the device structure -: the layer may either enclose or avoid the device structure

Table 4: MOS Device Layers


N+/PWDiode00100100000

P+/NWDiode01100010000

Table 5: Diode Device Layers


revision 3.8


SalicidedN+ PolyResistor

0-

001100000

SalicidedP+ PolyResistor

0-

001010000

SalicidedN+ OxideResistor

00100100000

SalicidedP+ OxideResistor

01100010000

Non-SalicidedN+ PolyResistor0-

001100001

Non-SalicidedP+ PolyResistor0-

001010001

Non-SalicidedN+ OxideResistor00100100001

Non-SalicidedP+ OxideResistor01100010001

Table 6: Resistor Device Layers


Nwellin OxideResistor01100100001

Nwellin STIResistor01100100000


revision 3.8


SPNP

01100110000

VNPN

11100110000

Varactor(NMOSCAP)01101100000

Table 7: Bipolar and Varactor Device Layers


revision 3.8

Device Layout Examples

1.2V NMOS

2.5V NMOS

1.2V Native NMOS1.2V LP NMOS

2.5V Native NMOS

1.2V PMOS1.2V LP PMOS

Nwell

2.5V PMOS

Nwell

Oxide

Poly

Nimp

Pimp

Nzvt

Nhvt

Phvt

Cont

Substrate PNP

Nburied

Vertical NPN

PNPdummyNPNdummy

Oxide_thk


revision 3.8

Nwell

Oxide

Poly

Nimp

Pimp

Nzvt

Nhvt

Phvt

Cont

NburiedResdum

Salicided N+ Poly Resistor

Resdum

Non-Salicided N+ Poly Resistor

SiProt

Resdum Resdum

Salicided P+ Poly ResistorNon-Salicided P+ Poly Resistor

Resdum Resdum

Salicided N+ Oxide ResistorNon-Salicided N+ Oxide Resistor

Resdum Resdum

Salicided P+ Oxide ResistorNon-Salicided P+ Oxide Resistor

ResWdum

Nwell in STI Resistor

ResWdum

Nwell in OD Resistor


revision 3.8

Nwell

Oxide

Poly

Nimp

Pimp

Nzvt

Nhvt

Phvt

Cont

Nburied

SiProt

DIOdummyDIOdummy

N+/PW Diode

P+/NW Diode


revision 3.8

Nburied NburiedNwell

Nburied Nburied

Nburied Nburied Oxide

Oxide

Nburied

Pimp

Nwell

Oxide

Nburied

Nimp

Nwell

Nwell

3.2NBL.W.1

N BURIED LAYER RULESN BURIED LAYER RULESRuleNameNBL.W.1NBL.E.1NBL.SP.1NBL.SE.1NBL.SE.2NBL.SE.3NBL.SE.4NBL.X.1

Value(um)3.20.45.04.42.20.50.4---

Description

Minimum Nburied width.Minimum Nburied to Nwell enclosure.Minimum Nburied to Nburied spacing (different potential).Minimum Nburied to non-related Nwell spacing.Minimum Nburied to Oxide spacing.Minimum Nwell ring (on Nburied) to P+ Active Area spacing.Minimum Nwell ring (on Nburied) to N+ Active Area spacing.Nwell must form isolation rings on Nburied

0.4NBL.E.1

5.0diffNet

NBL.SP.1

2.2NBL.SE.2

0.5NBL.SE.3

0.4NBL.SE.4

CMOS Digital Core Design Rules

4.4NBL.SE.1


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N BURIED LAYER RULES (continued)

rule_NBL_X_1bulk

errorNBL.X.1


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Nwell nwell_conn nwell_conn

OxideNwell

Oxide

nwellres nwellres

Nimp Pimp

0.6NW.W.1

NWELL AND NWELL RESISTOR (under STI) RULESRuleNameNW.W.1NW.SP.1NW.SP.2NW.SE.1NW.SE.2NW.SE.3NW.SE.4NW.E.1NW.E.2NW.E.3NW.E.4

Value(um)0.60.61.20.30.30.50.50.120.120.70.7

Description

Minimum Nwell width.Minimum Nwell spacing to Nwell (same potential).Minimum Nwell spacing to Nwell (different potential).Minimum Nwell spacing to N+ Active Area.Minimum Nwell spacing to P+ Active Area.Minimum Nwell spacing to N+ 2.5V Active Area.Minimum Nwell spacing to P+ 2.5V Active Area.Minimum Nwell enclosure of N+ Active Area.Minimum Nwell enclosure of P+ Active Area.Minimum Nwell enclosure of N+ 2.5V Active Area.Minimum Nwell enclosure of P+ 2.5V Active Area.

NWELL AND NWELL RESISTOR (under STI) RULES

0.6sameNetNW.SP.1

1.2diffNetNW.SP.2

0.3NW.SE.2

Nwell resistor is defined by the intersection of Nwell and ResWdum for DRC and LVS.

For STI Nwell resistors, the ResWdum shape must butt the N+ Oxide on both ends of Nwell theresistor and the ResWdum shape must be coincident or extend beyond the Nwell edges along thelength of the Nwell resistor.

1.2NW.SP.2

1.2NW.SP.2

NwellOxide

NwellOxide

Nimp PimpOxide_thk Oxide_thk

0.5NW.SE.3

0.5NW.SE.4

Nwell0.3

NW.SE.1


revision 3.8

NWELL AND NWELL RESISTOR (under STI) RULES (continued)

Nwell

Oxide

Nimp

0.12NW.E.1

Nwell

OxidePimp

0.12NW.E.2

Nwell

OxideOxide_thk

0.7 shieldedNW.E.3

NimpNwell

OxideOxide_thk

Pimp

0.7 shieldedNW.E.4

! nwell_in_od_res


revision 3.8

nwell_in_od_resOxide

Contnwell_in_od_res nwell_in_od_res SiProt

Nwell

OxideSiProt

Nimp Nimp

NWELL RESISTOR WITHIN OXIDE RULESRuleNameNWR.E.1NWR.E.2NWR.SE.1NWR.E.3NWR.O.1NWR.X.1NWR.SP.1

Value(um)1.20.320.320.250.45---

1.2

Description

Minimum Active Area to Nwell (in resistor) enclosure.Minimum salicided Nwell to Contact enclosure.Minimum Resist Protect Oxide to Nwell spacing.Minimum Resist Protect Oxide to Oxide enclosure.Minimum N+ Implant to Resist Protect Oxide overlap.Thick Oxide is NOT allowed over Nwell resistor.Minimum Nwell resistor to other Nwell spacing.

NWELL RESISTOR WITHIN OXIDE RULES

1.2NWR.E.1

0.32NWR.E.2

0.32NWR.SE.1

NWR.E.1

NWR.E.2

NWR.SE.1

NWR.E.3

NWR.O.1

Figure 1: NWELL RESISTOR WITHIN OXIDE RULES

ResWdum

Nwell resistor in Oxide is defined by the intersection of Nwell and Resdum for DRC and LVS.

For Nwell resistor within Oxide, the ResWdum shape must butt the Nimp on both ends of the Nwellresistor and the ResWdum shape must be coincident or extend beyond the Nwell edges along thelength of the Nwell resistor.

SIPROT.SE.1


revision 3.8

nwell_in_od_resOxide_thk

errorNWR.X.1

NWR.E.3 - Covered bySIPROT.E.1.

NWR.SP.1 - Covered by NW.SP.2.

NWELL RESISTOR WITHIN OXIDE RULES (continued)

$layer1$dt_Nimp

$value1$id1

macro

Macro Table $layer1siprot_in_nwell_res

$dt_NimpNimp

$id1NWR.O.1

$value10.45

$message1SiProt to Nimp overlap must be >= 0.45 um

SiProt/Nimp Overlap Check - with context


revision 3.8

Oxide

Oxide

PolyNimp

Oxide

PolyPimp

ACTIVE RULESRuleNameOXIDE.W.1OXIDE.W.2.1.1OXIDE.W.2.1.2OXIDE.W.2.2.1OXIDE.W.2.2.2OXIDE.W.3OXIDE.SP.1OXIDE.SP.2OXIDE.SP.3OXIDE.SP.4OXIDE.SE.1OXIDE.A.1OXIDE.EA.1OXIDE.L.1

OXIDE.L.2

OXIDE.X.1

Value(um)0.10.120.150.120.150.130.150.150.150.180.280.060.122.0

11.0

---

Description

Minimum Active Area width.Minimum 1.2V N-channel gate width.Minimum 2.5V N-channel gate width.Minimum 1.2V P-channel gate width.Minimum 2.5V P-channel gate width.Minimum Active Area bent 45 degrees width.Minimum N+ Active Area to N+ Active Area spacing.Minimum P+ Active Area to P+ Active Area spacing.Minimum N+ Active Area to P+ Active Area spacing.Minimum Active Area bent 45 degrees to Active Area spacing.Minimum Active Area to Thick Active Area spacing.Minimum area fpr Active Area.Minimum Active Area enclosed area ("donut" hole surrounded by Active Area).Maximum Oxide length between two contacts when the Oxide width is


revision 3.8

Oxide

area >= 0.06OXIDE.A.1

Oxide_thk

ACTIVE RULES (continued)

PimpOxide

PimpOxide

Oxide Oxide

0.15OXIDE.SP.2

0.18OXIDE.SP.4

NimpOxide

NimpOxide

Oxide

0.15OXIDE.SP.1

0.13OXIDE.W.3

Oxide! Nimp

! Pimp! Nzvt

errorOXIDE.X.1

rule_OXIDE_L_1_L_2bulk

errorOXIDE.L.1_OXIDE.L.2

Oxide

area >= 0.10OXIDE.EA.1

! SiProt

Oxide 0.28shielded

OXIDE.SE.1

PimpOxide

NimpOxide

0.15OXIDE.SP.3


revision 3.8

oxide_in_resresdum_sz



SiProtoxide_in_res

Cont

ACTIVE RESISTOR RULES (salicided/non-salicided)RuleNameOXIDER.W.1.1OXIDER.W.1.2OXIDER.L.1OXIDER.SE.1OXIDER.E.1OXIDER.SE.2OXIDER.X.1

Value(um)0.21.58.00.250.250.3---

Description

Minimum Active resistor width.Minimum suggested Active resistor width.Minimum suggested Active resistor length.Minimum Salicide Block to Contact spacing.Minimum Salicide Block to Active resistor enclosure.Minimum Active resistor to N+ or P+ Implant spacing.Active resistors must have N+ or P+ Implant.

ACTIVE RESISTOR RULES (salicided/non-salicided)

Active resistor is defined by the intersection of Oxide and Resdum for DRC and LVS.

For salicided Oxide resistors, the Resdum shape must butt the contacts on both ends of Oxide theresistor and the Resdum shape must be coincident or extend beyond the Oxide edges along thelength of the Oxide resistor.

For non-salicided Oxide resistors, the Resdum shape must be coincident with the edges of the Siprotthat crosses the width of the Oxide resistor and the Resdum shape must be coincident or extendbeyond the Oxide edges along the length of the Oxide resistor.

switch !SUGGESTED_CHECK

0.2OXIDER.W.1.1

switch SUGGESTED_CHECK

1.5OXIDER.W.1.2


8.0OXIDER.L.1

0.25OXIDER.SE.1

oxide_in_res Nimp0.3

OXIDER.SE.2

oxide_in_res Pimp0.3

OXIDER.SE.2


revision 3.8

SiProt

oxide_in_res

oxide_in_res! Nimp

! Pimp

0.25OXIDER.E.1 error

OXIDER.X.1

ACTIVE RESISTOR RULES (continued)


revision 3.8

Oxide_thk Oxide_thk Oxide_thkOxide_thk Oxide_thk

THICK ACTIVE (2.5V) RULESRuleNameOXIDETHK.W.1OXIDETHK.SP.1OXIDETHK.SP.2OXIDETHK.SE.1OXIDETHK.SE.2OXIDETHK.SE.3OXIDETHK.SE.4OXIDETHK.E.1OXIDETHK.SE.5OXIDETHK.E.2

Value(um)0.70.350.750.200.200.250.280.30.340.36

Description

Minimum Thick Active Area width.Minimum Thick Active Area to Thick Active Area spacing.Minimum Thick Active Area bent 45 degrees to Thick Active Area spacing.Minimum N+ 2.5V Active Area to 2.5V N+ Active Area spacing.Minimum P+ 2.5V Active Area to 2.5V P+ Active Area spacing.Minimum N+ 2.5V Active Area to 2.5V P+ Active Area spacing.Minimum Thick Active Area to Active Area spacing.Minimum Thick Active Area to Active Area enclosure.Minimum Thick Active Area to 1.2V Poly gate spacing.Minimum Thick Active Area to Thick Poly gate enclosure.

THICK ACTIVE (2.5V) RULES

Note 1: 2.5V MOS must be defined by Active which is fully enclosed by Thick Active (with 0.0 overlap).Note 2: 1.2V MOS is only defined by Active without any Thick Active.

0.7OXIDETHK.W.1

OXIDETHK.SE.4 - Covered by OXIDE.SE.1.

0.75OXIDETHK.SP.2

0.35OXIDETHK.SP.1

Oxide

Nimp

OxideOxide_thk

0.20OXIDETHK.SE.1

Oxide

Pimp

OxideOxide_thk

0.20OXIDETHK.SE.2

Oxide

Nimp

OxideOxide_thk

Pimp

0.25OXIDETHK.SE.3


revision 3.8

Thick ACTIVE RULES (continued)

OxideOxide_thk

Poly

0.36OXIDETHK.E.2

OxideOxide_thk

OxideOxide_thk Poly

0.34OXIDETHK.SE.5

0.30OXIDETHK.E.1


revision 3.8

N+ HIGH VT RULES RULESRuleNameNHVT.X.1NHVT.X.2NHVT.X.3NHVT.X.4

Value(um)---

---

---

---

Description

Nhvt exactly matches the Oxide it is on (0.0 enclosure on all sides).Nhvt is NOT allowed on Nwell.Nhvt is NOT allowed on P+ Active.Nhvt is NOT allowed on Nzvt.

N+ HIGH VT RULES

Note 1: Nhvt defines the 1.2V LP NMOS device.

rule_NHVT_X_1bulk

errorNHVT.X.1

NhvtNwell

errorNHVT.X.2

NhvtOxide

errorNHVT.X.3

Pimp

NhvtNzvt

errorNHVT.X.4


revision 3.8

rule_PHVT_X_1bulk

Phvt! Nwell

PhvtOxide

Nimp

PhvtNzvt

P+ HIGH VT RULES RULESRuleNamePHVT.X.1PHVT.X.2PHVT.X.3PHVT.X.4

Value(um)---

---

---

---

Description

Phvt exactly matches the Oxide it is on (0.0 enclosure on all sides).Phvt is NOT allowed outside Nwell.Phvt is NOT allowed on N+ Active.Phvt is NOT allowed on Nzvt.

P+ HIGH VT RULES

Note 1: Phvt defines the 1.2V LP PMOS device.

errorPHVT.X.1

errorPHVT.X.2 error

PHVT.X.3

errorPHVT.X.4


revision 3.8

Nzvt Nzvtrule_NZVT_O_1

bulk

Nzvt Oxide

PolyOxide

Nzvt Nwell

Nzvt

NATIVE NMOS ACTIVE RULESRuleNameNZVT.W.1NZVT.SP.1NZVT.O.1NZVT.SE.1NZVT.SE.2NZVT.E.1NZVT.E.1.DFMNZVT.L.1NZVT.W.2NZVT.X.1NZVT.X.2NZVT.X.3NZVT.X.4

Value(um)0.70.60.30.281.20.20.220.90.65---

---

---

---

Description

Minimum Nzvt width.Minimum Nzvt to Nzvt spacing.Minimum and maximum Nzvt to Active Area overlap.Minimum Nzvt to Active spacing.Minimum Nzvt to Nwell spacing.Minimum N+ Poly gate end cap to Native Active Area enclosure.Minimum N+ Poly gate end cap to Native Active Area enclosure for DFM.Minimum Native device Poly gate length.Minimum Native device Poly gate width.Nzvt is NOT allowed on Nwell.Bent Poly gates are NOT allowed on Nzvt.P+ Active Area is NOT allowed on Nzvt.Only one Active Area is allowed in an Nzvt region.

NATIVE NMOS ACTIVE RULES

Note 1: Native NMOS is defined by Active which is full enclosed by Nzvt with 0.3um enclosure.

0.6NZVT.SP.1 error

NZVT.O.1

0.28NZVT.SE.1 0.2

NZVT.E.1

1.2outsideOnlyNZVT.SE.2

0.7NZVT.W.1

Nzvt

Poly

OxideNzvt

0.9NZVT.L.1

Poly

OxideNzvt

0.65NZVT.W.2

OxidePimp

Nzvt

errorNZVT.X.3

rule_NZVT_X_4bulk

errorNZVT.X.4

NZVT.X.1 - Covered byNZVT.SE.2.

NZVT.X.2 - Covered by...

switch CHECK_DFM

PolyOxide

Nzvt

0.22NZVT.E.1.DFM


revision 3.8

POLY RULESRuleNamePOLY.W.1POLY.W.2POLY.W.3POLY.W.4POLY.W.5POLY.SP.1POLY.SP.2POLY.SP.2.DFMPOLY.SP.3POLY.E.1POLY.E.2POLY.E.1.DFMPOLY.E.2.DFMPOLY.SE.1POLY.SE.2POLY.E.3POLY.W.6POLY.SP.4POLY.X.1POLY.X.2POLY.D.1POLY.SE.3POLY.A.1

Value(um)0.10.10.280.280.10.60.120.140.120.180.180.200.200.10.10.20.180.22***

***

50%250.1

Description

Minimum 1.2V N-channel gate length.Minimum 1.2V P-channel gate length.Minimum 2.5V N-channel gate length.Minimum 2.5V P-channel gate length.Minimum Poly interconnect width.Minimum Poly resistor space.Minimum gate space.Minimum gate space for DFM.Minimum Poly interconnect space.Minimum N-channel gate extension beyond Active Area.Minimum P-channel gate extension beyond Active Area.Minimum N-channel gate extension beyond Active Area for DFM.Minimum P-channel gate extension beyond Active Area for DFM.Minimum Poly interconnect to unrelated Active Area space.Minimum Poly interconnect to related Active Area space.Minimum Active Area (source/drain) to gate enclosure.Minimum bent Poly width.Minimum bent Poly space.Bent gate is not allowed.Bent Poly resistor is not allowed.Maximum Poly density across full chip.Maximum Poly segment length (width < 0.14) between two contacts.Minimum area for Poly interconnect.

POLY RULES


revision 3.8

POLY RULES (continued)

Poly! Oxide

PolyResdum

Poly

PolyOxide

Poly Poly! Oxide

Poly

0.1POLY.W.5

0.6POLY.SP.1

0.12POLY.SP.2

0.12POLY.SP.3

Poly

OxideNimp

Poly

OxidePimp

Poly

OxideOxide_thk

NimpPoly

OxideOxide_thk

Pimp

0.1POLY.W.1

0.1POLY.W.2

0.28POLY.W.3

0.28POLY.W.4

Poly

OxideNimp

Poly

OxidePimp

0.18POLY.E.1

0.18POLY.E.2


revision 3.8


Poly

OxideNimp

Poly

OxidePimp

0.20POLY.E.1.DFM

0.20POLY.E.2.DFM

switch CHECK_DFM

PolyOxide

Poly

0.14POLY.SP.2.DFM


revision 3.8


switch CHECK_DENSITYDensity

Poly

ratio


revision 3.8

POLY RESISTOR RULES (salicided/non-salicided)RuleNamePOLYR.W.1.1POLYR.W.1.2POLYR.L.1POLYR.SE.1POLYR.E.1POLYR.E.2POLYR.E.3POLYR.SE.2POLYR.X.1

Value(um)0.21.58.00.250.280.150.150.3---

Description

Minimum Poly resistor width.Minimum suggested Poly resistor width.Minimum suggested Poly resistor length.Minimum Salicide Block to Contact spacing.Minimum Salicide Block to Poly resistor enclosure.Minimum N+ Implant to Poly used in resistor enclosure.Minimum P+ Implant to Poly used in resistor enclosure.Minimum Poly resistor to other Implant spacing.Poly resistors must have N+ or P+ Implant.

POLY RESISTOR RULES (salicided/non-salicided)

Poly resistor is defined by the intersection of Poly and Resdum for DRC and LVS.

For salicided Poly resistors, the Resdum shape must butt the contacts on both ends of Poly theresistor and the Resdum shape must be coincident or extend beyond the Poly edges along the lengthof the Poly resistor.

For non-salicided Poly resistors, the Resdum shape must be coincident with the edges of the Siprotthat crosses the width of the Poly resistor and the Resdum shape must be coincident or extendbeyond the Poly edges along the length of the Poly resistor.

poly_in_resresdum_sz

SiProtpoly_in_res

Cont


8.0POLYR.L.1

0.25POLYR.SE.1



switch !SUGGESTED_CHECK

0.2POLYR.W.1.1


1.5POLYR.W.1.2


revision 3.8

poly_in_res! Nimp

! Pimp

errorPOLYR.X.1

POLY RESISTOR RULES (continued)

poly_in_res Nimp poly_in_res Nzvt

poly_in_res Pimp

0.3POLYR.SE.2

0.3outsideOnlyPOLYR.SE.2

0.3POLYR.SE.2

SiProt

poly_in_res

Nimp

poly_in_res

Pimp

poly_in_res

0.28POLYR.E.1

0.15POLYR.E.2

0.15POLYR.E.3


revision 3.8

Nimp Nimp Nimp

Oxide

Nimp

Nimp! Oxide

OxidePimp

NwellOxide

Nimp

Oxide

NimpNwell

OxideNimp

Poly

! Nwell

N+ IMPLANT RULESRuleNameNIMP.W.1NIMP.SP.1NIMP.E.1NIMP.O.1NIMP.SE.1NIMP.E.2NIMP.E.3NIMP.SE.2NIMP.E.4NIMP.SE.3NIMP.A.1NIMP.EA.1NIMP.X.1

Value(um)0.240.240.140.160.160.020.180.020.180.180.150.16---

Description

Minimum N+ Implant width.Minimum N+ Implant space.Minimum N+ Implant to Active Area enclosure.Minimum N+ Implant to Active Area overlap.Minimum N+ Implant to P+ Active (inside Nwell) Area spacing.Minimum N+ Implant to Active Area (Nwell tie) enclosure.Minimum N+ Implant to gate side enclosure.Minimum N+ Implant to P+ Active Area (substrate tie) spacing.Minimum N+ to gate (endcap) enclosure.Minimum N+ Implant to P+ gate side (butted Implant) spacing.Minimum area for N+ Implant.Minimum N+ Implant ring enclosed area ("donut" hole surrounded by N+ Implant).N+ Implant is NOT allowed over P+ Implant.

N+ IMPLANT RULES

0.24NIMP.W.1

0.24NIMP.SP.1 0.14

NIMP.E.1

0.16NIMP.SE.1

0.16NIMP.O.1

0.02NIMP.E.2

0.18NIMP.E.3


revision 3.8

PolyOxide

Nimp

Poly

OxidePimp Nimp

Nimp

Nimp! Oxide

OxidePimp

! Nwell

N+ IMPLANT RULES (continued)

0.18NIMP.E.4

0.18NIMP.SE.3

area >= 0.15NIMP.A.1

0.02NIMP.SE.2

Nimp

area >= 0.16NIMP.EA.1

NimpPimp

errorNIMP.X.1


revision 3.8

Pimp Pimp Pimp

Oxide

Pimp

Pimp! Oxide

OxideNimp

! NwellOxide

Pimp

Nwell

Oxide

Pimp! Nwell

OxidePimp

Poly

P+ IMPLANT RULESRuleNamePIMP.W.1PIMP.SP.1PIMP.E.1PIMP.O.1PIMP.SE.1PIMP.E.2PIMP.E.3PIMP.SE.2PIMP.E.4PIMP.SE.3PIMP.A.1PIMP.EA.1PIMP.X.1

Value(um)0.240.240.140.160.160.020.180.020.180.180.150.16---

Description

Minimum P+ Implant width.Minimum P+ Implant space.Minimum P+ Implant to Active Area enclosure.Minimum P+ Implant to Active Area overlap.Minimum P+ Implant to N+ Active (outside Nwell) Area spacing.Minimum P+ Implant to Active Area (substrate tie) enclosure.Minimum P+ Implant to gate side enclosure.Minimum P+ Implant to N+ Active Area (Nwell tie) spacing.Minimum P+ to gate (endcap) enclosure.Minimum P+ Implant to N+ gate side (butted Implant) spacing.Minimum area for P+ Implant.Minimum P+ Implant ring enclosed area ("donut" hole surrounded by P+ Implant).P+ Implant is NOT allowed over N+ Implant.

P+ IMPLANT RULES

0.24PIMP.W.1

0.24PIMP.SP.1 0.14

PIMP.E.1

0.16PIMP.SE.1

0.16PIMP.O.1

0.02PIMP.E.2

0.18PIMP.E.3


revision 3.8

PolyOxide

Pimp

Poly

OxideNimp Pimp

Pimp

Pimp! Oxide

OxideNimp

Nwell

Pimp

P+ IMPLANT RULES (continued)

0.18PIMP.E.4

0.18PIMP.SE.3

area >= 0.15PIMP.A.1

0.02PIMP.SE.2

area >= 0.16PIMP.EA.1

PIMP.X.1 - Covered by NIMP.X.1.


revision 3.8

Cont Cont Cont

CONTACT RULESRuleNameCONT.W.1CONT.SP.1CONT.SP.2

CONT.SE.1CONT.SE.2CONT.SE.3CONT.SE.4CONT.SE.1.DFMCONT.SE.2.DFMCONT.SE.3.DFMCONT.SE.4.DFMCONT.E.1CONT.E.2CONT.E.3CONT.E.4CONT.SE.5

CONT.X.1CONT.X.2CONT.X.3

Value(um)0.120.140.16

0.100.120.120.140.120.140.140.160.060.040.060.060.24

---

---

---

Description

Maximum and minimum Contact width/length.Minimum Contact to Contact spacing.Minimum Contact to Contact spacing when the Contacts are in a 3x3 or largerarray (minimum dimension on one side of array is 3). Contacts spaced lessthan 0.18um should be considered for array spacing check.Minimum Contact on Active Area to gate spacing.Minimum Contact on 2.5V Active Area to gate spacing.Minimum gate Contact to Active Area spacing.Minimum 2.5V gate Contact to Active Area spacing.Minimum Contact on Active Area to gate spacing for DFM.Minimum Contact on 2.5V Active Area to gate spacing for DFM.Minimum gate Contact to Active Area spacing for DFM.Minimum 2.5V gate Contact to Active Area spacing for DFM.Minimum Active Area to Contact enclosure.Minimum Poly to Contact enclosure.Minimum Poly to Contact enclosure on at least two opposite sides (end of line).Minimum N+/P+ Implant on Active Area to Contact enclosure.Minimum Poly Contact to non-salacided Poly resistor or Active Contact tonon-salacided Active resistor spacing.Contact on gate is NOT allowed,Active Area Contact on N+/P+ Implant edge is NOT allowed.Contact must be covered by Metal1 and Active Area or Poly.

CONTACT RULES

0.12x0.12CONT.W.1

0.14CONT.SP.1

Cont Cont0.16

array 3x3halo 0.09

CONT.SP.2


revision 3.8

CONTACT RULES (continued)

ContOxide

Poly

ContPoly

Oxide

ContOxide

PolyOxide_thk

ContPoly

OxideOxide_thk

0.12CONT.SE.1.DFM

0.14CONT.SE.3.DFM

0.14CONT.SE.2.DFM

0.16CONT.SE.4.DFM

switch CHECK_DFM

ContOxide

Poly

ContPoly

Oxide

ContOxide

PolyOxide_thk

ContPoly

OxideOxide_thk

0.10CONT.SE.1

0.12CONT.SE.3

0.12CONT.SE.2

0.14CONT.SE.4


revision 3.8

CONTACT RULES (continued)

Cont! Oxide

! Poly

errorCONT.X.3

OxideCont

Poly

OxideCont

NimpOxide

Cont

Pimp

errorCONT.X.1

segment < 0.005CONT.X.2

segment < 0.005CONT.X.2

OxideCont

PolyCont

PolyCont

Nimp

ContOxide

Pimp

ContOxide

0.06CONT.E.1

0.04CONT.E.2

0.06oppSidesCONT.E.3

0.06CONT.E.4

0.06CONT.E.4

CONT.SE.5 - Covered by SIPROT.SE.1.


revision 3.8

SiProt SiProt SiProt SiProt Cont

OxideSiProtOxide

Poly SiProt

SiProt

Oxide

OxideSiProt

Poly! Oxide

SiProt

SALICIDE BLOCKING RULESRuleNameSIPROT.W.1SIPROT.SP.1SIPROT.SE.1SIPROT.SE.2SIPROT.SE.3SIPROT.E.1SIPROT.E.2SIPROT.E.3SIPROT.A.1SIPROT.EA.1SIPROT.SE.4

Value(um)0.440.440.240.240.440.250.240.281.21.20.35

Description

Minimum Salicide Block width.Minimum Salicide Block space.Minimum Salicide Block to Contact spacing.Minimum Salicide Block to unrelated Active Area spacing.Minimum Salicide Block to gate spacing.Minimum Salicide Block to Active Area enclosure.Minimum Active Area to Salicide Block enclosure.Minimum Salicide Block to Poly (on field) enclosure.Minimum Salicide Block area.Minimum Salicide Block enclosed area ("donut" hole surrounded by Salicide Block).Minimum Salicide Block to Poly (on field) spacing.

SALICIDE BLOCKING RULES

0.44SIPROT.W.1

0.44SIPROT.SP.1

0.24SIPROT.SE.1

0.24SIPROT.SE.2

0.44SIPROT.SE.3

0.25 shieldedSIPROT.E.1

0.24SIPROT.E.2 0.28

SIPROT.E.3

! Resdum

SiProtarea >= 1.2SIPROT.A.1

SiProt

area >= 1.2SIPROT.EA.1

Poly

! Oxide

SiProt0.35

SIPROT.SE.4


revision 3.8

METAL 1 RULESRuleNameMETAL1.W.1METAL1.W.2METAL1.SP.1.1

METAL1.SP.1.2METAL1.SP.1.3METAL1.SP.1.4METAL1.SP.1.5METAL1.SP.1.6METAL1.E.1METAL1.E.2

METAL1.L.1METAL1.SP.2METAL1.W.3METAL1.A.1METAL1.D.1

METAL1.D.2

Value(um)0.1212.00.12

0.180.500.901.502.500.000.06

0.180.160.140.07> 20%< 65%< 60%

Description

Minimum Metal 1 width.Maximum Metal 1 width.Minimum Metal 1 to Metal 1 spacing.Minimum Metal 1 to Metal 1 spacing if:one metal width > 0.18 and parallel length > 0.56.one metal width > 1.5 and parallel length > 1.5.one metal width > 3.0 and parallel length > 3.0.one metal width > 4.5 and parallel length > 4.5.one metal width > 7.5 and parallel length > 7.5.Minimum Metal 1 to Contact enclosure.Minimum Metal 1 to Contact enclsoure on two opposite sides of theContact.Minimum bent Metal 1 (45 degree angle) length.Minimum bent Metal 1 (45 degree angle) space.Minimum bent Metal 1 (45 degree angle) width.Minimum Metal1 area.Metal 1 Density range over any 120um x 120um area (checked by steppingin 60um increments).Maximum Metal 1 density over any 600um x 600um area (checked bystepping in 300um increments).

METAL 1 RULES


revision 3.8

METAL k ( k = 2, 3, 4, 5, 6, 7) RULESRuleNameMETALk.W.1METALk.W.2METALk.SP.1.1

METALk.SP.1.2METALk.SP.1.3METALk.SP.1.4METALk.SP.1.5METALk.SP.1.6METALk.E.1METALk.E.2METALk.L.1METALk.SP.2METALk.W.3METALk.A.1METALk.D.1

METALk.D.2

Value(um)0.1412.00.14

0.200.500.901.502.500.0050.060.200.180.160.08> 20%< 65%< 60%

Description

Minimum Metal k width.Maximum Metal k width.Minimum Metal k to Metal k spacing.Minimum Metal k to Metal k spacing if:one Metal k width > 0.20 and parallel length > 0.56.one Metal k width > 1.5 and parallel length > 1.5.one Metal k width > 3.0 and parallel length > 3.0.one Metal k width > 4.5 and parallel length > 4.5.one Metal k width > 7.5 and parallel length > 7.5.Minimum Metal k enclosure of Via k-1.Minimum Metal k enclosure of Via k-1on at least two opposite sides.Minimum bent Metal k (45 degree angle) length.Minimum bent Metal k (45 degree angle) space.Minimum bent Metal k (45 degree angle) width.Minimum Metal k area.Metal k Density range over any 120um x 120um area (checked by steppingin 60um increments).Maximum Metal k density over any 600um x 600um area (checked bystepping in 300um increments).

METAL k (k = 2, 3, 4, 5, 6, 7) RULES


revision 3.8

METAL k (k = 8, 9) RULESRuleNameMETALk.W.1METALk.W.2METALk.SP.1.1

METALk.SP.1.2METALk.SP.1.3METALk.SP.1.4METALk.SP.1.5METALk.E.1METALk.E.2METALk.A.1METALk.D.1

METALk.D.2

Value(um)0.4412.00.40

0.500.901.502.500.050.10.20> 20%< 65%< 60%

Description

Minimum Metal k width.Maximum Metal k width.Minimum Metal k to Metal k spacing.Minimum Metal k to Metal k spacing if:one Metal k width > 1.50 and parallel length > 1.50.one Metal k width > 3.00 and parallel length > 3.00.one Metal k width > 4.50 and parallel length > 4.50.one Metal k width > 7.5 and parallel length > 7.5.Minimum Metal k overlap of Via k-1.Minimum Metal k overlap of Via k-1 on at least two opposite sides.Minimum Metal k area.Metal k Density range over any 120um x 120um area (checked by steppingin 60um increments).Maximum Metal k density over any 600um x 600um area (checked bystepping in 300um increments).

METAL k (k = 8, 9) RULES


revision 3.8

Cont! metal1_conn

Contmetal1_conn

$layer2$layer1

$layer2$layer1

$layer2$layer1

$layer2$layer1

0.06 oppSidesMETAL1.E.2

METAL RULES (continued)

0.005insideOnly$id1

0.06 oppSides$id2

macro

Macro Table $name1Metal2Metal3Metal4Metal5Metal6Metal7

$layer1metal2_connmetal3_connmetal4_connmetal5_connmetal6_connmetal7_conn

$layer2Via1Via2Via3Via4Via5Via6

$id1METAL2.E.1METAL3.E.1METAL4.E.1METAL5.E.1METAL6.E.1METAL7.E.1

$id2METAL2.E.2METAL3.E.2METAL4.E.2METAL5.E.2METAL6.E.2METAL7.E.2

0.05insideOnly$id1

0.1 oppSides$id2

macro

Macro Table $name1Metal8Metal9

$layer1metal8_connmetal9_conn

$layer2Via7Via8

$id1METAL8.E.1METAL9.E.1

$id2METAL8.E.2METAL9.E.2

errorMETAL1.E.1


revision 3.8

$layer1

$layer1! $layer2

! $layer3

macro


$value1$id1

Macro Table $layer1metal1_connmetal2_connmetal3_connmetal4_connmetal5_connmetal6_connmetal7_connmetal8_connmetal9_conn

$name1Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9

$id1METAL1.W.1METAL2.W.1METAL3.W.1METAL4.W.1METAL5.W.1METAL6.W.1METAL7.W.1METAL8.W.1METAL9.W.1

$value10.120.140.140.140.140.140.140.440.44

macro

Macro Table $layer1metal1_connmetal2_connmetal3_connmetal4_connmetal5_connmetal6_conn

$layer2cont_array_zonevia1_array_zonevia2_array_zonevia3_array_zonevia4_array_zonevia5_array_zone

$layer3via1_array_zonevia2_array_zonevia3_array_zonevia4_array_zonevia5_array_zonevia6_array_zone

$name1Metal1Metal2Metal3Metal4Metal5Metal6

$id1METAL1.W.2METAL2.W.2METAL3.W.2METAL4.W.2METAL5.W.2METAL6.W.2

$value112.012.012.012.012.012.0


revision 3.8


$layer1 $layer1$value1 projectwidth a > $value2

errLength a > $value3$id1a b

Macro Table $layer1Metal1Metal2Metal3Metal4Metal5Metal6Metal7

$id1METAL1.SP.1.2METAL2.SP.1.2METAL3.SP.1.2METAL4.SP.1.2METAL5.SP.1.2METAL6.SP.1.2METAL7.SP.1.2

$value10.180.200.200.200.200.200.20

$value20.180.200.200.200.200.200.20

$value30.560.560.560.560.560.560.56

macro

$layer1 $layer1

$value1$id1

Macro Table $layer1Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9

$id1METAL1.SP.1.1METAL2.SP.1.1METAL3.SP.1.1METAL4.SP.1.1METAL5.SP.1.1METAL6.SP.1.1METAL7.SP.1.1METAL8.SP.1.1METAL9.SP.1.1

$value10.120.140.140.140.140.140.140.400.40

macro

$layer1

macro

Macro Table $layer1metal8_connmetal9_conn

$name1Metal8Metal9

$id1METAL8.W.2METAL9.W.2

$value112.012.0


revision 3.8

$layer1 $layer1

$layer1 $layer1

$layer1 $layer1

macro




0.50 projectwidth a > 1.50

errLength a > 1.50$id1a b

macro





macro






revision 3.8

$layer1 $layer1

$layer1

$layer1$layer1

macro






macro


$id1METAL1.L.1METAL2.L.1METAL3.L.1METAL4.L.1METAL5.L.1METAL6.L.1METAL7.L.1

$value10.180.200.200.200.200.200.20

segment >= $value1$id1

macro


$id1METAL1.SP.2METAL2.SP.2METAL3.SP.2METAL4.SP.2METAL5.SP.2METAL6.SP.2METAL7.SP.2

$value10.160.180.180.180.180.180.18

$id2METAL1.W.3METAL2.W.3METAL3.W.3METAL4.W.3METAL5.W.3METAL6.W.3METAL7.W.3

$value20.140.160.160.160.160.160.16

$value1$id1 $value2

$id2


revision 3.8

$layer1macro



$id1METAL1.A.1METAL2.A.1METAL3.A.1METAL4.A.1METAL5.A.1METAL6.A.1METAL7.A.1METAL8.A.1METAL9.A.1

$value10.070.080.080.080.080.080.080.20.2

area >= $value1$id1


revision 3.8


$layer1

switch CHECK_DENSITY

Density

ratio >= 0.20 = 20%


revision 3.8

VIA k (k = 1, 2, 3, 4, 5, 6) RULESRuleNameVIAk.W.1VIAk.SP.1VIAk.SP.2

VIAk.E.1VIAk.E.2VIAk.X.1

VIAk.X.2

VIAk.X.3

VIAk.X.4

Value(um)0.140.150.20

0.0050.06---

---

---

---

Description

Minimum and maximum Via k width.Minimum Via k to Via k spacing.Minimum Via k to Via k spacing when the Via ks are in a 3x3 or largerarray (minimum dimension on one side of array is 3). Via ks spaced lessthan 0.21um should be considered for array spacing check.Minimum Metal k to Via k enclosure.Minimum Metal k to Via k enclosure on at least two opposite sides of Via k.Minimum of two Via k with spacing


revision 3.8

VIA k (k = 7, 8) RULESRuleNameVIAk.W.1VIAk.SP.1VIAk.E.1VIAk.E.2

Value(um)0.360.360.030.08

Description

Minimum and maximum Via k width.Minimum Via k space.Minimum Metal k to of Via k enclosure.Minimum Metal k to Via k enclosure on at least two opposite sides of Via k.

VIA 7, 8 RULES


revision 3.8

$layer1 $layer1 $layer1

VIA RULES (continued)macro

Macro Table $layer1Via1Via2Via3Via4Via5Via6Via7Via8

$id1VIA1.W.1VIA2.W.1VIA3.W.1VIA4.W.1VIA5.W.1VIA6.W.1VIA7.W.1VIA8.W.1

$value10.14x0.140.14x0.140.14x0.140.14x0.140.14x0.140.14x0.140.36x0.360.36x0.36

$id2VIA1.SP.1VIA2.SP.1VIA3.SP.1VIA4.SP.1VIA5.SP.1VIA6.SP.1VIA7.SP.1VIA8.SP.1

$value20.150.150.150.150.150.150.360.36

$id3VIA1.SP.2VIA2.SP.2VIA3.SP.2VIA4.SP.2VIA5.SP.2VIA6.SP.2ignoreignore

$value30.200.200.200.200.200.20ignoreignore

$halo30.100.100.100.100.100.10ignoreignore

$value1$id1

$value2$id2

$layer1$layer2

$layer1$layer2

macro

Macro Table $name1Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8

$layer1Via1Via2Via3Via4Via5Via6Via7Via8

$layer2metal1_connmetal2_connmetal3_connmetal4_connmetal5_connmetal6_connmetal7_connmetal8_conn

$id1VIA1.E.1VIA2.E.1VIA3.E.1VIA4.E.1VIA5.E.1VIA6.E.1VIA7.E.1VIA8.E.1

$value10.0050.0050.0050.0050.0050.0050.030.03

$id2VIA1.E.2VIA2.E.2VIA3.E.2VIA4.E.2VIA5.E.2VIA6.E.2VIA7.E.2VIA8.E.2

$value20.060.060.060.060.060.060.080.08

$value1insideOnly$id1

$value2oppSides$id2

$layer1 $layer1$value3

array 3x3halo $halo3

$id3


revision 3.8

VIA RULES (continued)macro

Macro Table $name1Via1Via2Via3Via4Via5Via6



$layer1rule_VIA1_X_1rule_VIA2_X_1rule_VIA3_X_1rule_VIA4_X_1rule_VIA5_X_1rule_VIA6_X_1

$id1VIA1.X.1VIA2.X.1VIA3.X.1VIA4.X.1VIA5.X.1VIA6.X.1

$layer1bulk

error$id1

$layer1bulk

macro

Macro Table $name1Via1Via2Via3Via4Via5Via6



$layer1rule_VIA1_X_2rule_VIA2_X_2rule_VIA3_X_2rule_VIA4_X_2rule_VIA5_X_2rule_VIA6_X_2

$id1VIA1.X.2VIA2.X.2VIA3.X.2VIA4.X.2VIA5.X.2VIA6.X.2

error$id1

$layer1bulk

macro

Macro Table $name1Metal1Metal2

$name2Metal6Metal7

$layer1rule_VIAk_X_3_X_4arule_VIAk_X_3_X_4b

$id1VIAk.X.3_VIAk.X.4VIAk.X.3_VIAk.X.4 error$id1



revision 3.8

Nwell

ntap psd

ptap nsd

! Nwell


revision 3.8

$layer1 $layer1 $layer1

! $layer2

METAL k (k = 1, 2, 3, 4, 5, 6, 7, 8, 9) SLOT RULESMETAL k (k = 1, 2, 3, 4, 5, 6, 7, 8, 9) SLOT RULESRuleNameMSLOTk.W.1MSLOTk.L.1MSLOTk.SP.1

MSLOTk.E.1

MSLOTk.X.1

MSLOTk.X.2

MSLOTk.X.3MSLOTk.X.4MSLOTk.X.5MSLOTk.X.6

Value(um)2.02.0M1/M2-7/M8,M90.12/0.14/0.44M1/M2-7/M8,M90.12/0.14/0.44

Description

Minimum Metal k Slot width.Minimum Metal k Slot length.Minimum Metal k Slot to Metal k Slot spacing (equal to the minimumMetal k width).Minimum Metal k to Metal k Slot enclosure (equal to the minimumMetal k width).Metal k Slots must be added to Metal k with both width and lengthgreater than 12.0um.The length of Metal k Slots should be parallel to the direction of thecurrent flow.Metal k Slot rules do not apply to Contact and Via array areas.Metal k Slot rules do not apply to bond pad areas.Metal k Slots must be rectangular or square.After Metal k Slots are added, Metal k must still meet densityrequirements.

macro

Macro Table $layer1Metal1_slotMetal2_slotMetal3_slotMetal4_slotMetal5_slotMetal6_slotMetal7_slotMetal8_slotMetal9_slot

$layer2BondpadBondpadBondpadBondpadBondpadBondpadBondpadBondpadBondpad

$name1Metal1 SlotMetal2 SlotMetal3 SlotMetal4 SlotMetal5 SlotMetal6 SlotMetal7 SlotMetal8 SlotMetal9 Slot

$id1MSLOT1.W.1_MSLOT1.L.1MSLOT2.W.1_MSLOT2.L.1MSLOT3.W.1_MSLOT3.L.1MSLOT4.W.1_MSLOT4.L.1MSLOT5.W.1_MSLOT5.L.1MSLOT6.W.1_MSLOT6.L.1MSLOT7.W.1_MSLOT7.L.1MSLOT8.W.1_MSLOT8.L.1MSLOT9.W.1_MSLOT9.L.1

$value12.02.02.02.02.02.02.02.02.0

$id2MSLOT1.SP.1MSLOT2.SP.1MSLOT3.SP.1MSLOT4.SP.1MSLOT5.SP.1MSLOT6.SP.1MSLOT7.SP.1MSLOT8.SP.1MSLOT9.SP.1

$value20.120.140.140.140.140.140.140.440.44

$value1$id1

$value2$id2

Metal1-9 Slot Spacing Check & Width Check - with context


revision 3.8

METAL k (k = 1, 2, 3, 4, 5, 6, 7, 8, 9) SLOT RULES (continued)

$layer1$layer2

macro

Macro Table $layer1Metal1_slot_not_BPMetal2_slot_not_BPMetal3_slot_not_BPMetal4_slot_not_BPMetal5_slot_not_BPMetal6_slot_not_BPMetal7_slot_not_BPMetal8_slot_not_BPMetal9_slot_not_BP

$layer2Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9

$name1Metal1 SlotMetal2 SlotMetal3 SlotMetal4 SlotMetal5 SlotMetal6 SlotMetal7 SlotMetal8 SlotMetal9 Slot

$id1MSLOT1.E.1MSLOT2.E.1MSLOT3.E.1MSLOT4.E.1MSLOT5.E.1MSLOT6.E.1MSLOT7.E.1MSLOT8.E.1MSLOT9.E.1

$value10.120.140.140.140.140.140.140.440.44

Metal1-9/Metal1-9 Slot Enclosure Check


revision 3.8

ANTENNA RULESRuleNameANT.1ANT.2ANT.3

ANT.4.Mx

ANT.5.Vx

ANT.6.Mx(x = 2, 3, 4, 5,6, 7, 8, 9)

Value(um)275.0550.015.0

475.0

25.0

1200.0

Description

Maximum ratio of Poly area to the gate area the Poly is connected to.Maximum ratio of Poly sidewall area to the gate area the Poly is connected to.Maximum ratio of Poly Contact area to the gate area the Contact is connectedwith.Maximum ratio of single level Metal x (x = 1, 2, 3, 4, 5, 6, 7, 8, 9) area to the (gate area + 2*Diff area)Maximum ratio of single level Via x (x = 1, 2, 3, 4, 5, 6, 7, 8) area to the (gate area + 2*Diff area)Maximum ratio of cummulative multi level Metal areas to the (gate area + 2*Diff area)

ANTENNA RULES

Note 1: Source/drain diffusion areas of MOS devices are counted as part of the diode area.Note 2: It is recommended to use one large diode with multiple Contacts rather than several smaller diodes.


revision 3.8

gate

Polypoly_tap

poly_on_field

gate

Polypoly_tap

poly_on_field

gate

Polycont_poly

cont_antenna

gate

Polycont_poly

metal1_conn

ANTENNA RULES (continued)

Antennaswitch !SKIP_CHECK_POLY_ANT_1

ratio (poly_on_field.area / gate.area)


revision 3.8

gate

Polycont_poly

metal1_conn

Antenna

ratio (metal2_conn.area / (gate.area + 2*diff_diode.area))


revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connAntenna



revision 3.8


gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_conn

switch !SKIP_CHECK_METAL8_ANT_4Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_connVia7

metal8_conn

ANTENNA RULES (continued)switch !SKIP_CHECK_METAL9_ANT_4

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

ANTENNA RULES (continued)switch !SKIP_CHECK_VIA1_ANT_5

Antenna

ratio (Via1.area / (gate.area + 2*diff_diode.area))


revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connAntenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_conn


Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_conn


Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_connVia7

metal8_conn


Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_connVia7

metal8_connVia8

metal9_conn


Antenna



revision 3.8


gate

Polycont_poly

metal1_connVia1

metal2_conn

Antenna

id: ANT.6.M2message: Cumulative Metal1 through Metal2 area to (gate area + 2*diff_diode.area) ratiomust be


revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_conn

Antenna



revision 3.8

gate

Polycont_poly

metal1_connVia1

metal2_connVia2

metal3_connVia3

metal4_connVia4

metal5_connVia5

metal6_connVia6

metal7_connVia7

metal8_conn

Antenna



revision 3.8

CMOS I/O Design Rules

The "ESDdummy" marker layer must be used to mark I/O ESD circuitry. If the"ESDdummy" layer is not used, the correct DRC checks of I/O ESD circuitry will nottake place.

NMOS and PMOS devices used for ESD protection follow a strict finger structure usingspecific finger dimaensions and layout.

ESD Design RulesRuleNameESD.1

ESD.2

ESD.3ESD.4

ESD.5ESD.6ESD.7ESD.8

ESD.9

ESD.10

ESD.11ESD.12

ESD.13ESD.14

ESD.15

Value(um)15 - 65

390

390

0.051.8

1.80.3

0.25

Description

Width of each finger of NMOS and PMOS in I/O buffers and in Vdd to Vss ESDprotection.Minimum NMOS combined finger width for I/O buffers and for Vdd to Vss ESDprotection.Minimum PMOS combined finger width for I/O buffers.Outer Oxide area of NMOS and PMOS in I/O buffers and in Vdd to Vss ESDprotection must be Source or connected to Bulk to prevent parasitic bipolarsand unwanted discharge paths during ESD zapping.NMOS ESD protection devices must be surrounded by a P+ Guard Ring.PMOS ESD protection devices must be surrounded by an N+ Guard Ring.NMOS and PMOS in ESD protection can NOT have butted taps.NMOS and PMOS in an I/O buffer must have non-salicided Drains. TheContacts still must be salicided.A P+ Oxide strap should be placed between N+ Oxides of different I/O andESD devices when both connect to different pads.An N+ Oxide strap should be placed between P+ Oxides of different I/O andESD devices when both connect to different pads.Minimum SiProt to Poly gate overlap in NMOS and PMOS drains.Minimum enclosure of SiProt edge to Poly gate edge in NMOS and PMOS I/Odrains.Minimum SiProt to Oxide overlap in NMOS and PMOS I/O drains.Exact gate length of NMOS and PMOS in I/O buffers and in Vdd to Vss ESDprotection.Minimum Poly gate to Contact spacing in NMOS and PMOS in I/O buffers andin Vdd to Vss ESD protection.

ESD Design Rules


revision 3.8

ESD Design Rules (continued)

PolyOxide

segment >= 15.0


revision 3.8

ESDdummy

ESD Design Rules (continued)

OxideSiProt

OxidePoly

OxidePoly

Cont

1.8ESD.13

segment == 0.3ESD.14

0.25ESD.15


revision 3.8

Bond Pad Design Rules

In-Line Bond Pad Design RulesRuleNameBONDPAD.W.1BONDPAD.L.1BONDPAD.SP.1BONDPAD.E.1BONDPAD.SP.2BONDPAD.B.1

BONDPAD.W.2BONDPAD.W.3BONDPAD.SP.3BONDPAD.SP.4BONDPAD.E.2

BONDPAD.E.3

BONDPAD.R.1

BONDPAD.R.2

BONDPAD.SP.5BONDPAD.W.4

BONDPAD.W.5

BONDPAD.SP.6

BONDPAD.SP.7

Value(um)52.068.08.02.03.01.8~3.2

0.140.360.220.540.05

0.09

16.0

4.0

1.51.0

5.0

1.0~3.5

1.1

Description

Minimum Bondpad width of edges parallel to the die edge.Minimum Bondpad length of edges perpendicular to the die edge.Minimum Bondpad to Bondpad metal spacing.Minimum Metal (all levels) enclosure of Bondpad.Minimum Bondpad Metal to Metal (including Bondpad Metal) spacing.Minimum length of Bonpad Metal beveled corner. All Bonpad Metalcorners must be beveled at 45 degrees.Minimum and maximum Bondpad Via k width (k = 1, 2, 3, 4, 5, 6).Minimum and maximum Bondpad Via k width (k = 7, 8).Minimum Bondpad Viak to Bondpad Viak spacing (k = 1, 2, 3, 4, 5, 6).Minimum Bondpad Viak to Bondpad Viak spacing (k = 7, 8).Minimum Bondpad Metalk to Bondpad Viak enclosure(k = 1, 2, 3, 4, 5, 6).Minimum Bondpad Metalk+1 to Bondpad Viak enclosure(k = 1, 2, 3, 4, 5, 6).Minimum Bondpad Metalk to Bondpad Viak enclosure(k = 7, 8).Minimum Bondpad Metalk+1 to Bondpad Viak enclosure(k = 7, 8).Minimum Bondpad Viak inside Metalk to Metalk+1 crossing(k = 1, 2, 3, 4, 5, 6).Minimum Bondpad Viak inside Metalk to Metalk+1 crossing(k = 7, 8).Minimum and Maximum Pad Metal slot to Pad Metal slot spacing.Minimum and Maximum Pad Metal slot width (expect first slot on eachedge of Pad).Minimum and Maximum Pad Metalk width in outer ring of Pad Metalk(expect for the bevelled corners) (k = 1, 2, 3, 4, 5, 6, 7, 8).Minimum and Maximum Pad Metalk ring to nearest Pad Metalk acrossfirst slot (k = 1, 2, 3, 4, 5, 6, 7, 8).Minimum Pad Viak array to Pad Viak array spacing (k = 1, 2, 3, 4, 5, 6, 7, 8).

1) The bond pad structure must contain all Metal levels and all Via levels.2) Metals over the Bonpad area are slotted with 1um slots spaced 1.5um.3) The top metal is solid and does not contain stress slots.


revision 3.8

Bond Pad Design Rules (continued)

rule_Bondpad_Missing_M1

rule_Bondpad_Missing_V1

errorBONDPAD.O.1

rule_Bondpad_Missing_M2errorBONDPAD.O.1

rule_Bondpad_Missing_M3errorBONDPAD.O.1

rule_Bondpad_Missing_M4 rule_Bondpad_Missing_M5 rule_Bondpad_Missing_M6errorBONDPAD.O.1

errorBONDPAD.O.1

errorBONDPAD.O.1

rule_Bondpad_Missing_M7 rule_Bondpad_Missing_M8 rule_Bondpad_Missing_M9errorBONDPAD.O.1

errorBONDPAD.O.1

errorBONDPAD.O.1

errorBONDPAD.O.2

rule_Bondpad_Missing_V2errorBONDPAD.O.2

rule_Bondpad_Missing_V3errorBONDPAD.O.2

rule_Bondpad_Missing_V4 rule_Bondpad_Missing_V5 rule_Bondpad_Missing_V6errorBONDPAD.O.2

errorBONDPAD.O.2

errorBONDPAD.O.2

rule_Bondpad_Missing_V7 rule_Bondpad_Missing_V8errorBONDPAD.O.2

errorBONDPAD.O.2

bulk


revision 3.8


macro

Bondpad$layer1

2.0BONDPAD.E.1

Macro Table $layer1bondpad_metal1_filledbondpad_metal2_filledbondpad_metal3_filledbondpad_metal4_filledbondpad_metal5_filledbondpad_metal6_filledbondpad_metal7_filledbondpad_metal8_filledbondpad_metal9_filled

$layer2Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9

$layer1 $layer23.0

BONDPAD.SP.2

bondpad_sq bondpad_to_die_edge

bulkBondpad Bondpad

5.0errLength bondpad_sq < 52.0

BONDPAD.W.1

8.0BONDPAD.SP.1

rule_BONDPAD_L_1errorBONDPAD.L.1


revision 3.8

$layer1bulk

macro

Macro Table $layer1rule_BONDPAD_B_1_m1rule_BONDPAD_B_1_m2rule_BONDPAD_B_1_m3rule_BONDPAD_B_1_m4rule_BONDPAD_B_1_m5rule_BONDPAD_B_1_m6rule_BONDPAD_B_1_m7rule_BONDPAD_B_1_m8rule_BONDPAD_B_1_m9

$name1Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8Metal9

errorBONDPAD.B.1


$layer1segment >= 1.8


revision 3.8


$layer2$layer1

macro

Macro Table $layer1bondpad_metal1bondpad_metal2bondpad_metal3bondpad_metal4bondpad_metal5bondpad_metal6bondpad_metal7bondpad_metal8


$name1Metal1Metal2Metal3Metal4Metal5Metal6Metal7Metal8

$value10.050.050.050.050.050.050.090.09

$id1BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.3BONDPAD.E.3

$value1$id1

$layer1$layer2 $layer2

macro



$value10.220.220.220.220.220.220.540.54

$id1BONDPAD.SP.3BONDPAD.SP.3BONDPAD.SP.3BONDPAD.SP.3BONDPAD.SP.3BONDPAD.SP.3BONDPAD.SP.4BONDPAD.SP.4

$value1$id1

BONDPAD.W.2 and BONDPAD.W.3 - covered by VIAk.W.1.

macro




$value10.050.050.050.050.050.050.090.09

$id1BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.2BONDPAD.E.3BONDPAD.E.3

$layer2$layer1

$value1$id1


revision 3.8

$layer1bulk

errorBONDPAD.W.4

Macro Table $layer1rule_BONDPAD_W_4_metal1rule_BONDPAD_W_4_metal2rule_BONDPAD_W_4_metal3rule_BONDPAD_W_4_metal4rule_BONDPAD_W_4_metal5rule_BONDPAD_W_4_metal6rule_BONDPAD_W_4_metal7rule_BONDPAD_W_4_metal8


macro


$layer1bulk

errorBONDPAD.SP.5

Macro Table $layer1rule_BONDPAD_SP_5_metal1rule_BONDPAD_SP_5_metal2rule_BONDPAD_SP_5_metal3rule_BONDPAD_SP_5_metal4rule_BONDPAD_SP_5_metal5rule_BONDPAD_SP_5_metal6rule_BONDPAD_SP_5_metal7rule_BONDPAD_SP_5_metal8


macro

$layer1bulk

error$id1

Macro Table $layer1rule_BONDPAD_R_1_via1rule_BONDPAD_R_1_via2rule_BONDPAD_R_1_via3rule_BONDPAD_R_1_via4rule_BONDPAD_R_1_via5rule_BONDPAD_R_1_via6rule_BONDPAD_R_2_via7rule_BONDPAD_R_2_via8

$name1Via1Via2Via3Via4Via5Via6Via7Via8



$value16.016.016.016.016.016.04.04.0

$id1BONDPAD.R.1BONDPAD.R.1BONDPAD.R.1BONDPAD.R.1BONDPAD.R.1BONDPAD.R.1BONDPAD.R.2BONDPAD.R.2

macro


revision 3.8


$layer1bulk

errorBONDPAD.W.5

Macro Table $layer1rule_BONDPAD_W_5_metal1rule_BONDPAD_W_5_metal2rule_BONDPAD_W_5_metal3rule_BONDPAD_W_5_metal4rule_BONDPAD_W_5_metal5rule_BONDPAD_W_5_metal6rule_BONDPAD_W_5_metal7rule_BONDPAD_W_5_metal8


macro

$layer1Macro Table $layer1bondpad_metal1_slot_on_edgebondpad_metal2_slot_on_edgebondpad_metal3_slot_on_edgebondpad_metal4_slot_on_edgebondpad_metal5_slot_on_edgebondpad_metal6_slot_on_edgebondpad_metal7_slot_on_edgebondpad_metal8_slot_on_edge


macro

>=1.00


revision 3.8

CMOS Digital Electrical ParametersSheet Resistances

Contact/Via Resistances

global parameters$R_metal8_9$R_metal2_7$R_metal1$R_snpoly$R_sppoly$R_nsnpoly$R_nsppoly$R_snactive$R_spactive$R_nsnactive$R_nspactive$R_nwell$R_pwell

0.020.060.08101010040010101001504001600

Metal 8,9 sheet resistanceMetal 2,3,4,5,6,7 sheet resistanceMetal 1sheet resistanceSalicide N+ Poly sheet resistanceSalicide P+ Poly sheet resistanceNon-salicide N+ Poly sheet resistanceNon-salicide P+ Poly sheet resistanceSalicide N+ Oxide sheet resistanceSalicide P+ Oxide sheet resistanceNon-salicide N+ Oxide sheet resistanceNon-salicide P+ Oxide sheet resistanceNwell sheet resistancePwell sheet resistance

The units for sheet resistance are ohms/square

The units for sheet resistance are ohms/contact or ohms/viaglobal parameters$R_via7_8$R_via2_6$R_via1$R_metal1-contact$R_poly-contact$R_nplus-contact$R_pplus-contact

0.351.41.41101515

Via 7,8 resistanceVia 2,3,4,5,6 resistanceVia 1 resistanceMetal 1 to Contact resistancePoly to Contact resistanceN+ Oxide to Contact resistanceP+ Oxide to Contact resistance


revision 3.8

Current Densities

Contact/Via Current Densities

The units for current density are ma/umglobal parameters$L_metal8_9$L_metal1_7

82

Metal 8,9 current densityMetal 1,2,3,4,5,6,7 current density

The units for current density are ma/contact or ma/viaglobal parameters$I_via1_6$I_Via7_8$I_metal-contact-poly$I_metal-contact-oxide

0.10.80.10.1

Via 1,2,3,4,5,6 current densityVia 7,8 current densityMetal 1 Contact to Poly current densityMetal 1 Contact to Oxide current density


revision 3.8

Layer and Dielectric ThicknessThe units for layer and dielectric thickness are angstromsLayerPass2Pass1Metal 9IMD 8Metal 8IMD 7Metal 7IMD 6Metal 6IMD 5Metal 5IMD 4Metal 4IMD 3Metal 3IMD 2Metal 2IMD 1Metal 1ILDPolySTI (FOX)

Thickness (A)7000100001000060001000060003600300036003000360030003600300036003000360030003000300015003500

Description7.94.2CuK = 4.2CuK = 4.2CuK = 2.9CuK = 2.9CuK = 2.9CuK = 2.9CuK = 2.9CuK = 2.9Cusilicon dioxide K = 3.9

silicon dioxide K = 3.9


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1V PMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto

2.48nm1.20E+206.00E+2060nm20 ohm/sq6.00E+1925nm500 ohm/sq-140mV

for MOS Vt fine tuning

1V NMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto

2.33nm6.0E+193.00E+2060nm10 ohm/sq3.00E+1925nm250 ohm/sq170mV


LP 1V PMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto



100mv more Vto to reduce leakage by 10x

LP 1V NMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto



100mv more Vto to reduce leakage by 10x


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I/O 2.5V PMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto



I/O 2.5V NMOSToxChannel ConcentrationD/S Surface ConcentrationD/S XjD/S RshLDD Surface ConcentrationLDD XjLDD RshVto



Key Fast-Slow Model ParametersFast Vto %Slow Vto %Fast Tox %Slow Tox %Fast Mobility %Slow Mobility %Fast LDD Rsh %Slow LDD Rsh %

-1010-1010-3030-3030


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CDB layersOxideOxide_thkNwellPolyNhvtNimpPhvtPimpNzvtSiProtNburiedContMetal1Via1Metal2Via2Metal3Via3Metal4Via4Metal5Via5Metal6Via6Metal7Via7Metal8Via8Metal9

2461011121314151618203032343638404244464850525456586062

OxideOxide_thkNwellPolyNhvtNimpPhvtPimpNzvtSiProtNburiedContMetal1Via1Metal2Via2Metal3Via3Metal4Via4Metal5Via5Metal6Via6Metal7Via7Metal8Via8Metal9

CDB layersIND3dummyESDdummy

114115

IND3dumESDdum

DF2 Layer TablesCDB layersMetal1_slotMetal2_slotMetal3_slotMetal4_slotMetal5_slotMetal6_slotMetal7_slotMetal8_slotMetal9_slot

717273747576777879

M1slotM2slotM3slotM4slotM5slotM6slotM7slotM8slotM9slot

CDB layersPsubDIOdummyPNPdummyPWdummyNPNdummyIND2dummyINDdummyBJTdumCap3dumResdumBondpadCapdumCapMetalResWdumM1ResdumM2ResdumM3ResdumM4ResdumM5ResdumM6ResdumM7ResdumM8ResdumM9ResdumVPNP2dumVPNP5dumVPNP10dum

808284858688909293949596979899100101102103104105106107108109110

PsubDIOdumPNPdumPWdummyNPNdumIND2dumINDdumBJTdumCap3dumResdumBondpadCapdumCapMetalResWdumM1ResdumM2ResdumM3ResdumM4ResdumM5ResdumM6ResdumM7ResdumM8ResdumM9ResdumVPNP2dumVPNP5dumVPNP10dum

CDB layerstext 230 text


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DF2 Layer Purposes Tables

CDB purposesslotport1regiongridppathppath1macro

nwelldnwellipwellGeoShareportfill

12345678910111213

sltpt1reggrdpp0pp1mac

nwldnwipwgeopt0fil


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metal4_connVia3

metal3_connvia2_out_capInd

metal2_connVia1

metal1_conncont_poly

poly_conncont_ndiff

ndiff_connntap

nwell_connptap

psubstrate

metal5_conn

metal6_conn

Via4

Via5

CapMetalvia2_cap

ind_term2ind_term2_tap

ind_term1ind_term1_tap

cont_pdiffpdiff_conn

nb_tapNburied

metal7_connVia6

metal8_connVia7

metal9_connVia8

Bondpadbp_tap

ConnectivityConnectivity Definition

cont_collnpn_coll

cont_emitnpn_emit

cont_basenpn_base


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metal1_conn

ptie_dsptie_ds_v

ptie_tsptie_ts_v

ntie_nsntie_ns_v

ntie_dnsntie_dns_v

May 31, 2007 GPDK 90nm Mixed Signal Process Spec page A1

revision 3.8

$dt_Nimp dummy$layer1 dummy$layer2 dummy$layer3 dummyBJTdum input 15;0 df2order 103 packet zbip fillStyle outlineBondpad input 36;0 df2order 96 (Bondpad drawing) packet passCap3dum input 84;0 df2order 102 packet zcap fillStyle outlineCapMetal input 14;0 df2order 72 (CapMetal drawing) packet

mcapCapdum input 12;0 df2order 102 packet zcap fillStyle outlineCont input 6;0 df2order 24 (Cont drawing) packet cw viaDIOdummy input 22;0 df2order 107 (DIOdummy drawing) packet

zdiodeESDdummy input 74;0 df2order 110 (ESDdummy drawing) packet

esddumIND2dummy input 17;0 df2order 100 (IND2dummy drawing) packet

zind2IND3dummy input 70;0 df2order 101 (IND3dummy drawing) packet

zind3INDdummy input 16;0 df2order 99 (INDdummy drawing) packet

zindM1Resdum input 75;0 (M1Resdum drawing) df2order 104 packet

zrm1M2Resdum input 76;0 (M2Resdum drawing) df2order 104 packet








zrm9Metal1 Metal1_d_n or Metal1_p or Metal1_fMetal1_d input 7;0 df2order 30 (Metal1 drawing) packet m1

Attach Text: 7;3 (Metal1 label)Metal1_d_n if MergePinAndNet Metal1_d or Metal1_n else

Metal1_dMetal1_f input 7;5 df2order 81 (Metal1 fill) packet m1_fillMetal1_n input 7;4 df2order 30 (Metal1 net) packet m1Metal1_p input 7;1 df2order 30 (Metal1 pin) packet m1

Attach Text: 7;3 (Metal1 label)Metal1_slot input 7;2 df2order 81 (Metal1 slot) packet m1_slotMetal1_slot_not_BP Metal1_slot andnot (Bondpad size 3)Metal1_v Metal1_p and Metal1_d viaMetal2 Metal2_d_n or Metal2_p or Metal2_fMetal2_d input 9;0 df2order 34 (Metal2 drawing) packet m2

Attach Text: 9;3 (Metal2 label)


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Metal2_d_n if MergePinAndNet Metal2_d or Metal2_n elseMetal2_d

Metal2_f input 9;5 df2order 82 (Metal2 fill) packet m2_fillMetal2_n input 9;4 df2order 34 (Metal2 net) packet m2Metal2_p input 9;1 df2order 34 (Metal2 pin) packet m2













Attach Text: 35;3 (Metal6 label)Metal6_slot input 35;2 df2order 86 (Metal6 slot) packet m6_slot


revision 3.8

Metal6_slot_not_BP Metal6_slot andnot (Bondpad size 3)Metal6_v Metal6_p and Metal6_d viaMetal7 Metal7_d_n or Metal7_p or Metal7_fMetal7_d input 38;0 df2order 54 (Metal7 drawing) packet m7






Attach Text: 40;3 (Metal8 label)Metal8_slot input 40;2 df2order 88 (Metal8 slot) packet m8_slotMetal8_slot_not_BP Metal8_slot andnot (Bondpad size

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Gpdk090 DRM