GlueX Collaboration Meeting

February 20 - 22, 2014

12GeV Trigger Electronics

R. Chris Cuevas

Hardware Status ( A top down view,, )

Global Trigger Processing

Installation & Commissioning

Summary

2

Trigger Hardware Status • Trigger Supervisor ( TS ) - Complete

Boards have been thoroughly tested and delivered Revisions to firmware are minor iterations are a result of testing

improvements Production boards are being used in Global Test Stand for a variety of

verification testing of firmware and CODA libraries. Functional hardware verification with Trigger Distribution(TD) boards

complete. TS firmware supported with CODA3 libraries

• Trigger Supervisor Input/Output (TSIO) – Complete Rear transition board tested with Densishield cable from GTP

William Gu

• TI – TD Trigger Interface – Trigger Distribution - Complete

All production modules have been delivered and pass acceptance 10 TI boards have been modified to be used as TI-”Master” units

- (2) TI “Master” boards have been configured for the FCAL.

Six crates to each “Master” and additional transceiver will

be added to connect to Global Trigger input(Fiber)

- (2) TI “Master boards have been installed for BCAL also The TI Master boards have been modified and tested thoroughly. TD firmware and TI firmware versions are stable and supported with

CODA3 libraries

*New* feature added to TI-TD fiber optic link. ROC ID information is transferred so the fiber link source and destination is available for verification.

3

Trigger Hardware Status William GuB. Moffit

GLOBAL TRIGGER PROCESSOR

4 ChannelQSFP Fiber

RJ45Ethernet

Jack

4x 8-ChannelLVPECL

Trigger Outputs to TSHigh Speed Densi-Shield® Cable assemblies

Altera FPGAStratix IV GX

DDR2 Memory256 MB

Gigabit Links to SSPVXS “Switch” card

S. KanetaB. RaydoC. Hewitt

4

JTAG

• 2 Production Boards delivered• Passed acceptance testing• Production design includes:- QSFP fiber port- Front panel I/O- Front panel RJ45 Ethernet- 1Gb Ethernet

• Significant testing with full VXS crate. All GigabitLinks work as expected.

Linux OS on the GLOBAL TRIGGER PROCESSOR

5

B. RaydoC. Hewitt

• Global Trigger Processor ( GTP ) - Complete

Boards have been thoroughly tested and delivered Significant firmware activities include effort for new embedded Linux OS Production boards are being used in Global Test Stand for a variety of

verification testing of firmware and CODA libraries. Functional hardware verification with SubSystem Processors in VXS

crate. All boards included for full Hall D Global Trigger test in the lab. The GTP transceivers (Altera) have been tested with the SSP at 5Gb/s GTP firmware released for development of CODA3 libraries GTP manual updated.

Linux Kernel is a stable release (3.12) Significant support for Altera FPGA Linux runs on the Altera NIOS II processor

Linux OS on the GLOBAL TRIGGER PROCESSOR

6

B. RaydoC. Hewitt

1Gb Ethernet

Hall D Global Trigger Logic

SSPs GTPto TS

B. Raydo

7

SSPs GTPto TS

B. Raydo

8

SSPs GTPto TS

B. Raydo

9

SSPs GTPto TS

B. Raydo

Sub-Detectors

10

SSPs GTPto TS

B. Raydo

• Very good example of production hardware tested with full crate• All VXS Gigabit input streams tested• Fully verified with existing TI and SD Clock, Sync and Trigger signals

11

Sub-System Processor Ben Raydo

8

12

XilinxVirtex V‘TX150T

VXS‘P0’

VME64x‘P2’

VME64x‘P1’

8 QSFP Fiber TransceiversFrom 8 Front End Crate CTP

• SubSystem Processor ( SSP ) - Complete All production boards have been delivered. Production contract included:

- 10 Hall D- 15 Hall B- 1 each for Halls A & C

Firmware version 1.0 and CODA3 library complete, but needs testing

13

Trigger Hardware Status Ben Raydo

Crate Trigger Processor VXS ConnectorsCollect serial data from 16 FADC-250(64Gbps)

Hai DongJeff Wilson

2013 Production CTP

New Front Panel I/O

14

• Crate Trigger Processor ( CTP ) - Complete Production quantities (30) for Hall D

• All production boards pass (FCAT)Full Crate Acceptance Testing- CTP boards delivered to Hall D group

Hall D L1 full crate energy sum is stable and is part of FCAT

FCAT verifies that trigger data is aligned properly from all 16 FADC250 boards

All Gigabit serial lanes operated in sync @2.5Gbps Clock counters, trigger counters on all boards

verified to be in agreement

• Firmware for BCAL L1 pedestal subtraction definedand in development• CTP SSP fiber link ID firmware feature needs final

test and library in progress• Firmware versions for TOF, Tagger, and PS havebeen prioritized

MTP Parallel Optics

8 Gbps to SSP

• Signal Distribution ( SD ) - Complete All production modules have been delivered and installed!

15

Trigger Hardware Status Nick Nganga

Flash ADC 250Msps ( FADC250 )- See Fernando’s update also Production board delivery to JLAB groups is complete

Production board repairs are progressing slowly (12 Hall D boards remain in repair status)

“Mode 6” (TDC algorithm) has been corrected from initial release. New firmware for this mode has been tested thoroughly.- Readout data includes pulse integral value and time

stamp value is high resolution (LSB=62.5ps; 6-bits)- This mode will be used for production Physics operations

and will be required for maximum trigger rate See Bryan Moffit’s DAQ site that contains the latest Jlab Module

Manuals with notes for relevant firmware versionhttps://coda.jlab.org/wiki/index.php/JLab_Module_Manuals

- Firmware change request method (proposed)1. Submit request to Hall D DAQ person2. Hall D DAQ person sends to FE and DAQ group leaders3. FE/DAQ groups will prioritize and organize relevant discussion

meetings as required. 16

Trigger Hardware Status F. BarbosaH. DongE. JastrzembskiJeff Wilson

Global Crate Testing - Update• Significant activities have been completed

and are too numerous to list here• Global Trigger crate has been tested• TSTD crate has been tested• Firmware and CODA library development

include an impressive amount of work!• Global Trigger monitoring (GUI) plus remote

configuration (firmware download) have been implemented and tested.

• Global Trigger crate and TSTD crate have been moved to the Hall. 17-Feb

• Details:- TD and TS need to be installed in crate- SBCs need to be installed in crates- SBCs Network connection needed- Crate (fan tray) network interface

needed- Connect Densi-Shield cables from GTP

to TS

17

Scott KanetaBen RaydoWilliam GuB. Moffit

2.954usMeasured full ‘round trip’ trigger latency

Trigger Fiber Optics

• Trigger System Fiber Optics (Q1 – FY14 procurement) System diagrams have updated for Hall D Thanks to Hall D group for installation help!

18

A. StepanyanM. Taylor

What’s next?

• Activity 2543115 – Performance Testing

• Establish trigger distribution connections (Fiber) to all crates

o Main FO trunk lines and patch panels installed

o Install TD and TS boards in TD crate

o Set required delays for each TI fiber length and measure trigger signal alignment between crates in each subsytem

• Global Crate

o Establish CTP SSP fiber link connections

o Run deterministic test patterns to measure and verify L1 trigger alignment and scaler counts.

o Measure and verify other Global Trigger system functions

• Prepare for cosmic ray trigger testing

- FCAL only

- BCAL with FDC (and CDC?)

- Many other commissioning tests omitted here,

19

Summary

• Global Trigger and Trigger Distribution crates are installed

• Almost all FO trunk lines are installed and tested

- Final patch cables need to be connected

• Firmware released for all boards, including new updates for FADC250 “TDC” feature

• Firmware development for BCAL cosmic ray trigger has started and other firmware developments have been prioritized. (See example below)

Tagger “Hit Count” algorithm, TOF, and Pair Spectrometer applications

• All production CTP have been fully qualified with FCAT

• Acceptance testing activities are complete for delivered production boards.

• Essential CODA library development and library release is complete for almost every board. A few boards will have their library released after final testing.

• Check out 12GeV Trigger hardware progress: https://halldweb1.jlab.org/wiki/index.php/Electronics_Trigger_Meetings

Questions?

20

All sorts of cool stuff

Backup Slides

All Trigger Modules Delivered!

2

Front End Crate• FADC250, (FADC125), (F1TDC)• Crate Trigger Processor• Signal Distribution• Trigger Interface

Trigger Control/Synchronization• Trigger Supervisor• Trigger Distribution

FADC250 CTP

SD TI

SSP GTP

TSTD

L1 Trigger ‘Data’MTP Ribbon Fiber

Trigger ‘Link” ControlClock, SyncMTP Ribbon Fiber

Global Trigger Crate• Sub-System Processor• Global Trigger Processor

SSP

TI-1 Trigger Interface modulecan be configured to controlup to 9 front end crates

This method allows for local control of a detectorSub-system.

TI needs to be configuredfor this mode with multiple FO Transceivers

Local control of CLOCK,SYNC, and Trigger signals

Global Trigger system signals NOT available

Perfect for initial testing ofDetector sub-systems. (FCAL, BCAL)

Fiber

TI operating in TS modeWilliam Gu

5

User Input/OutputFront Panel (dECL)

TI-2

TI-3

TI-4

TI-5

TI-6

TI-7

TI-8

TI-9

Full DAq Crate Testing Plans

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• Before deploying full crates with all required modules:• Will test using “Playback” mode and CODA• No input cables necessary; User defined signals loaded in front-end FPGA• Deterministic test for all channels and Gigabit serial lane alignment check• Verify TI SD Payload Board Synchronization and Clock• Re-Use these tools for Hall commissioning effort

• Test station used for FINAL firmware verification and software ‘library’ development• Bryan Moffit has created a preliminary plan and list of test functions • See wiki link https://halldweb1.jlab.org/wiki/index.php/Full_Crate_Acceptance

This full crate test station in EEL109 is an essential infrastructure element needed to test and verify the front end and trigger hardware/software before installation in the Halls.

Bryan MoffitEt al.

System Description

Crate Trigger Processing

Flash ADC Modules

Detector Signals

Sub-System Processing(Multi-Crate)

Global Trigger Processing

TriggerSupervisor

(Distribution)

TS -> TD -> TILink

1.25Gb/sBi-Directional

BUSYTrigger SyncTrig_Comnd

CTP -> SSP -> GTPL1 Trig_Data

Uni_Directional

Energy Sums

6

Noise in the FADC (No Readout during data taking)

03/21/2012 CniPol Meeting 26

Sing

le E

vent

All

Eve

nts

Noise in the FADC (Readout during data taking)

03/21/2012 CniPol Meeting 27

Sing

le E

vent

All

Eve

nts

Two DAQ Crate Testing: FY11

200KHz Trigger Rate!

• Pre-Production and 1st articleboards have been received and tested• Significant effort for circuit boardfabrication, assembly and acceptancetesting• System testing includes:

• Gigabit serial data alignment 4Gb/s from each slot 64Gb/s to switch slot Crate sum to Global crate @8Gb/s

• Low jitter clock, synchronization ~1.5ps clock jitter at crate level 4ns Synchronization

• Trigger rate testing• Readout Data rate testing• Bit-Error-Rate testing

-Need long term test (24 - 48 hrs)

• Overall Trigger Signal Latency ~2.3us (Without GTP and TS)

Readout Controller Capable of 110MB/s- Testing shows we are well within limits