Girish_Viswanath_Bellary_Resume_July_2015

RESUMENAME : GIRISH VISWANATH BELLARY.EMAIL : [email protected] .MOBILE : ( + 91 ) - 95350 12972.

EDUCATION SUMMARY

DEGREE : BACHELOR OF ENGINEERING.BRANCH : ELECTRONICS AND COMMUNICATION.COLLEGE : NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA , SURATHKAL. UNIVERSITY : MANGALORE UNIVERSITY,

MANGALORE, KARNATAKA.MONTH and YEAR of PASSING : JULY - 1998.CLASS : FIRST CLASS with DISTINCTION.AGGREGATE : 76 %.

WORK EXPERIENCE SUMMARY

Domain : Hardware - VLSI Design - Back End.Specialization : Physical Design , STA and IO STA.Work Experience : 14 Years and 11 Months.Technology Nodes : 360 nm, 260 nm, 180 nm, 130 nm, 90 nm, 65 nm,

45 nm and 28 nm.

mailto:[email protected]

I have been working extensively on VLSI Physical Design ( Back End ) Technologies since August 1998.

I have previously worked with Global Multinational companies like :

IBM , Bengaluru ( 09 Years and 05 Months) , Wipro Technologies , Kochi , Kerala ( 11 Months ) , MindTree Limited , Bengaluru ( 01 Year ) , Cyient, Bengaluru ( 03 Years and 01 Month ) andSynapse Designs , Bengaluru ( 06 Months ).

I joined IBM Bengaluru as a Physical Design Engineer on 03 - August - 1998. I have worked with IBM Bengaluru for a period of 09 Years and 05 Months.

I have also worked at IBM onsite locations like IBM , Essex Junction , Burlington , Vermont , USA ( 04 Months ) and IBM , Hopewell Junction East Fishkill , New York , USA ( 01 Year ).

I have successfully delivered as many as Five ASICs at IBM. These IBM ASICs are working across Technology nodes such as 360 nm, 260 nm and 180 nm. These IBM ASICs are used in Networking and Video applications at various IBM customer locations worldwide. I have successfully delivered as many as Seventy IPs / Cores / Subchips at IBM. These IBM cores are working across various Technology nodes such as 180nm , 130nm , 90nm and 65nm. Most of these IBM cores are classified as High Speed Serialiser / De-serialiser cores ( HSS Cores ). The communication protocols used by these HSS cores are SCSI , SATA and PCIEXPRESS . The latest IBM HSS core that has been delivered in 65nm node and has been working since the year 2007. I have led a Physical Design Team of 07 people at IBM between 2004 and 2007.

I left IBM Bengaluru as an R & D Engineer on 31 - December - 2007.

I joined Wipro Technologies, Kochi, Kerala as a Senior Project Leader on 01 - September - 2008. I have worked with Wipro Technologies , Kochi , Kerala for a period of 11 Months.

I have successfully delivered Four IPs / Cores / Sub chips at Wipro Technologies , Kochi , Kerala. All of these Wipro sub chips are working in the Technology node 45 nm and are classified as Double Data Rate cores ( DDR2.0 ). I have led a Physical Design Team of 03 People during the Physical Design and development of DDR 2.0 Cores at Wipro Technologies , Kochi , Kerala.

I left Wipro Technologies , Kochi as a Senior Project Leader on 23 - July - 2009.

I joined MindTree Limited , Bengaluru as a Technical Manager on 21 - October - 2010. I have worked with MindTree Limited , Bengaluru for a period of 01 Year.

I have achieved IO STA closure for the Phoenix interfaces such as UHPI, McBSP and McSPI. Each Phoenix interface was Timing closed in all Modes / Timing Corners / Core Voltages of operation. The Two Core voltages supported are 1.3V and 1.05V. The Four IO voltages supported are 1.8V, 2.5V, 2.75V and 3.3V. For UHPI and McBSP interfaces the modes of operation are EXT_CLK and INT_CLK. For McSPI interface the modes of operation are MASTER and SLAVE modes.

I left MindTree Limited, Bengaluru as a Technical Manager on 01 - October - 2011.

I joined Cyient , Bengaluru as a Tech Lead on 03 - October - 2011. I have worked with Cyient, Bengaluru for a period of 03 Years and 01 Month. Cyient was formerly known as Infotech Enterprises Limited until July 2014.

I have worked on Hawk2 : Two RLMs : 45 nm physical design project which involved the complete Physical Design flow for Two RLMs at Cyient , Bengaluru. I have worked on Cobra : 1 Chip : 45 nm physical design project at Cyient , Bengaluru. I have worked on Three XF2 RLMs : 45 nm at Cyient , Bengaluru . The XF2 project involved complete Physical Design flow execution for Three XF2 RLMs. I have worked on Four AQ RLMs : 32 nm at Cyient, Bengaluru. The AQ project involved complete Physical Design flow execution for Four AQ RLMs. Aludra : 1 RLM : 45 nm , DopplerCS : 1 RLM : 32 nm , Cylon1.1 : 3 RLMs : 45 nm and SD5860Lite : 3 RLMs : 32 nm node.

I left Cyient, Bengaluru as a Tech Lead on 17 - October - 2014.

I joined Synapse Techno Design Innovations Pvt Ltd as a Senior Technical Manager on 20 - October - 2014.

I worked on PP_P05_PAR_WRAP : RLM : 28nm at Synapse, Bengaluru.

I left Synapse Techno Design Innovations Pvt Ltd as a Senior Technical Manager on 30-Apr-2015.

EMPLOYMENT SUMMARY

V EMPLOYER NAME : SYNAPSE TECHNO DESIGN INNOVATIONS PRIVATE LIMITED.

POSITION HELD at SYNAPSE : SENIOR TECHNICAL MANAGER. EMPLOYEE NUMBER at SYNAPSE : IN0437. JOINING DATE at SYNAPSE : 20 - OCTOBER - 2014. LEAVING DATE at SYNAPSE : 30 - APRIL - 2015. Number Of Months at SYNAPSE : 06 Months. SYNAPSE ADDRESS : SYNAPSE TECHNO DESIGN

INNOVATIONS PRIVATE LIMITED, VIII Floor, TOWER C , GATE #2,

PRESTIGE SHANTHINIKETAN COMMERCIAL COMPLEX,

NEAR I.T.P.L. MAIN ROAD, WHITEFIELD, BENGALURU - 560 066.

SYNAPSE PHONE : ( + 91 ) - 080 - 6753 9100. SYNAPSE WEBSITE : www.synapse-da.com

IV EMPLOYER NAME : CYIENT.POSITION HELD at CYIENT : TECH LEAD.DIVISION NAME at CYIENT : SEMICONDUCTOR DESIGN & ANALYSIS.EMPLOYEE NUMBER at CYIENT : 20414.JOINING DATE at CYIENT : 03 - OCTOBER - 2011.LEAVING DATE at CYIENT : 17 - OCTOBER - 2014.Number Of Years at CYIENT : 03 Years and 01 Month.

CYIENT ADDRESS : CYIENT IT PARK , # 110/A & 110/B ,

PHASE I , ELECTRONICS CITY , OFF HOSUR MAIN ROAD , BENGALURU - 560 100.

CYIENT PHONE : ( + 91 ) - 080 - 2518 6000.CYIENT WEBSITE : www.cyient.com

III EMPLOYER NAME : MINDTREE LIMITED.POSITION HELD at MINDTREE : TECHNICAL MANAGER.DIVISION NAME at MINDTREE : RESEARCH & DESIGN SERVICES.EMPLOYEE NUMBER at MINDTREE : M1013999.JOINING DATE at MINDTREE : 21 - OCTOBER - 2010.LEAVING DATE at MINDTREE : 01 - OCTOBER - 2011.Number Of Months at MINDTREE : 01 Year.MINDTREE ADDRESS : GLOBAL VILLAGE ,

MYLASANDRA , OFF MYSORE ROAD , BANGALORE - 560 059.

MINDTREE PHONE : ( + 91 ) - 080 - 6706 4000.MINDTREE WEBSITE : www.mindtree.com

II EMPLOYER NAME : WIPRO TECHNOLOGIES.

http://www.mindtree.com/

http://www.cyient.com/

http://www.synapse-da.com/

POSITION HELD at WIPRO : SENIOR PROJECT LEADER. DIVISION NAME at WIPRO : PRODUCT ENGINEERING SERVICES.EMPLOYEE NUMBER at WIPRO : 168364.JOINING DATE at WIPRO : 01 - SEPT - 2008. LEAVING DATE at WIPRO : 23 - JULY - 2009.Number Of Months at WIPRO : 11 Months.WIPRO ADDRESS : WIPRO TECHNOLOGIES, INFOPARK , SPECIAL ECONOMIC ZONE,

KAKKANAD, KOCHI - 682 030, KERALA.

WIPRO PHONE : ( + 91 ) - 0484 - 399 1021.WIPRO WEBSITE : www.wipro.com

I EMPLOYER NAME : IBM INDIA PRIVATE LIMITED.POSITION HELD at IBM : R & D ENGINEER.

DIVISION NAME at IBM : HARDWARE DESIGN SERVICES.EMPLOYEE NUMBER at IBM : 910104.JOINING DATE at IBM : 03 - AUGUST - 1998.LEAVING DATE at IBM : 31 - DECEMBER - 2007.Number Of Years at IBM : 09 Years and 05 Months.IBM ADDRESS : IBM INDIA PRIVATE LIMITED,

EMBASSY GOLF LINKS ( EGL ), BLOCK D, OFF KORAMANGALA INDIRANAGAR INTERMEDIATE RING ROAD, BENGALURU - 560 071, KARNATAKA.

IBM PHONE : ( + 91 ) - 080 - 4177 7239.IBM WEBSITE : www.ibm.com

EXPERIENCE DETAILS

http://www.ibm.com/

http://www.wipro.com/

Functional Domain Name Experience Description

VLSI Design.Physical Design ( Back End ).

14 Years and 11 months.

Engineering discipline that deals with Lay Out of ASICs and IPs.

TECHNICAL SKILLS

Primary Skills

ASIC Physical Design , IP Physical Design , IO STA, Customer management and Design knowledge.

Secondary Skills

Architecture , VHDL , Verilog , HSS , DDR2.0, Fiber Channel , Infiniband , SATA , SCSI and Project Management.

Mature Skills

Interviewing , Hiring and Mentoring Physical Design Engineers.

PROJECT EXPERIENCE

Project 1 PP_P05_PAR_WRAP 28 nm Nov 2014 to Apr 2015.

Project Site : Synapse, Bengaluru.Physical Design Flow : Cadence Encounter, Synopsys PrimeTime and Calibre.Product Type : RLM.RLM Name : PP_P05_PAR_WRAP.RLM Size : 0.80 mm x 1.70 mm.RLM Gate Count : 443.6 K cells.RLM Cell Utilization : 70 %.Process : TSMC 28 nm.

Project 2 UT0105A 28 nm July 2014 to Oct 2014.

Project Site : Cyient, Bengaluru.Physical Design Flow : Cadence Encounter , Synopsys PrimeTime and Calibre.Product Type : RLM.RLM Name : TRXM.RLM Size : 1.70 mm x 1.00 mm.RLM Gate Count : 250 K cells.RLM Cell Utilization : 57 %.Process : TSMC 28 nm.

Project 3 NOVAFORA 28 nm May 2014 to June 2014.

Project Site : Cyient, Bengaluru.Physical Design Flow : Cadence Encounter, Synopsys PrimeTime and Calibre.Product Type : RLM.RLM Name : NOVAFORA.Novafora RLM Size : 1.15 mm x 1.78 mm.Novafora RLM Gate Count : 169 K.Novafora RLM Cell Utilization : 60.29.Process : TSMC 28 nm.

Project 4 SD5860_LITE 28 nm December 2012 - April 2014.

Project Site : Cyient, Bengaluru.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Product Type : RLMs.Process : TSMC 28 nm.Chip Name : SD5860_LITE.Chip Package Type : C4 Area Array.

RLM Names : esi, psf and psgf.Project Objective : Physical Design for Three RLMs.

ESI RLM Size : 0.80 mm x 1.70 mm.ESI RLM Gate Count : 443.6 K cells.ESI RLM Cell Utilization : 63.76 %.

PSF RLM Size : 1.75 mm x 1.15 mm.PSF RLM Gate Count : 685.4 K cells.PSF RLM Cell Utilization : 71 %.

PSGF RLM Size : 1.70 mm x 1.06 mm.PSGF RLM Gate Count : 260.3 K cells.PSGF RLM Cell Utilization : 58.4 %.

Number of On Chip Hard Macros : 18.Types of Hard Macros : esi , psf , psgf , cpi_logic , sm , sml ,

sma , gcs , gcs_0 , gcs_1 , il , msupb , pcie_wrp, tile, tile_qcm, oe, psgp and psp.

Project 5 CYLON 1.1 45 nm August 2012 - June 2013.

Project Site : Cyient, Bengaluru.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Product Type : RLMs.Chip Name : CYLON1.1.RLM Names : XgSixTopWrapper and CylonMacTriQuad.Project Objective : Physical Design for Three RLMs.

CMTQ RLM Size : 1.37 mm x 1.40 mm.CMTQ RLM Gate Count : 393 K.CMTQ RLM Cell Utilization : 78.12.

XG6T RLM Size : 1.15 mm x 1.78 mm.XG6T RLM Gate Count : 169 K.XG6T RLM Cell Utilization : 60.29.

NCI0 RLM Size : 4.57 mm x 2.25 mm.NCI0 RLM Gate Count : 1,844 K.NCI0 RLM Cell Utilization : 82.13.

Number of On Chip Hard Macros : 23.

Types of Hard Macros : XgSixTopWrapper - 1, CylonMacTriQuad - 1 , Arsenic - 1 , Helium - 5 , Neon - 7, Radon - 4 , EFUSE - 3 , Dcal128Mux64_9t - 1.

Project 6 DOPPLERCS 28 nm June 2012 - July 2012.

Project Site : Cyient, Bengaluru.Product Type : RLMs.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Chip Name : DOPPLERCS.RLM Name : SC8.Project Objective : Physical Design.

SC8 block RLM Size : 1.69 mm x 1.78 mm. SC8 block RLM Gate Count : 448 K Cells. SC8 block RLM Net Count : 487 K Nets. Number of Hard Macros : 65. Types of Hard Macros : RF1* ( 44 ), SRAM1D* ( 14 ) , RA2U* ( 2 ) ,

RF2* ( 3 ), DRAM* ( 1 ) , BIST ( 1 ).Number of Soft Macros : 196.Types of Soft Macros : FARR* (61), FBIO* (61), SBIO* (61),

BIST* (13).

Project 7 ALUDRA 45 nm May 2012 - June 2012.

Project Site : Cyient, Bengaluru.Product Type : RLM.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Chip Name : ALUDRA.RLM Name : al_cl1_cl2_ac.Project Objective : RLM development ( One ).

al_cl1_cl2_ac block RLM Size : 1.72 mm x 1.72 mm.al_cl1_cl2_ac block RLM Gate Count : 352 K Cells.al_cl1_cl2_ac block RLM Net Count : 365 K Nets.al_cl1_cl2_ac block RLM IO pin count : 4605.Number of Macros : 60.Type of Macros : SRAM1D* ( 10 ), RA2S* ( 50 ).

Project 8 AQ 28 nm April 2012 - May 2012.

Project Site : Cyient , Bengaluru , India.Product Type : RLMs.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Chip Name : AQ.RLM Names : hash_JDcfg_JVaq , gumem_JDcfg_JVaq,

rord_JDcfg_JVaq and disp_JDcfg_JVaq.Project Objective : Physical Design for Four RLMs.

hash_JDcfg_JVaq block RLM Size : 1.275 mm x 1.275 mm.hash_JDcfg_JVaq block RLM Gate Count : 538 K Cells.hash_JDcfg_JVaq block RLM Net Count : 550 K Nets.Number of Macros : 32.Number of SCBs : 15.Type of Macros : SRAMs ( 05 ) , RAs/RFs ( 27 ).

gumem_JDcfg_JVaq block RLM Size : 1.040 mm x 2.048 mm.

gumem_JDcfg_JVaq block RLM Gate Count : 475 K Cells.gumem_JDcfg_JVaq block RLM Net Count : 480 K Nets.Number of Macros : 18.Number of SCBs : 14.Type of Macros : SRAMs ( 16 ) , RAs/RFs ( 02 ).

rord_JDcfg_JVaq block RLM Size : 1.563 mm x 1.670 mm.rord_JDcfg_JVaq block RLM Gate Count : 518 K Cells.rord_JDcfg_JVaq block RLM Net Count : 528 K Nets.Number of Macros : 51.Number of SCBs : 12.Type of Macros : SRAMs ( 10 ) , RAs/RFs ( 41 ).

disp_JDcfg_JVaq block RLM Size : 1.276 mm x 1.277 mm.disp_JDcfg_JVaq block RLM Gate Count : 562 K Cells.disp_JDcfg_JVaq block RLM Net Count : 572 K Nets.Number of Macros : 34.Number of SCBs : 14.Type of Macros : RAs / RFs ( 34 ).

Project 9 XF2 45 nm Jan 2012 - Mar 2012.

Project Site : Cyient , Bengaluru.Product Type : RLMs.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.Chip Name : XF2.

RLM Names : xf_io_JDspd_12G, fdata_xbar_ca and fdata_xbar_bank_thread_JDbank_JV.

Project Objective : RLM development ( Three ).

xf_io_JDspd_12G block RLM Size : 1.786 mm x 1.930 mm.xf_io_JDspd_12G block RLM Gate Count : 420 K Cells.xf_io_JDspd_12G block RLM Net Count : 430 K Nets.Number of Macros : 22.Type of Macros : SRAMs ( 1 ) , RAs/RFs ( 21 ).

fdata_xbar_ca RLM Size : 0.950 mm x 1.008 mm.fdata_xbar_ca Gate Count : 200 K Cells.fdata_xbar_ca Net Count : 210 K Nets.Number of Macros : 0.

fdata_xbar_bank_thread_JDbank_JV RLM size : 5.567 mm x 2.308 mm.fdata_xbar_bank_thread_JDbank_JV Gate Count : 435 K Cells.fdata_xbar_bank_thread_JDbank_JV Net Count : 445 K Nets.Number of Macros : 152. Type of Macros : RAs/RFs ( 152 ).

Operating Conditions :

Tmax = 115 ; Tmin = 0 ; Tnom = 85; Vmax = 1.10V ; Vmin = 0.95V, Vnom = 1.0V.

Customer / Client Deliverables :

Three RLM blocks namely , xf_io_JDspd_JV_12G, fdata_xbar_bank_thread_JDbank_JV and fdata_xbar_ca.

Project 10 COBRA 45 nm Nov 11 - Jan 2012.

Project Site : Cyient, Bengaluru.Product Type : RLM.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.RLM Name : COBRA.Gate Count : 312 K cells.

Customer / Client Deliverables : Cobra RLM.

Tools & Technologies : Synopsys ICC, Synopsys PrimeTime and Calibre.

Operating Systems : Windows 7 and Linux.

Role Played : Tech Lead.

Project 11 HAWK2 45 nm Oct 11 - Jan 2012.

Project Site : Cyient, Bengaluru.Product Type : RLMs.Physical Design Flow : Synopsys ICC, Synopsys PrimeTime and Calibre.RLM Names : FMC_Wrapper and HIB_Wrapper.Project Objective : RLM Development ( Two ).FMC RLM Area : 9.60 mm x 1.15 mm.HIB RLM Area : 7.60 mm x 8.61 mm.Functional Clock Frequency ( Highest ) : 900.9 Mhz.

HAWK2 has a total of 30 IPs including the following :

DDR3IPHY ( DDR3.0 Integrated PHY ), DDR3IPHY2P1 ( DDR2.1G PHY Hard Core ), HS06GP( HSS 3G-6G C4 ), HS15GB( HSS 15G-BP ), PLL ( Base Library ), PLLIF( PLL-LC Tank-IF), TVSENSE ( Temperature and Voltage Sensor ), EDRAMD ( Embedded DRAM ), EDRAMT ( Embedded DRAM - 2 Port ), RA ( Register Array ),RF1 ( 1 Port Register File ), RF2 ( 2 Port Register File ), SRAM1D ( 1 Port SRAM ), SRAM2S ( Dual Port SRAM ), SRAM2T ( Compilable 2 Port SRAM ), BMM, DMC0, DMC1,EFQ, EMC, FMC, HIB, IRX, ITX, IVQ, SCB, TEC, EFUSEPRIT12, EFUSESECT12, EFUSETERT12.

The Operating Voltages are Vmax = 1.03V; Vmin=0.97V; Vnom = 1.0V.The Operating Temperatures are Tmax = 115 C, Tmin = 0 C, Tnom = 110 C.The IR Drop Max = 0.008 V; IR Drop Min = 0.007 V.The Power on Hours ( EM / Reliability ) = 87600 Hours.The EM Frequency = 50 Hz.

Customer / Client Deliverables : Complete Physical Design flow on RLMs like

FMC and HIB.

Tools & Technologies : Cadence Encounter.

Operating Systems : Windows 7 and Linux.

Role Played : Tech Lead.

Project 12 PHOENIX 90nm Oct 10 - Oct 2011.

Project Site : MindTree Limited , Bengaluru.Product Type : RLMs.Design Tools used : Synopys PrimeTime.Project Objective : PRP and IO STA constraint definition

and Timing closure.Die Size : 3.97 mm x 4.47 mm.Gate Count : 05 Million.Functional Clock Frequency ( Highest ) : 155 MHz.Power Dissipation : 400mW.

Phoenix has a Total of 55 Peripherals / Cores / Macros / IPs including :

McBSP, McSPI, UHPI, EMIF, MMCSD, VBUSP,DMA ,USB, USB 2.0 PHY, PLL, I2C, UART, 10-bit SAR, SPI, McBSP , I2S, RTC / Timer, Emulation Trace, ATPG Transition Fault Clock Leaker and eFuse FuseFarm.

The combinations which have high priority (ie: Timing closure goals) are:

1.05V core & 3.3V IO (EMIF and all others). 1.3V core & 3.3V IO (EMIF and all others). 1.05V core & 1.8V IO (EMIF only). 1.3V core & 1.8V IO (EMIF only).

Customer / Client Deliverables : PRP and IO STA constraint definition and closure.Customer Applications : Cellphone and other Audio applications.

Parametric Reference Profile ( PRP ) closure for the Phoenix 90nm chip. PRP data includes Part Release Data, Peripherals/IPs data, STA Reports,Data Manuals, PE Parameter Values, Customer Parameter Values, Design Margins,Design TDL, Product Test Data, Operating Modes , Operating Conditions,IC Voltages, Load/Capacitance ( min & max ) , Slew ( min & max ), Temperature ( min & max ), Design Parameters, Design Specs, Register List, I/O Timing Diagrams, Delivery Owners List, IC Tester Data.

Defining and closure of the IOSTA Constraints for the Phoenix peripherals namely McBSP, McSPI and UHPI.

Role Played : Technical Manager.Operating Systems : Windows7 and Linux.Team Size : 03.

Project 13 DDR 2.0 Macros 45 nm Sept 08 - July 09.

Project Site : Wipro Technologies, Kochi, Kerala.Description : Physical design and development for DDR Macros.

DDR 2.0 Macros such as Command NS and Data NS and EW at 45 nm. The Functional clock in DDR Mode runs at 400 Mhz. The same Functional clock in SDR Mode runs at 200 Mhz.

Tools & Technologies : Magma and Synopsys PrimeTime.Place and Route - Magma , Static Timing Analysis - Synopsys PrimeTime,Noise Analysis - Cadence Celtic,

Signal E.M - Magma,Power Analysis - Prime Power and Magma BlastRail,IR Drop Analysis - Apache Redhawk,

Formal Verification - Verplex, DRC and LVS Checks - Magma GVSV scripts.

Operating System : Windows XP and Texas Instruments - Linux.

Role Played : Senior Project Leader .

Responsibilities / Contribution : I have performed various Physical Design tasks including Floorplanning, Tap Cell Placement ( N-Well Fillers ), Magma C.T.S.,Magma Fix Cell ( P.D.S.) , Clock Optimisation, Clock Tree Wiring, Magma Fix Wire ( Detail Routing ), Static Timing Analysis (S.T.A.), Noise Analysis, Signal E.M. Analysis, IR Drop Analysis, Power Analysis,Lay Out Checks, Running DRC and LVS Checks, DOTLIB Generation and Sub Chip Archival including custom master libraries.

Team Size : 3.

Project 14 HSS Wrong Way Wiring Support 65nm Oct 07 - Dec 07.

Project Site : IBM India Private Limited, Bengaluru.

Description : Preparing the HSS Cores in 65 nm for Manufacturing Aware Router to perform wiring in the wrong direction ( ie., routing in Horizontal direction for a Metal layer which usually is expected to be Vertical routing ).

Tools & Technologies : IBM EDA Tools - GUIDE, ChipBench, Chip Edit and Bonn Router.

Operating System : IBM AIX and Windows XP.

Role Played : Project Leader .

Responsibilities / Contribution : Prepared and executed a plan for building real Physical Testcases to verify the Manufacturing Aware Routing ( MAR ) wrong way routing on IBM HSS Cores.

Team Size : 7.

Project 15 HSS 04G, 06G, 07G, 10G & 11G Back Plane, Full Duplex,

Infini Band, SSF 4G, SQUALL and PCIEXPRESS Cores 65 nm Jan 07 - Dec 07.


Description : Physical Design for IBM - 65 nm - HSS Cores.

Tools & Technologies : IBM EDA Tools - GUIDE, ChipBench and Chip Edit, EinsTimer.

Operating System : IBM - AIX and Windows - XP.


Responsibilities / Contribution : Planned and performed various Physical Design tasks including Floorplanning, Congestion

Analysis, Clock Tree Synthesis (C.T.S.), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis (S.T.A.), Noise Analysis, Lay Out Checks, Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 7.

Project 16 HSS 04G / 06G / 07G & 11G Back Plane, Full Duplex, InfiniBand , SSF4G, CALRES 04G/06G, SQUALL and PCIEXPRESS CORES 90 nm

Oct 04 - Dec 07.





Responsibilities / Contribution : Planned and performed various Physical Design tasks including Floorplanning, Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks, Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 7.

Project 17 PCI23 90nm Oct 04 - Dec 04.


Description : Physical Design for IBM - 90nm - Cores.


Operating System : IBM - AIX and Windows - XP.Role Played : Project Leader .

Responsibilities / Contribution : Planned and performed various Physical Design tasks including Floorplanning, Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks, Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 7.

Project 18 CYCLONE 90nm Sep 04 - Oct 04.

Customer Name : IBM - East Fishkill, NY, USA.





Role Played : Project Leader.

Responsibilities : Planned and performed various Physical Design tasks including Floorplanning, Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks, Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 7.

Project 19 STINGRAY1.1 130nm Aug 04 - Sep 04.


Description : Implemented ECOs for Timing Closure on customer request.



Role Played : Project Leader .Responsibilities : Implemented ECOs for Timing Closure on

customer request.

Team Size : 3.

Project 20 6G CALRES and U6JM_CALRES 130 nm Jan 04 - May 04.


Description : Physical Design for IBM - 130nm cores.


Operating System : IBM AIX.

Role : Project Leader.

Contribution : Planned and performed various Physical Design tasks including Floorplanning ,

Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis

( S.T.A. ), Noise Analysis, Lay Out Checks, Cmoschks, Generation of GDS, EDIF,

LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 1.

Project 21 HSS BP, FD, IF, SSF and PCIEXPRESS Cores 130 nm Aug 02 - Jul 04.

Project Site : IBM India Private Limited, Bengaluru.Description : Physical Design for IBM - 130nm cores.Tools & Technologies : IBM EDA Tools - GUIDE, ChipBench and Chip

Edit, EinsTimer. Operating System : IBM AIX.Role : Project Engineer.

Contribution : Planned and performed various Physical Design tasks including Floorplanning ,

Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks,Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 1.

Project 22 SCSI SPI 5 130 nm Jun 02 - Aug 02.



Tools & Technologies : IBM EDA Tools GUIDE, ChipBench and Chip Edit, EinsTimer.


Role : Project Engineer.

Contribution : Planned and performed various Physical Design tasks including Floorplanning , Congestion Analysis, Clock Tree Synthesis ( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring, Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks,Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 1.

Project 23 ZEPHYRLOGIC 130 nm Apr 02 - Jun 02.






Contribution : Planned and performed various Physical Design tasks including Floorplanning , Congestion Analysis, Clock Tree Synthesis

( C.T.S. ), Clock / Scan Trace, Full Place P.D.S., Clock / Scan Optimisation, Clock Tree Wiring,

Static Timing Analysis ( S.T.A. ), Noise Analysis, Lay Out Checks,Cmoschks, Generation of GDS, EDIF, LEFs, DOTLIBs, Noise Abstracts, Running DRC & LVS Checks.

Team Size : 1.

Project 24 PXB 180 nm Jan 02 - Apr 02.


Description : IBM ASIC - Physical Design - 180 nm.





Team Size : 1.

Project 25 UNILINK 180 nm Jun 01 - Dec 01.

Project Site : IBM - East Fishkill, NY, USA.





Team Size : 1.

Project 26 SERIAL ATA 180 nm Apr 01 - Jun 01.







Team Size : 1.

Project 27 TALLIX 180 nm Jan 01 - Apr 01.


Description : IBM - ASIC - Physical Design - 180 nm.


Operating System : IBM AIX.Role : Project Engineer.


Team Size : 1.

Project 28 OBERIC 180 nm Sep 00 - Jan 01.

Project Site : IBM India Private Limited, Bengaluru ( 03 months ) and IBM - East Fishkill, NY, USA ( 01 month ).






Team Size : 1.

Project 29 DENALI 260 nm Oct 99 - Sep 00.

Project Site : IBM India Private Limited, Bengaluru ( 08 months ) and IBM , Burlington, Vermont, USA ( 03 months ).






Team Size : 1.Project 30 ORION 360 nm May 99 - Oct 99.







HONORS AND AWARDS

I have secured 14th Rank in the Engineering Section and 84th Rank in the Medical Section out of 70,000 students who appeared in the National Level Karnataka Common Entrance Test ( KCET ) conducted by the Karnataka Examinations Authority ( KEA ) during the academic year 1994.

" IBM FIVE YEAR SERVICE AWARD " awarded by IBM as on 03 - AUG - 2003.

" IBM ASIC EXCELLENCE AWARD " awarded by IBM as on 15 - SEP - 2004.

PROFESSIONAL TRAINING COURSES and CONFERENCES ATTENDED

IBM INDIA PRIVATE LIMITED : TRAINING COURSES

1. “ VHDL Coding “ Internal Training Course at IBM , Bengaluru , Karnataka , India ( Two Months ; August 1998 to October 1998 ).

2. “ VLSI A.S.I.C. Flow “ Training Course at D'GIPRO - Bengaluru , Karnataka, India.( One week ; November 1998 ).

3. “ VHDL Coding ” Training Course at Indian Institute of Science - Bengaluru , India.( Three days ; December 1998 ).

4. IBM internal Physical Design Test Cases namely “CRANE” and “EAGLE” at IBM Bengaluru ( Two months ; December 1998 to February 1999 ).

5. ChipBench and ASOK Training Course at IBM Burlington, Vermont, U.S.A. ( One month ; March 1999 to April 1999 ).6. Annual V.L.S.I. Conference held at Science City , Calcutta, West Bengal , India ( Three days ; January 2000 ).7. “ASIC Speciality Training ( AST )“ held at IBM , Bengaluru, India. ( September 2002, 2003, 2004 and 2005 ).8. “ Variation Aware Timing ( VAT )” Training class held at IBM , Bengaluru , India. ( June 2004 ).9. “ DFM and DFY Tools” class delivered by Mentor Graphics at IBM , Bengaluru , India ( August 2007 ).

WIPRO TECHNOLOGIES : TRAINING COURSES

1. “ Magma EDA Tool - A.S.I.C. - P.D. Flow “ self training course at Wipro Technologies, Kochi, Kerala, India ( One Month ; September 2008 ).

2. “ Dynamic I.R. Drop Analysis “ class held at Wipro Technologies , Kochi, Kerala, India ( September 2008 ).

3. “ Future Trends in V.L.S.I. Design “ class held at Wipro Technologies , Kochi, Kerala, India ( September 2008 ).

4. “ Introduction to D.F.T.” class held at Wipro Technologies - Kochi, Kerala, India ( October 2008 ).4. “ RFQ Calc ( Static and Dynamic Power ) “ presentation held at Wipro Technologies, Kochi, Kerala,

India ( October 2008 ).

6. “ Texas Instruments - Warp Core Power Router “ presentation offered by Texas Instruments , Bengaluru ( November 2008 ).7. “ I.C.P and A.I.C.P. “ Training programme on “Interviewing Skills” offered by Wipro Technologies , Kochi ( November - 2008 ).

CYIENT : TRAINING COURSES

1. Training course on the Physical Design Flow with Cadence Encounter on the Novafora TestCase at Cyient, Bengaluru starting May 2014.

2. Attended a presentation delivered by Cadence Team on “AZURO” regarding “ Clock Optimization and Power Optimization” on 11 - July - 2012 at Cyient, Bengaluru.

3. “ First Time Managers “ at Cyient , Bengaluru on 17th and 18th of October 2011.4. “ New Hire Orientation” at Cyient , Bengaluru on 2nd and 3rd of November 2011.5. “ IBM APS1 & APS2 Lectures and Lab Sessions” web based tutorials at Cyient , Bengaluru between

04th and 18th of November 2011.

JOB INTERVIEWS CONDUCTED

1. I have interviewed Fifty Physical Design candidates at Synapse, Bengaluru in the Physical Design domain during the period October - 2014 to March - 2015.

2. I have interviewed Six Physical Design candidates at Cyient, Bengaluru in the Physical Design domain on 24th and 25th of May - 2014.

3. I have interviewed Fourteen Physical Design candidates at Cyient , Bengaluru in the Physical Design domain on 09th and 10th of June - 2012.4. I have interviewed Two Physical Design candidates at Cyient , Hyderabad in the Physical

Design domain on 22nd and 23rd of December - 2011. TECHNICAL LECTURES , PRESENTATIONS and MENTORING ACTIVITIES

1. Lecture class on “ Dynamic IR Drop Analysis ” at Wipro Technologies , Kochi , Kerala during January - 2009.

2. Mentored all the Freshers who joined the “ IBM Physical Design HSS Team “ during the years 2006 and 2007.

3. Lecture class on “ IBM MAR : Detail Router : 65 nm “ at IBM Embassy Golf Links , Bengaluru ( October - 2007 ).

4. Lecture class on “ IBM MARPO : ASIC Power Routing : 65 nm “ at IBM , Manyatha , Bengaluru ( October - 2007 ).

5. Presentation on “ IBM Williwaw2 : Testsite “ for the HSS Physical Design Team at IBM Embassy Golf Links , Bengaluru ( September - 2007 ).

6. Presentation on “ IBM GYM EDA Tool “ for the Freshers Batch August 2007 at IBM Embassy Golf Links, Bengaluru ( August - 2007 ).

7. Lecture class on “ IBM HSS Cores : 130 nm and 90 nm “ at IBM Embassy Golf Links , Bengaluru ( March - 2007 ).

8. Presentation on “ IBM GYM EDA Tool “ for the Freshers Batch : January 2007 at IBM Embassy Golf Links, Bengaluru ( January - 2007 ).

9. Presentation on “ IBM GYM EDA Tool “ for the IBM Physical Design Team at IBM Embassy Golf Links, Bengaluru ( January - 2002 ).

10. Lecture class on “ Analog Electronics “ at IBM , Golden Enclave , Bengaluru during April - 2000. 11. Lecture class on “ Physics “ including the topics like “ Optics, Sound, Current Electricity, Magnetism

and Modern Physics ” at IBM , Golden Enclave , Bengaluru during January - 2000.12. Lecture class on “ Mathematics “ including the topics like “ Arithmetic , Algebra, Geometry, Analytical

Geometry, Trigonometry and Calculus “ at IBM , Golden Enclave, Bengaluru during July - 1999.

Date : May - 2015. Place : Bengaluru, Karnataka.

Documents

Girish_Viswanath_Bellary_Resume_July_2015