Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

1852 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 6, JUNE 2013

Germanium Multiple-Gate Field-Effect TransistorsFormed on Germanium-on-Insulator Substrate

Bin Liu, Xiao Gong, Chunlei Zhan, Genquan Han, Hock-Chun Chin, Moh-Lung Ling, Jie Li, Yongdong Liu,Jiangtao Hu, Nicolas Daval, Christelle Veytizou, Daniel Delprat, Bich-Yen Nguyen,

and Yee-Chia Yeo, Member, IEEE

Abstract— We demonstrate the integration of high perfor-mance p-channel Germanium Multiple-Gate Field-Effect Tran-sistors (MuGFETs) on a Germanium-on-Insulator substrate.Detailed process conditions are documented in this paper. Theeffects of Ge fin doping concentration on the electrical perfor-mance of Ge MuGFETs are discussed, and this could be useful forfurther device optimization. It is found that a higher fin dopingleads to better control of short-channel efforts of Ge MuGFETsbut degrades the on-state current and transconductance. Highon-state current for Ge MuGFETs is reported in this paper.

Index Terms— Fin doping, FinFETs, GeOI, Germanium, metalS/D, MuGFETs, OCD.

I. INTRODUCTION

AS scaling of complementary metal-oxide-semiconductor(CMOS) enters the sub-20 nm regime, carrier transport

in the transistor is quasi-ballistic and the drive current will beultimately limited by the injection velocity [1], [2], instead ofthe saturation velocity in the case of long channel devices. Theinjection velocity was experimentally found to be proportionalto low field mobility [3]. Therefore, high mobility channelmaterial is desirable for future low voltage and high speedCMOS applications. Germanium (Ge) is considered as one ofthe most promising channel materials to replace silicon (Si) infuture CMOS applications due to its high carrier mobilities,especially hole mobility [4]–[11].

Starting from the 22 nm technology node, Si channelMultiple-Gate Field-Effect Transistors (MuGFETs) or Fin-FETs have been used for high volume CMOS production, as

Manuscript received January 11, 2013; revised March 25, 2013; acceptedApril 10, 2013. Date of current version May 16, 2013. This work wassupported by the National Research Foundation of Singapore under GrantNRF-RF2008-09. The review of this paper was arranged by Editor W. Tsai.

B. Liu, X. Gong, C. Zhan, G. Han, and Y.-C. Yeo are with theDepartment of Electrical and Computer Engineering, National University ofSingapore, Singapore 119260, Singapore, and also with the NUS GraduateSchool for Integrative Sciences and Engineering, National University ofSingapore, Singapore 117456, Singapore. (e-mail: [email protected];[email protected]; [email protected]; [email protected];[email protected]).

H.-C. Chin, M.-L. Ling, J. Li, Y. Liu, and J. Hu are with NanometricsInc., Milpitas, CA 95035 USA (e-mail: [email protected];[email protected]; [email protected]; [email protected];[email protected]).

N. Daval, C. Veytizou, D. Delprat, B.-Y. Nguyen are with theSoitec Parc Technologique des Fontaines, Bernin F-38190, France(e-mail: [email protected]; [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2013.2258924

Fig. 1. 3-D schematics demonstrating the key process steps to fabricateGe MuGFETs on GeOI substrate. (a) Channel implant and dopant activation;(b) Fin patterning and etch; (c) Cyclic DHF-H2O etch; (d) High-κ deposition;(e) TaN deposition; (f) TaN etch and NiGe formation.

the additional gates provide improved short channel control forextremely scaled devices [12]–[14]. High mobility Ge channelFET with multiple-gate structure [15]–[23] could be adoptedto achieve high drive current and good short channel control atsub-20 nm technology nodes. Germanium-on-Insulator (GeOI)substrate is a good platform for realizing high performance GeMuGFETs [24]. Although Ge planar FETs have been studied,integration of 3-D Ge MuGFETs with high-κ metal gate onGeOI substrate is not well explored or developed yet.

In this paper, we report omega-gate (�-gate) MuGFETsformed on GeOI substrates, featuring low temperature Si2H6passivated channel, high-κ dielectric and metal gate stack,and self-aligned metallic nickel germanide (NiGe) source/drain(S/D). Transistors were fabricated using Si CMOS compatibleprocess modules developed in this paper. The effects of findoping on Ge MuGFET electrical characteristics will be inves-tigated. Initial results were published in [25]. In this paper,we provide a more detailed documentation of the fabricationprocess as well as results and discussion.

II. DEVICE FABRICATION

Fig. 1 shows the 3-D schematics illustrating the key processsteps used to fabricate Ge MuGFETs. The correspondingdevice structure formed after each process step is shown.High quality GeOI samples were formed by SmartCutTM

technology, and used as starting substrates.

0018-9383/$31.00 © 2013 IEEE

LIU et al.: GERMANIUM FETs ON GERMANIUM-ON-INSULATOR SUBSTRATE 1853

Fig. 2. (a) TEM micrograph showing the cross-section of a Ge fin teststructure. (b) Schematic illustrating five key floating or fitting parameters inthe OCD model. These parameters are useful for monitoring key processvariations. (c) SEM top view of the periodic grating of the Ge fin structureused in the OCD analysis. SE beam was oriented perpendicular to the Gefin during data collection. (d) Zoomed-out cross-sessional TEM image of theOCD test structure. (e) Comparison of measured (symbols) and simulated(lines) N(�), C(� , �), and S(� , �) spectroscopic spectra, where � is theangle whose tangent is the ratio of the magnitudes of the total reflectioncoefficients, and � is the change in phase difference between s-polarizationand p-polarization before and after reflection from the sample [28]. Excellentspectral fitting was achieved.

After depositing a 10 nm SiO2 capping layer, phospho-rus (P) channel implant [as shown in Fig. 1(a)] was per-formed to dope the Ge layer n-type. Two different P doses(8 × 1012 cm−2 and 1.6 × 1013 cm−2) were used onseparate samples to study the effect of channel or fin dopingconcentration on the electrical characteristics of Ge MuGFETs.Devices with P dose of 8 × 1012 cm−2 and 1.6 × 1013 cm −2

will be referred to as “device with low fin doping” and “devicewith high fin doping”, respectively. The same implant energyof 30 keV was used for both of the implant splits. The dopantswere activated using a 600 °C 60 s anneal in a Rapid ThermalProcessing (RTP) system [26].

After P implantation and activation, Ge fins were definedby electron beam lithography (EBL) and dry-etched usingChlorine-based plasma [Fig. 1(b)]. After resist stripping inoxygen plasma, nondestructive in-line characterization of Crit-ical Dimension (CD) and profile of the Ge fin structure wasperformed by scatterometry Optical CD (OCD) measurement.Transmission Electron Microscopy (TEM) was used to exam-ine the cross-section of a Ge fin test structure [Fig. 2(a)]. Aschematic in Fig. 2(b) illustrates the key parameters of interestin the OCD model to monitor key process variations. Thefive floating or fitting parameters include fin width (WFIN),fin height (HFIN), buried oxide thickness (TBOX), oxide recessheight (HREC), and hardmask thickness (THM). The OCDmeasurement was carried out by spectroscopic ellipsometry(SE), with the propagation of optical beam oriented perpen-dicular to the periodic Ge fin grating structure, as shown inFig. 2(c). The Angle of Incidence is 65°, as indicated in Fig.2(d). A zoomed-out cross-sessional TEM image of the Gefin test structure is shown in Fig. 2(d). Fig. 2(e) shows themeasured (symbols) and best fitted (lines) spectra simulated

0.00

0.02

0.04

0.06

0.08

0.10

HRECTBOX HFINWFINTHM

3σ (n

m)

Floating Parameters

0 50 100 1500

50

100

150 Ge Fin Width, WFIN

WF

IN b

y O

CD

(nm

)

WFIN by SEM (nm)

Slope = 1.0

49

TEM (nm) OCD (nm)WFIN 99.6 98.8 TBOX 138.2 140.5 HREC 19 18.2 HFIN 56.8 55.2 THM 8 8.7

Fig. 3. (a) Correlation of fin width measured by OCD and by SEM isexcellent with Coefficient of Determination, R2, of 0.997 and slope of 1.049.In addition, OCD parameters were also compared with those obtained byTEM analysis, and a good match was achieved. (b) Ten independent OCDmeasurements were performed on the same site, and the 5 OCD parameters(TBOX, HREC, WFIN, HFIN, and THM) were extracted. σ is the standarddeviation of each OCD parameter obtained from the measurements. A low 3σfor all floating parameters indicates the good static precision or repeatabilityof the OCD characterization.

Fig. 4. Cross-sectional SEM image of a Ge fin test structure after fin etchand DHF (1:50) dip. The encroachment of SiO2 layer can be clearly seen.

from Rigorous Coupled Wave Analysis and adjustment ofmodel parameters [27]. Fig. 3(a) reveals excellent correlationon fin width between OCD and scanning electron microscopy(SEM). All other parameters from OCD also match well withthose from TEM [inset of Fig. 3(a)]. Excellent static precision,with 3σ lower than 0.1 nm, was achieved in all parameters,as shown in Fig. 3(b).

After formation of Ge fins, a cyclic dilute hydrofluoricacid (DHF) and deionized water (DIW) clean was performedto remove native oxide and to undercut the SiO2 beneaththe Ge fin. The rinse time in DHF and DIW was 15 seach in one cycle and the total clean time was 150 s(i.e., 5 cycles). The undercut step enables the formation of a�-shaped metal gate, as illustrated in Fig. 1(c). Fig. 4 shows across-sectional SEM image of a Ge fin test structure after finetch and DHF clean. SiO2 undercut can clearly be observed.The samples were then loaded into an ultra-high vacuum(UHV) tool for pre-gate sulfur hexafluoride (SF6) plasma cleanfor 50 s to remove any residual native oxide on Ge fins. Insitu disilane (Si2H6) treatment was then performed to form ahigh quality Si passivation layer with the chamber temperatureless than 400 °C to avoid any Si and Ge inter-diffusion [6],[29]–[30]. Gate stack comprising ∼4 nm HfO2 and TaNwas then deposited by atomic layer deposition and sputtering,


(a) (b)

Fig. 5. (a) HRTEM of TaN/HfO2/SiO2/Si stack formed on top of a Gefin. The Si passivation layer was partially oxidized. (b) Gate leakage currentIG vs. gate voltage VG plot of a gate pad with an area of 10−4 cm2 formedon bulk Ge substrate.

Fig. 6. Schematics of NiGe formation on Ge fin (nongate region)(a) without and (b) with removal of metal spacers. Successful removal ofTaN spacers adjacent to the Ge fin leads to a larger NiGe contact area. This iscrucial to maintain a relatively small source/drain resistance for Ge MuGFETs.(c) TEM image of NiGe formed on Ge fin, showing NiGe formed on thesidewalls of the fin.

respectively [Fig. 1(d) and (e)]. Fig. 5(a) shows a high resolu-tion TEM (HRTEM) image of TaN/HfO2/SiO2/Si stack formedon top of a Ge fin. The Si passivation layer was partiallyoxidized. In a separate experiment involving Si2H6 treatmentof Ge0.97Sn0.03 surface, which is similar to Ge, data obtainedfrom X-ray Photoelectron Spectroscopy indicate the presenceof both SiO2 and Si beneath the HfO2 layer. Fig. 5(b) showsthe gate leakage current IG as a function of gate voltage VG ofa metal gate pad having an area of 10−4 cm2 which was formedon bulk Ge substrate. Very low gate leakage current density of∼ 1.5 × 10−6 A/cm2 was obtained from the Si2H6 passivatedgate stack at a gate voltage VG of −1 V, indicating the highquality of the gate stack. The capacitance-equivalent thicknessof the gate stack measured for a long channel transistorfabricated on bulk Ge substrate using the same gate stackformation process is ∼ 1.7 nm.

Gate patterning was then performed by EBL, followed bygate etch. Due to the topology of the vertical fin channel, metalgate spacers are usually formed adjacent to the Ge fin after thenormal gate etch process used for planar devices. These metal

TABLE I

GATE ETCH RECIPES FOR TaN GATE ETCH (MAIN ETCH FOR REMOVING

TaN IN PLANAR REGION) AND TaN SPACER REMOVAL (OVER-ETCH

STEP). THE TaN SPACER REMOVAL RECIPE EMPLOYS CHF3 TO ACHIEVE

A MUCH HIGHER ETCH SELECTIVITY

OF TaN OVER HFO2

Recipe Name Cl2(sccm)

Ar(sccm)

CHF3(sccm)

He-O2(sccm)

SubstrateBias (W)

TaN gate etchrecipe 200 0 0 0 200

TaN spacerremoval recipe

120 40 80 10 80

spacers are not desirable, as they not only lead to possible gate-to-S/D short, but also reduce the S/D contact area when NiGecontact is formed. It is essential to maintain as large a contactarea as possible to reduce contact resistance for MuGFETs.Fig. 6(a) and (b) show two cross-sectional schematics of NiGeformed on Ge fins (nongate region) without and with metalgate spacers removed, illustrating the benefit of removing TaNspacers adjacent to the Ge fin. Therefore, it is crucial toremove the metal gate spacers to achieve as low a contactresistance as possible. In this paper, a two-step gate etchprocess was developed, of which the first etch step employsthe TaN gate etch recipe while the second step uses a TaNspacer removal recipe. Table I shows the recipes used in thispaper. In the TaN spacer removal step, CHF3 was used toenhance the TaN:HfO2 etch selectivity. Fluorine-based plasmacould suppress the HfO2 etch rate by forming HfOXFY on theHfO2 surface [31]. Moreover, the substrate bias in the TaNspacer removal recipe was purposely reduced to achieve betterselectivity of TaN:HfO2 and to increase the degree of isotropyin the etching of TaN underneath the Ge fin.

After gate etch, 10 nm Ni was sputtered, followed by a two-step sub-400° C annealing process (250° C /330° C) [32], [33]to form the self-aligned NiGe metallic S/D. Fig. 6(c) shows aTEM image of NiGe formed on a Ge fin with a fin width WFINof ∼ 55–60 nm. The NiGe formation on both of the sidewallsof Ge fin is clearly demonstrated, as the TaN spacers alongthe fin sidewalls were removed.

Fig. 1(f) shows a final 3-D device structure of the transistorfabricated in this paper. Fig. 7(a) is a tilted-view SEM imageshowing the layout of a MuGFET. Fig. 7(b) shows a TEMimage of a MuGFET sample with FIB cut direction indicatedin the SEM image [Fig. 7(a)]. The �-shaped metal gate wrapsaround the Ge fin which has a HFIN of ∼ 23 nm and a WFINof ∼ 85 nm. Devices with WFIN from ∼ 60 nm to ∼ 100 nmand physical gate length LG from ∼ 90 nm to ∼ 380 nm werefabricated.

III. RESULTS AND DISCUSSION

Fig. 8(a) and (b) shows the drain current |ID | versus gatevoltage VGS curves for two Ge MuGFETs which have asame LG of ∼ 330 nm and a same WFIN of ∼ 85 nm, butreceived with two different P implant doses of 8 × 1012 cm−2

(low fin doping) and 1.6 × 1013 cm−2 (high fin doping)


(a) (b)

Fig. 7. (a) SEM image of a transistor fabricated in this paper. The line alongwhich FIB cut was made is also shown. (b) TEM image of the device alongthe TaN gate line as indicated in the SEM image in Fig. 7 (a), showing the�-shaped metal gate. Fin height HFIN of the MuGFET is ∼ 23 nm and finwidth WFIN is ∼ 85 nm.

(a) (b)

-2 -1 0 110-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

VDS = -1 V

VDS = -50 mV

WFIN = ~85 nmLG = ~330 nm

High Fin Doping

Dra

in C

urre

nt|I D

| (A

/µm

)

Gate Voltage VGS (V)-2 -1 0 1

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

VDS = -1 V

VDS = -50 mV

WFIN = ~85 nmLG = ~330 nm

Low Fin Doping

Dra

in C

urre

nt|I D

| (A

/µm

)

Gate Voltage VGS (V)

Fig. 8. |ID |-VG S characteristics of two MuGFETs having the samephysical LG of ∼ 330 nm and the same WF I N of ∼ 85 nm,but different phosphorus implant doses: (a) 8 × 1012 cm−2 and(b) 1.6 × 1013 cm−2.

during channel implant. The values of drain current reportedin this work are normalized by the total effective channelwidth WEFF, where WEFF is calculated as WFIN + 2 HFIN + 2WFIN,Btm [WFIN,Btm is illustrated in Fig. 7(b)]. WEFF of thesetwo devices in Fig. 8 are ∼ 165 nm. At VDS = −50 mV,both devices demonstrate similar subthreshold swing Sof ∼ 180 mV/decade, and show good ION/IOFF ratio of morethan 104. At VDS = −1 V, the device with low fin dopingshows higher off-state leakage current. The high off-stateleakage current at low VGS could interfere with the extractionof S as much of the subthreshold region may not be observeddue to a high leakage floor. As a result, the device with low findoping has a higher S than the device with high fin doping atVDS of −1 V. In addition, the MuGFET with high fin dopingexhibits a smaller DIBL of 107 mV/V, as compared with theMuGFET with low fin doping. Although the difference inchannel doping concentration is expected to lead to a thresholdvoltage VTH difference of ∼ 53 mV, it should be noted thatno significant VTH difference was observed on the two devicesin Fig. 8(a) and (b). This could be due to the following twofactors. Firstly, the device-to-device variation of VTH is large,

Fig. 9. Cumulative plot of IMIN for MuGFETs with different fin dopings.IMIN is the minimum value of the drain current |ID| in the |ID|-VGS plot atVDS = −1 V. MuGFETs with high fin doping show significantly lower IMINas compared with those with low fin doping.

100 200 300 4000

200

400

600

Low Fin doping High Fin doping 1

DIB

L (m

V/V

)

Gate Length (nm)

Fig. 10. DIBL-LG characteristics of MuGFETs with low and high fin doping.DIBL increases as LG scales down. Device with high fin doping and a gatelength of ∼ 90 nm has a DIBL of ∼ 330 mV/V.

which is believed to be due to random dopant fluctuation [34],Ge fin height variation [35], and fin width and gate lengthvariation. Secondly, the number of devices fabricated for eachLG and WFIN is small, which is due to low throughput of EBL.The small VTH shift due to doping difference is believed to bemasked by device-to-device variation.

Fig. 9 shows the cumulative plots of IMIN (the mini-mum drain current in the |ID|-VGS plot) at VDS = −1 Vfor devices with different fin doping concentrations, demon-strating that devices with high doping have lower IMIN.MuGFETs with low and high fin doping show median IMINof1.55 × 10−6 A/μm and 3.84 × 10−8 A/μm, respectively.Fig. 10 shows DIBL-LG characteristics of MuGFETs with lowand high fin doping. DIBL increases as LG scales down forboth splits. The devices with high fin doping have lower DIBLat a fixed LG, as compared with the MuGFETs with low findoping. Devices with the same high fin doping and a LG of∼ 90 nm, but different WFIN of ∼ 85 nm and ∼ 60 nm showDIBL of ∼ 330 mV/V and ∼ 265 mV/V, respectively.

Despite the use of multiple-gate structure and small findimension (∼ 23 nm × ∼ 85 nm), the device with low findoping has poor control of short channel effects. This could be


Fig. 11. (a) S-Temperature T and (b) VTH-T plots for a MuGFET with highdoping and WFIN of ∼ 85 nm. The grey lines are best fit lines.

due to negative charges at the Ge-SiO2 interface, as discussedin the literature [36], [37]. Depending on n-type Ge dopingconcentration and the backside negative charge density, thecharges could possibly induce weak to strong surface inversionof n-type Ge even without a gate bias. This possibly leads toa source-to-drain leakage current path and poor short channelcontrol. From the experimental data, the effect of the backsidehole inversion of the GeOI substrate could be important indetermining the short channel effects for devices with lowfin doping. Further device simulation accurately modeling thebackside interface charges could provide better understandingof the impact of doping concentration on short channel effectof Ge MuGFETs on GeOI substrates.

At positive VGS (Fig. 8), increasing VGS reduces the back-side hole inversion charge density and the resulting source-to-drain leakage via hole conduction. Therefore, the IOFFcomponent that increases with increasing VGS is not relatedto the parasitic backside hole channel. The dominant leakagecurrent observed at positive VGS (or accumulation bias) isdue to front-side electron tunneling from the drain to thechannel through the NiGe/n-Ge Schottky barrier. This tunnel-ing probability increases with increasing VGS . At lower findoping [Fig. 8(a)], the electric field from the gate extendsdeeper into the Ge fin, influencing a larger NiGe/n-Ge junc-tion area and giving rise to a larger IOFF. A higher findoping [Fig. 8(b)] increases the front-side drain-to-channeltunneling probability, but the drain-channel junction area influ-enced by the gate is reduced, and this could explain thelower IOFF.

Low temperature characterization was performed on aMuGFET with high fin doping to study the backside interfacecharge effect. Temperature dependences of S and VTH areshown in Fig. 11(a) and (b), respectively, where the graylines are best fit lines. The slope of ∂S/∂T observed is∼ 0.83 mV/decade.K, which is much larger than the the-oretically predicted value of ∼ 0.2 mV/decade.K. This isbelieved to be due to both the front side HfO2/SiO2/Si-Ge andbackside Ge-SiO2 interface charges. VTH-T plot in Fig. 11(b)indicates a ∂VTH /∂T of ∼ 1.29 mV/K. The larger temperaturedependence of VTH, as compared with the theoretical valuecorresponding to channel doping of ∼ 1017 cm−3, further

Fig. 12. (a) |ID|-VGS and (b) GM-VGS characteristics at VDS = −1 Vof MuGFETs having the same LG and WFIN, but different P dopingconcentrations. Device with a low fin doping has higher drain current andpeak transconductance.

suggests the existence of backside interface charge effect ondevice electrical characteristics [38], [39].

The backside charges at the Ge-SiO2 interface bring newchallenge to integration of FinFETs/MuGFETs on GeOI sub-strates. The experimental data in this paper indicate onepossible direction to overcome the problem, i.e., doping theGe. The Ge region near the buried oxide could be dopedmore heavily to have better short channel control. Increasingfin doping results in substantial leakage current reductionespecially at high drain voltage, e.g., VDS = −1 V, and bettershort channel control. This is because higher fin doping couldhelp prevent the formation of surface inversion by providingmore space charges to balance the negative interface charges[36], suppressing hole conduction via the parasitic back chan-nel. A higher channel doping also decreases depletion widthof n-Ge, improving gate control and reducing subthresholdleakage current. Passivating the Ge-SiO2 backside interfacealso reduces leakage [37]. MuGFETs with �-shaped gate areexpected to have better gate control as compared with planarFETs with similar body thickness, due to the additional gatesand a smaller backside Ge-SiO2 area.

However, high fin doping leads to performance degradationin terms of drive current as well as transconductance. Thisphenomenon was also observed in Si FinFETs [40], [41].Fig. 12(a) shows |ID |-VGS characteristics at VDS = −1 Vof the same two Ge MuGFETs as in Fig. 8(a) and (b),demonstrating the device with low fin doping has higher draincurrent. Similarly, device with low fin doping also show bettersaturation transconductance GMSat as shown in the GMSat-VGS characteristics with VDS = −1 V in Fig. 12(b). Asexpected, a higher fin doping degrades the current as well asthe transconductance, even though it leads to better control ofshort channel effects. This is partially caused by the increasedcarrier scattering due to the additional dopants in the channel.

In addition, it is also observed that the device with higherfin doping has a larger source/drain series resistance RSD,as demonstrated by the total resistance RTOTAL-|VGS| plot inFig. 13. RTOTAL is extracted using VDS/ID, where VDS =−50 mV. At a high |VGS| of 6 V, RTOTAL (or extrapolated


Fig. 13. RTOTAL-|VGS| plots of the same two devices of Fig. 8, showingthat the device with a low fin doping has a lower extrapolated RSD.

Fig. 14. |ID|-VDS plots of the two devices with (a) low and (b) high findoping, showing that the device with low fin doping has a higher drain currentat the same VDS and VGS - VTH.

RSD) of the devices with low and high fin doping are ∼ 4 k�and 9 k� (or 660 �.μm and 1485 �.μm), respectively. Theformation of NiGe on sidewalls of Ge fin helps maintain RSDas low as possible. The higher RSD of device with high findoping could be possibly due to the higher hole barrier causedby the additional P doping [42], [43]. Further characterizationusing diodes is needed to verify this. No diodes were fabricatedtogether with the Ge MuGFETs on GeOI substrates in thispaper. In order to fabricate diodes on the GeOI substrates, thediode design would have to be a lateral diode having integratedn+ Ge contacts. This requires several more steps, includingadditional lithography and n-type dopant activation steps withhigh thermal budget.

The enhanced carrier scattering induced by additional findoping and the larger RSD result in smaller on-state currentION of the MuGFET with high fin doping. As observed fromthe |ID|-VDS characteristics in Fig. 14(a) and (b), deviceswith low and high fin doping show ION of 330 μA/μm and197 μA/μm, respectively, at VDS = −1 V and VGS − VTH =−1 V. An even higher drive current of ∼ 450 μA/μm wasachieved for a MuGFET with low fin doping, smaller gatelength of ∼ 160 nm, and DIBL of ∼ 450 mV/V (not shownhere).

150 200 250 300 350

20

30

40

50

60

VDS = -50 mVWFIN = ~85 nm

Low Fin Doping High Fin Doping

Gate Length LG (nm)Peak

Tra

nsco

nduc

tanc

e G

MLi

nMax

(μS/

μm)

Fig. 15. Peak linear transconductance GMLinMax versus LG for devices withlow and high fin doping. GMLinMax increases as LG scales down.

Fig. 16. Comparison of on-state current ION of the devices in this paperwith other Ge multiple-gate devices in the literature at similar VDS and gateoverdrive [15]–[23]. High ION is achieved in this paper for Ge MuGFETsfabricated by top-down approaches (in squares). Transistors fabricated usingbottom-up approaches (Ge nanowire grown by CVD) [15]–[16] are plotted indiamonds.

Fig. 15 shows peak linear transconductance GMLinMax ver-sus LG for devices with low and high fin doping. It couldbe observed that GMLinMax increases as LG scales downfor both of the splits. Further scaling of LG will lead tohigher transconductance and drive current, demonstrating goodscalability of Ge MuGFETs.

Drive currents of Ge MuGFETs in this paper are comparedwith those of other Ge MuGFETs reported in the literatureat similar but not exactly the same VDS and gate over-drive[15]–[23] [see ION-LG (log scale) plot in Fig. 16]. VDS andgate over-drive used in each report are shown in the insetof Fig. 16. All current values are normalized by WEFF orperimeter for fair comparison. Devices reported by [15] and[16] were fabricated by bottom-up methods (i.e., Ge fins wereformed by CVD method and no etching was used). Devicesin the other publications [17]–[23] were formed by top-down fabrication techniques which are more compatible withexisting CMOS manufacturing processes. Ref. [21] reportedION of 385 μA/μm at VDS = −1.2 V and VGS – VTH =−0.8 V. At VDS = −1.2 V and VGS – VTH = −0.8 V, ourdevice has an ION of ∼ 380 μA/μm. High on-state currentis achieved in this paper for Ge MuGFETs fabricated by top-down approaches.


IV. CONCLUSION

In conclusion, we demonstrated the integration of high per-formance Ge MuGFETs on GeOI substrate using CMOS com-patible process modules. Detailed process flow is documented.Devices with high and low fin doping concentrations showgood ION/IOFF ratio and transconductance. The MuGFETwith high fin doping is demonstrated to have better shortchannel control, but the heavier fin doping leads to reduceddrive current and transconductance. A high on-state current isreported for Ge MuGFETs fabricated by top-down approaches.It is believed that further optimization of Ge MuGFETsfabrication process could lead to even better gate controlwhile maintaining or even further improving the high drivecurrent achieved. Ge MuGFET on GeOI substrates fabricatedby a Si CMOS compatible fabrication process provides goodscalability, and could be a good candidate for future CMOSapplications.

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Bin Liu received the B.Eng. degree in electricalengineering from the National University of Singa-pore, Singapore, where he is currently pursuing thePh.D. degree.

His current research interests include multiple-gate Ge MOSFETs, strained-silicon MOSFETs, andreliability physics of transistors.

Xiao Gong is currently pursuing the Ph.D. degreewith the National University of Singapore, Singa-pore.

His current research interests include simulationand fabrication of high-mobility channel devices,multiple-gate transistors, and strain-channel transis-tors.

Chunlei Zhan is currently pursuing the Ph.D.degree with the National University of Singapore,Singapore.

His current research interests include low powerand high-mobility CMOS transistors’ design andfabrication.

Genquan Han received the B.Eng. degree fromTsinghua University, Beijing, China, and the Ph.D.degree from the Institute of Semiconductors, Chi-nese Academy of Sciences, Beijing, China.

He is currently with the National University ofSingapore, Singapore.

Hock-Chun Chin received the B.Eng. and Ph.D.degrees in electrical engineering from the NationalUniversity of Singapore, Singapore.

He is currently working on advanced metrologysolutions at Nanometrics, Milpitas, CA, USA.


Moh-Lung Ling received the B.Eng. and Ph.D.degrees in mechanical engineering from NationalUniversity of Singapore, Singapore.

He is currently working on advanced metrologysolutions at Nanometrics, Milpitas, CA, USA.

Jie Li received the Ph.D. degree in chemistry and theM.S. degree in electrical engineering from StanfordUniversity, Stanford, CA, USA.

He is currently a Principal Application Scientistwith Nanometrics, Milpitas, CA, USA, working onnanoscale metrology techniques.

Yongdong Liu received the Ph.D. degree in opti-cal engineering from Tsinghua University, Beijing,China.

He worked on MEMS devices at the Tokyo Insti-tute of Technology, Tokyo, Japan, and in nanopho-tonics at the University of Utah, Salt Lake City, UT,USA. He is currently with Nanometrics.

Jiangtao Hu received the Ph.D. degree in chemistryfrom Harvard University, Cambridge, MA, USA.

He is the Director of Applications Developmentwith Nanometrics, Milpitas, CA, USA. He has 12years of experience in the industry of metrologyequipment for semiconductor manufacturing.

Nicolas Daval received the Ph.D. degree in thin filmpower device design and fabrication in 2002.

His work focuses on future CMOS, high mobilitymaterials, and on-insulator substrates.

Christelle Veytizou managed some projects atSoitec, Bernin, France, in the R&D group, to developnew substrates for a Fully Depleted CMOS roadmap.

Daniel Delprat received the Ph.D. degree in microelectronics from Paris 6University, Paris, France.

He joined Soitec, Bernin, France, in 2003, where he is currently leadingthe advanced R&D Group.

Bich-Yen Nguyen joined Soitec, Bernin, France,as a Senior Fellow supporting technology devel-opment of the new SOI devices/applications. Priorto joining Soitec, she was a Senior Manager atFreescale/Motorola and a Dan Noble Fellow.

Yee-Chia Yeo (S’98–M’02) received the B.Eng.(First Class Hons.) and M.Eng. degrees from theNational University of Singapore (NUS), Singapore,and the M.S. and Ph.D. degrees from the Universityof California, Berkeley, CA, USA.

He is currently at NUS.

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Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate