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Fig. 5. Device no. 10 (140 h) depicting filament formation. The white region is an A1 wirebond.

of the curved nodules, would exert an additional force on the diffusing atoms (assuming a negative effective charge), giving rise to growth of the observed filaments.

A recent article [ 6 ] indicated that further development work is continuing in EBS technology although no further effort is being conducted at Watkins-Johnson Company. In addition, considering the common usage of phosphosilicate glass passivation, the above results may be of interest to device designers working in radiation environments.

ACKNOWLEDGMENT The authors wish to thank Dr. C. Bryson of Surface Science

Laboratories, Palo Alto, CA, for frequent instruction and assistance.

REFERENCES A. Silzars, D. Bates, and A. Ballonoff, Proc. ZEEE, vol. 6 2 , pp. 11 19- 1158,1974. D. Bates, R. Knight, S. Spinella, and A. Silzars, Watkins-Johnson Co., Palo Alto, CA, Tech. Rev. 100122-077. A. Tenney and M. Ghezzo, J.'ElectrochemSoc.,vol. 120,pp. 1091- 1095,1973. B. Todd, 3. Lineweaver, and J. Kerr, J. Appl. Phys., vol. 31, pp. 51-56.1960. J. Johanneson and W. Spicer, J. Appl. Phys., vol. 47, p. 3028, 1976. S. Ichimura and R. Shimizu, J. Appl. Phys., vol. 50, pp. 6020- 6022,1979. N. Robin and B. Ramirez, Electron. Des., pp. 50-55, Feb. 1, 1980.

Geometric Effects on the Gate-Controlled Capacitor

E. B. SLUTSKY AND J. N. ZEMEL

Abstract-The effect of p-n junction geometry on the capacitance- voltage (C-Y) and conductance-voltage (G-V) characteristics of a gate-controlled capacitor (GCC) is discussed. Three p-n junction

Manuscript received October 12, 1979; revised April 29, 1980. This paper is part of a dissertation submitted by E. B. Slutsky to The Moore School of Electrical Engineering, University of Pennsylvania, in partial fulfillment of the requirements for the Ph.D. degree.

E. B. Slutsky is with Bell Laboratories, Reading, PA 19604. J. N. Zemel is with The Moore School of Electrical Engineering, Uni-

versity of Pennsylvania, Philadelphia, PA 19104.

geometries were studied; one was a circular structure and the remaining two were cross structures. It is concluded that the effective transit distances are decreased as the geometries of the junction become more complex.

INTRODUCTION MacIver [ 11 describes a gate-controlled capacitor (GCC)

which offers an extended capacitance range by combining the p-n junction and MOS techniques to obtain operation in the deep-depletion mode. He reports capacitance changes with dc bias in the ratio of 15 : 1 in 14 V without reaching a maxi- mum. The present authors have investigated what effect the geometric shape of the diffused p-n region has on the C-V and G-V. The three geometries studied consist of one circular and two cross structpres, Fig. l(a), (b), and (c). The first cross structure has 90 between each of the ofour arms of the cross, and the second cross structure has 45 between each of the eight arms.

Zemel [ 21 , [ 31 proposed an application of this type of stmc- ture to ion-concentration measurements, and verification has been obtained by Wen, Chen, and Zemel[41.

THEORETICAL CONSIDERATIONS

The modeling technique used for the GCC is based on the distributed model proposed by Andres [5] to describe the influence of a reversed-biased p-n junction on the admittance characteristics of an MOS device. The technique consists of sectioning the GCC into small regions along the plane of its surface. The properties of each separate region are represented by an individual lump, and these lumps are then connected to form a distributed representation of the overall admittance.

Each surface region to be lumped is characterized by the use of a modified version of the capacitance model developed by Hofstein and Warfield [ 61 . The complete distributed network that describes the GCC is shown in Fig. 2. CI is the capaci- tance associated with the inversion layer charge. CI) is associ- ated with the depletion-layer charge, and the oxide capacitance is CO. A resistance R,s is associated with the current resulting from carrier generation and recombination at trapping centers located at the oxide-semiconductor interface; a similar resis- tance R,, accounts for generation and recombination in the depletion region. Finally, Rd is the resistance associated with the flow of minority carriers from the bulk to the surface. R,s, R,D, and R d are in parallel and thus can be represented by an equivalent resistor RT.

As a first approximation, it is assumed that the storage of charge at trapping centers located near the oxide-semiconduc- tor interface as well as the resistance of the bulk material be- tween the external substrate contact and the regions beneath the gate are negligible. Also, the gate metallization and the silicon substrate were assumed to offer negligible resistance. Because the n-diffused region acts as a second source of elec- trons supplying the capacitance CI of each lump, it is con- nected to each region through the distributed resistance of the inversion layer RI. One- dimensional distributed circuit model component values obtained from standard space-charge theory have been obtained [ 71, [ 81 .

For the circular GCC the lumped regions take on the appear- ance of flat doughnuts. The capacitive components of each lump are calculated by multiplying CO, CD , and Cz by the area of the top surface of the particular volume. The resistors R d , R I), and R,s are found by dividing by the same surface area.

%he accuracy of the lumped model is dependent on the num- ber of lumps selected. Andres found that over a wide range of

0018-9383/80/009-1843$00.75 0 1980 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VDL. E D - 2 7 , NO. 9, SEPTEMBER 1980

A L U M I N U M FIELD JUNCTION DEPTH

A L U M I N U M BACK

P.TYPE Si ' ( 1 0 O R m )

(b)

FIELD PLATE

IUNCTION DEPTH

BACK CONTACT

(C) Fig. 1. Gate-controlled capacitor geometries. (a) Circular-shaped p-n

junction. (b) Cross-shaped p-n junction with 90" between arms. (c) Cross-shaped p-n junction with 45" between arms.

VG values, even a one-lump model predicts the results with reasonable accuracy; however, to include the complete range of biases, Andres selected a five-lump system. The range of biases covered here are more extensive, and thus a seven-lump system was used. The loop equations can be put into matrix form and solved for the admittance [ 71. The real term G, and the imaginary term C p can be obtained from the complex admittance term.

FABRICATION High-resistivity ( p - 60-1 00 i2 cm) p-type (1 1 1) oriented

silicon was chosen as the starting material for the GCC's. A thermal oxide approximately 10 000 a thick owas grown in steam. This oxide served as the mask for a 1225 Cphosphorus diffusion resulting in a junction depth of approximately 3 pm.

P S U B S T R A T E (FLORTING) I Fig. 2. Model lumped element of a one-dimensional GCC.

After phosphorus diffusion, the thick oxide was removed and a 1500-2000-~-thick thermal oxide was immediately grown. Holes cut in the oxide provided access to the diffused p-n junction region. A 4000-&thick layer of aluminum was deposited over the silicon wafer surface, and the metal con- tacts to the p-n junction and the gate region were then delin- eated by photomasking and etching. The gate, p-n junction, and contact dimensions for each of the three models are shown in Fig. l(a), (b), and (c).

MEASUREMENTS The capacitance and conductance were measured as func-

tions of dc voltage on a Boonton Model 75C-S13 capacitance bridge with the small-signal measurement frequency varied from 5 kHz. The signal amplitude was set at 15 mV rms. A KeitNey 660A guarded dc differential voltmeter was used in conjunction with the bridge. Measurements at 1 MHz were carried out with a Boonton Model 71AR capacitance-induc- tance meter with the signal voltage at 15 mV rms. Electrical contact to the GCC was made between the gate and p-n junc- tion diffused region with substrate floating. Individual devices were tested in wafer form by probing with tungsten carbide tip probes. The wafer containing the GCC devices was mounted within a light-excluding probe box through which an inert gas was circulated.

RESULTS The Cp-Vc and GP-VG data for the three p-n junction

geometries studied are plotted as a function of frequency in Fig. 3(a), (b), and (c). Fig. 3(a) shows that for the circular- shaped p-n junction, GCC tested at a frequency of 1 MHz (over a gate voltage range of - 15 to +55 V) the inversion region capacitance changes in the ratio of 25 : 1 in 70 V, without reaching a maximum. However, Fig. 3(a) also indicates that the magnitude of the conductance term at 1 MHz, if measured, would be large. Fig. 3(a) also shows the comparison of the theoretical and experimental frequency dependent Cp-Vc and G p - v ~ curves for the circular diffused model. The agreement between experiment and theory is good. The maximum dif- ference for the Cp-Vc data occurs at 1 MHz and is 28 percent. For the other frequencies, however, the differences are less than 10 percent for both Cp-Vc and G p - v ~ .

Fig. 3(b) and (c) illustrates the results of testing the two cross-structure p-n junction GCC's as a functio? of frequency. Fig. 3(b) shows that for the structure with 90 between cross

k - 40 i

. ..

-20 0 20 4 0 60 80 100

800 1 I c

VG ( v ) (C)

Fig. 3. Frequency dependence of the measured CTVG and G ~ V G characteristics of a GCC with (a) circular-shaped p-n junction; (b) 90” between arms of cross-shaped p-n junction; and (c) 45” between arms of cross-shaped p-n junction.

arms, the inversion-region capacitance at a frequency of 1 MHz changes in the ratio of approximately 3.6: 1 in 70 V, without reaching a maximum. Fig. 3(c) indicates that the inversion region capacitance for the GCC with 45 between the arms of the cross structure p-n junction at a frequency of 1 MHz changes in the ratio of 5 : 1 in 70 V. The gate-voltage range for both cross structures is - 15 to +55 V.

DISCUSSION

It can be concluded from inspection of Fig. 3 that there is a clear dependence of the C p - v ~ and Gp-V, characteristics on

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 9, SEPTEMBER 1980 1845

the geometric shape of the p-n junction. Univ., Stanford, CA, Tech. Rep. 4825-2 SU-SEL-68-093, Office

At frequencies low enough for the mobile charge to follow the applied ac signal, the applied signal and the charge are in phase. The conductance term of the complex admittance is small, and the change in capacitance with dc voltage is rapid. At high frequencies, the mobile charge and the applied signal are not in phase due to transit time effects in the inversion layer. The conductance term of the complex admittance is no longer small relative to the capacitance term.

In the circular device, the parallel conductance increases monotonically with positive gate voltage. This can be under- stood in terms of the decreasing mobility of the carriers of the strong inversion layer with increasing surface potential. In other words, the decreased space-charge-layer mobility increases the loss in the parallel equivalent circuit model. This is seen, in part, in the one-dimensional case treated by Burns [ 9 ] . It was determined that because of the distributed nature of the model used, the mobile charge does not follow an applied voltage itep but rather exhibits a time delay. The delay time td as expressed by Burns is

td a L~ / F n ( vg - vt) (1) where pn is the effective mobility of charge carriers in the active region, Vg - V , is the operating voltage, and L is a characteristic length (in the case of an IGFET, the active channel region). Thus the delay time increases as i in de- creases. In our case, the characteristic length is determined by an average of the product of the transit time and the drift velocity over the geometry. For the complex shapes of Fig. l(b) and (c), this product is not simple to estimate. The dis- tributed character of the GCC implies that the spatial integra- tion will be highly geometry sensitive. However, as the voltage increases, the characteristic length should become inversion charge density dependent as well as mobility dependent in the cross structures. This is due to L being comparable to the spacing of the device over much of the crotch of the crosses for high-inversion charge density. As the frequency goes up, less and less of the crotch region can be reached before voltage reversal occurs. Hence, the loss term increases at high frequen- cies even for the complex structures. We conclude that the reduction in G p at higher voltages observed in Fig. 3(b) and (c) can be associated with the two-dimensional nature of the inversion layer,

These results are quite significant to the operating character- istics of the ion-controlled diode. Wen and Zemel used these results to calculate the behavior of an ion-controlled diode containing both (1 00) and (1 1 1) surfaces [ 41 . Using the basic model described herein, it has been possible to establish that precision p X measurements can be conducted where the noise level is at the p X level or better [ 101. Modeling of the ion-controlled diode using the results of this paper has been confirmed [4 ] .

REFERENCES [ 11 B. A. MacIver, “A hybrid voltage-variable capacitor,” IEEE

Trans. Electron Devices, vol. ED-18, pp. 401-408, July 1971. [ 21 Advances in Automated Analysis (Technicon International Con-

gress), vol. 1, p. 68, 1976. Available from Medraid Inc., P.O. Box 417, Tarrytown, NY, 10591.

[3] J. N. Zemel, “Chemically sensitive semiconductor devices,” Res. Develop., vol. 28, no. 4, pp. 38-44, Apr. 1977.

[4] C. C. Wen, T. C. Chen, and .I. N. Zemel, “Ion controlled diodes (ICD),” in IEDM Tech. Dig. (Washington, DC, Dec. 1978), also, IEEE Trans. Electron Devices, vol. ED-26, no. 12, pp. 1945- 1951, Dec. 1979.

[5] K. W. Andres, “A simple characterization of gate-to-substrate impedance in metal-oxide-semiconductor structures under non- equilibrium conditions,” Solid-state Electron. Lab., Stanford

I. 846 TEEE TRANSACTIONS OM ELECTRON DEVICES, VOL. ED-27, NO. 8 , SEPTEMBER 1.980

of Naval Res. Contract, NONR-225(44), NR375865, Dec. 1’368. [6] S. R. Hofstein and G. Warfield, Solid-state Electron., vol. 8, no.

321,1965. [7] E. B. Slutsky, Ph.D. Dissertation, Univ. of Pennsylvania, Philadel-

phia, PA, 19104,1974. [ 81 D. R. Frankl, in Electrical Properties of Semiconductor Surfaces.

Oxford, England: Pergamon, 1967, ch. 3. [ 91 J. R. Burns, “Large signal transit-time effects in the MOS transis-

tor,” RCA Rev., vol. 30, no. 1, pp. 15-35, Mar. 1969. [ l o ] C. C. Wen, I. Lauks, and J . N. Zemel, ‘‘Valinomycin doped

photoresist layers for K+ sensing,” submitted to Thin Solid Films.

Experimental Derivation of the Source and Drain Resistance of MOS Transistors

PAUL I . SUCIU AND RALPH L. JOHNSTON

Abstract-A new method for experimentally deriving the source-and- drain resistance of MOS transistors is presented along with experimental results verifying its accuracy. The method also yields the mobility re- duction with high gateoxide field. The measurements are done on two (or more) MOS transistors which are identical except that their gate lengths differ by a known amount.

INTRODUCTION As new MOS technologies are being tried in the quest for

ever decreasing transistor dimensions, it is necessary to mini- mize the source-and-drain resistance and t o evaluate it directly. Sheet resistivity and contact window testers can provide only an approximation to the actual source-and-drain resistance. We describe here a method of extracting source-and-drain re- sistance from the measurements of two or more transistors that are identical except for their channel lengths. The method also yields the mobility reduction due to high field in the gate oxide.

DERIVATION OF THE SOURCE-AND-DRAIN RESISTANCE Fig. 1 shows an MOS transistor with source-and-drain resis-

tance RT = Rs + R D . For small drain-to-source voltage the current is approximately

where, as in [ 1 J ,

W ch

Bo = Po c o x -

VbS = vGS - IDSRS

~ b s = VDS - IDSRT

U,, is the mobility degradation coefficient, po is the low-field

Fig. 1. MOS transistor with source-and-drain resistance.

I Vsue = 0.0 VOLTS

Vg = 0 .07V MASK L P

o.2 t O l I I I I I I 0 I 2 3 4 5 6

VQS-VT (VI

Fig. 2. Variation of E versus VGS - VT for transistors with different gate lengths.

channel mobility, Cox is the gate oxide capacitance per unit area, W is the channel width, Lch is the channel length, Rs is thy source r5sistance, and R ~ i s the source-and-drain resistance. VGS and VDS are the gate-to-source and drain-to-source volt- ages applied to the intrinsic device and VGS and VDS are those applied externally. Substituting the above relationships into ( l ) , we obtain a second-order equation in IDS with VGS and VDS as coefficients. If we assume R ~ V D ~ << R T ( V G S - V T ) (e.g., VD+S - 70 mV, VGS - VT - 1 V) we can solve for IDS and obtam

Date received February 18, 1980; revised April 30, 1980. where A = Uo + PoR,. Since VDS is very small and normally The authors are with Bell Laboratories, Murray Hill, NJ 07974. 2pORs VDS << 1, the second term under the square root is

0018-9383/80/009-1846$00.75 0 1980 IEEE