Class 14: Timing and Delays - University of Kentucky ...web.engr.uky.edu/~elias/lectures/ln_14.pdfClass 14: Timing and Delays Gate Capacitance (Martin p.261) Modeling of a gate capacitor

Joseph A. Elias, PhD 1

Class 14: Timing and DelaysTopics:1. Intro2. Fan-In and Fan-Out3. Gate Delays4. Gate Delays5. Gate Delays6. Gate Delays7. Gate Delays8. Rise Time Delay9. Rise Time Delay10. Rise Time Delay 11. Fall Time Delay12. Equal DelaysGate Capacitance13. Junction Capacitance14. Junction Capacitance15. Junction Capacitance16. Junction Capacitance17. Junction Capacitance18. Interconnect Capacitance19. Delay of CMOS Gates20. Delay of CMOS Gates


Class 14: Timing and DelaysFan-In and Fan-Out (Weste p264-267)

•Fan-in is the number of inputs connected to a gate•Fan-out is the number of outputs connected to a gate•Who cares? DELAY due to loading (what loading?)•How does one express delay of a circuit based on nodes?


Class 14: Timing and DelaysGate Delays (Weste p215)

For a transistor in saturation,

which can be written asI = β/2 (Vgs-Vtn)2

whereβ = µ Cox (W / L)

β is a conductance, since I = G V


Class 14: Timing and Delays

Given the circuit on the right (what is it?)

•When the output is pulled downwhat transistor(s) is(are) on?

•When the output is pulled up, what transistor(s) is(are) on?

Gate Delays (Weste p215)

Given that three n-ch are in series,what is the delay of the combination?

The R portion of the RC delay can be thought of as the effective β of the transistors



Equivalent β for three series (why?) n-ch transistors

Equivalent β for one (why?) p-ch transistors

Delay time α Cload Delay time α (1 / β)

so the delay through three transistors with thea capacitive load will be three times that ofa single transistor with the same capacitive load



So given the 3-input NAND gate,and assuming (why?):

One can find that the ratio:

Which is why one wants to makep-ch in parallel and n-ch in series.


Class 14: Timing and DelaysRise Time Delay (Weste p264-267)

Rise time delay

where

So based on the 3-input NAND, for a large number of gates,the number of series inputs should be limited to 2-5.

Consider the worst-case rise-time delay for an m-input NAND gate

Why p-channel?



Using

One can re-write the rise time delay as:

Rise Time Delay (Weste p264-267)



The rise time delay:

once rewritten,has the form:

where

m-n-k-r-

This is a way to break apart the rise time delay into two components:1) Internal, based on the fixed internal delay of the transisto2) Output, based on the loading

Rise Time Delay (Weste p264-267)


Class 14: Timing and DelaysFall Time Delay (Weste p264-267)

Similar to rise time delay, the fall time delay as a function of fan-in and fan-out:

This was assuming equal-sized gates (n/p size fixed)as is the case in standard cells and gate arrays

What in the eq. is thedifference betweenrise and fall times?


Class 14: Timing and DelaysEqual Delays (Weste p264-267)

Assuming equal delays gives

To achieve this, the ratios are

So p-ch would be made (βn / m βp) times widerfor equal rise and fall delay


Class 14: Timing and DelaysGate Capacitance (Martin p.261)

Modeling of a gate capacitor is complex. Why?

Active region, gate is a combination of intrinsic gate capacitanceand overlap capacitance. Overlap of what?What contributes to the terms in the equation?

Linear region, gate cap is dominated by what portion of the CV curve?This leads to the expression

Once transistor gate ramps down, the channel is in what portionof the CV curve?

That is the reason models are key to getting accurate AC simulations.


Class 14: Timing and DelaysJunction Capacitance (Martin p.261-4)

Junction capacitances are due to what part of the transistor?Assuming a 3.3V swing, it can be approximated as

What does the term Cj0 mean?This is the junction of the gate. The other portion ofthe junctions are those not against a gate.

The sidewall capacitance can be approximated by

This term accounts for the periphery not against the gate.



Where is the sidewall junction capacitance?Where is the other junction capacitances?

Junction Capacitance (Martin p.261-4)



The three types of layout to be considered todetermine junction capacitance are :a) non-shared junctions with contactsb) shared junctions without contactsc) shared junctions with contacts



•Junction Area

•Junction Periphery(w/o ct, each diff)

•Shared Junction Area

•Shared Junction Periphery

Both area and periphery much smaller.Why does this matter?



•Distance gate to gate is 3L. Why?

•Shared Junction Area

•Shared Junction Periphery

•So it is better to use a shared drain when possible


Class 14: Timing and DelaysInterconnect Capacitance (Martin p.265-7)

What is used for interconnect?•Metal•Poly•Diffusion•LI-local interconnect

What components are in the capacitance?•Parallel plate component•Fringe component

Fringe component is empirically derived for a process

Interconnect is radically changing in the next few years tocopper and low-K dielectrics. More later in the semester.


Class 14: Timing and DelaysDelay of CMOS Logic Gates (Martin p.270-1)

Given the following circuit. How would one estimate the delay time?

What is the 1->0 delay at node Vx when A input goes 0->1•What are the parasitics due to junctions?•Use the concept of equivalent resistance of a transistor to

estimate delay.

What is this?


Class 14: Timing and DelaysDelay of CMOS Logic Gates (Martin p.270-1)

•Capacitance of Cp1 is due to Q1 drain, shared with Q2 source,which is most likely a shared drain without a contact

•Capacitance of Cp2 is due to two inverters, along withthe junction capacitance of Q2 drain and Q3 & Q4 sources

•Q2 has an unshared drain with contact. How was this known?•Q3 & Q4 share a source junction with a contact. Why?

•Loading due to the inverters is 4Cox x 1.8 um^2. Where did this come from?

•A goes 0->1, then Cp1 discharge through Q1 resistance.•Cp2 will be discharged through what?

τ = Req1 Cp1 + (Req1 + Req2) Cp2

Documents

Class 14: Timing and Delays - University of Kentucky ...web.engr.uky.edu/~elias/lectures/ln_14.pdfClass 14: Timing and Delays Gate Capacitance (Martin p.261) Modeling of a gate capacitor