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General Purpose and Alternate Function I/O (GPIO and AFIO)

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GPIO Features Bi-directional I/O ports available

Standard I/Os 5V tolerant The GPIOs can sink 25mA 18 MHz Toggling Configurable Output Speed up to 50 MHz Up to 16 Analog Inputs Alternate Functions pins (like USARTx, TIMx, I2Cx, SPIx,…) Can be set-up as external interrupt One I/O can be used as Wake-Up from STANDBY (PA.00) One I/O can be set-up as Tamper Pin (PC.13) All Standard I/Os are shared in 5 ports (GPIOA..GPIOE) Locking mechanism to avoid spurious write in the IO registers: When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the configuration of

the port bit until the next reset (no write access to the CRL and CRH registers corresponding bit).

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GPIO Configuration Modes

Bit

Set/R

eset

R

egis

ters

Inpu

t Dat

a R

egis

ter

Out

put D

ata

Reg

iste

r

Read / Write

I/O p

in

Analog Input

Alternate Function Input

Alternate Function Output

To On-chip Peripherals

From On-chip Peripherals

Push-Pull orOpen Drain

TTL Schmitt

Trigger

OUTPUT CONTROL

ON

VDD or VDD_FT(1)

VSS

VDD

VSS

OFF

0

Input Driver

Output Driver

Read

Configuration Mode CNF1 CNF0 MOD1 MOD0

Input Floating (Reset State)

0 1

Input Pull-Up(2)

Input Pull-Down(2)

1 0

Output Push-Pull

0 0

01: 10 MHz10: 2 MHz11: 50 MHz

OutputOpen-Drain

0 1

AF Push-Pull 1 0

AF Open-Drain

1 1

Analog Input 0 0

00

Write

ON/OFF

ON/OFF

Pull

- UP

Pull

- Dow

n

VDD

VSS

or disabled

(2) Input Pull-Up and Input Pull-Down are differentiated by the PxODR.y bit field.

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AFIO Features/ GPIO Remapping(1/3) To optimize the number of peripherals available for the 64-pin or the 100-pin

or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, In this case, the alternate functions are no longer mapped to their original assignations.

Note: For more details please refer to “Product Datasheet STM32F100x468B-B”

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AFIO Features/ GPIO Remapping(2/3) Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register (AFIO_MAPR). Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the GP IOs function.

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AFIO Features/ GPIO Remapping(3/3) Using Debug pins:

To optimize the number of free GPIOs during debugging, this mapping can be configured indifferent ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR).

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EXTI Features• Up to 19 Interrupt/Events requests

Up to 80 GPIOs can be used as EXTI line(0..15)

EXTI line 16 connected to PVD output EXTI line 17 connected to RTC Alarm

event EXTI line 18 connected to USB Wake-up

from suspend event

• Independent trigger (rising, falling, rising & falling) and mask on each interrupt/event line

• Dedicated status bit for each interrupt line

• Generation of up to 19 software interrupt/event requests

• Two Configuration mode: Interrupt mode: generate interrupts with

external lines edges Event mode: generate pulse to wake-up

system from SLEEP and STOP modes

• EXTI mapped on High Speed APB (APB2) to save time entering in the External Interrupt routine

EXTI

[15:

0]

Interrupt Mask Register

Pending Request Register

Software InterruptEvent Register

Rising Trigger Selection Register

To NVICEdge Detect

Circuit

Pulse Generator

Falling Trigger Selection Register

Event Mask Register

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EXTI Features

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Now you are able to…

Develop your application on STM32F100 device using GPIO and EXTI

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Thank you