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A Loss-Mitigating Scheme for DC/Pulsating-DCConverter of a High-Frequency-Link System

1

2

Liang Jia and Sudip K. Mazumder, Sr., Senior Member, IEEE3

Abstract—This paper outlines a soft-switching scheme based4on zero-current-switching (ZCS) principle with extended range5for the front-end isolated dc/pulsating-dc converter of an isolated6three-phase rectifier-type high-frequency-link power converter.7General modulation methodology and optimization conditions are8presented, and with the help of linear programming, the opti-9mum solution for a particular objective function can be achieved10to implement the proposed ZCS scheme. In conjunction with11a back-end ac/ac converter operating with a novel patent-filed12hybrid modulation scheme [1], [2], which reduces the number13of hard-switched commutation per switching cycle, the proposed14ZCS scheme can also realize zero-voltage-switching on secondary-15side rectifier to improve the overall efficiency further. With the16nonzero pulsating-dc output, the proposed ZCS scheme is effective17even without an active-clamp circuit, and it is suitable for applica-18tions where low-voltage dc to high-voltage three-phase ac power19conversion is required.20

Index Terms—High-frequency link, isolated three-phase con-21verter, power conversion, pulsating-dc, zero-current switching22(ZCS).23

I. INTRODUCTION24

THE need for realizing power-dense compact power-25

conversion systems (e.g., shown in Fig. 1) that sup-26

port bidirectional power flow is an important factor for Navy27

and Defense from the standpoints of reduced-footprint-space,28

weight, labor cost, and mobility. The existing megawatt-class29

converters typically operate at low switching frequency due to30

the limited turn on/off performances of the high-voltage power31

semiconductor devices resulting in bulky and costly magnetic32

materials and filters. An overview of such topologies is pro-33

vided in [3], [4]. The development of fast power semiconductor34

devices and advanced magnetics (e.g., SiC power devices [5]–35

[7] and nanocrystalline transformers [8]) yield the possibility36

of efficient high-frequency compact power-conversion systems37

[9]–[12]. However, such systems are expected to encounter38

Manuscript received July 5, 2010; revised October 12, 2010, December 8,2010 and February 13, 2011; accepted March 16, 2011. This work wassupported in part by the U.S. National Science Foundation (NSF), receivedby Prof. S. K. Mazumder. However, any opinions, findings, conclusions,or recommendations expressed herein are those of the authors and do notnecessarily reflect the views of the NSF.

L. Jia is with the Philips, Rosemont, IL 60018 USA (e-mail: liang.jia@queensu.ca).

S. K. Mazumder, Sr. is with the Laboratory for Energy and Switching-Electronics Systems and also with the Department of Electrical and ComputerEngineering of the University of Illinois at Chicago, Chicago, IL 60607 USA(e-mail: mazumder@uic.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2181130

enhanced electromagnetic emission and interference, switching 39

loss, and device stresses [13]. The origin of these problems 40

can be traced back to the switching dynamics of the power 41

semiconductor devices. For instance, the three-phase rectifier- 42

type high-frequency-link (RHFL) converter (shown in Fig. 1), 43

which comprises two full-bridge converters (Bridges I and II) 44

followed by an ac/ac converter (Bridge III), yields a compact 45

system owing to high-frequency operation, but may suffer 46

from additional switching losses because of three-stage high- 47

frequency operation. To address this issue, several approaches, 48

based on square-wave and continuous-sine-wave modulations 49

have been proposed [10], [11], [14]–[16]. In [10], an active- 50

snubber-based soft-switching scheme for Bridges I and II is 51

proposed that is applicable for single as well as higher number 52

of phases. However, an additional power semiconductor and 53

associated circuitry is required. References [14], [15] out- 54

line zero-voltage-zero-current-switching (ZVZCS) and zero- 55

voltage-switching (ZVS) converter for Bridges I and II yielding 56

a dc output instead of a pulsating-dc output for the direct- 57

power-conversion topology in Fig. 1. The ZVZCS scheme for 58

the unidirectional power-flow topology (i.e., Bridge II is a 59

diode rectifier) is based on a varying-width and constant-phase- 60

shift scheme along with forced commutation of the Bridge III 61

converter. The scheme in [15] is based on varying phase-shift 62

modulation. Reference [16] also discusses a similar topology 63

for a dc/dc converter operating using an asymmetrical duty 64

cycle to achieve ZVS. 65

In [11], a varying-phase-shift and constant-width asymmet- 66

rical soft-switching scheme was proposed for the front-end 67

isolated dc/pulsating-dc converter (with a diode-rectifier-based 68

Bridge II) along with a loss-mitigating hybrid-modulation 69

scheme for Bridge III [1], [2]. However, the ZCS range of 70

[11] is limited by the modulation index. In this paper, using an 71

optimization method, an improved symmetrical ZCS scheme 72

(based on variable pulse-width and variable pulse-placement) 73

is outlined to further extend the soft-switching range of [11]. It 74

can be implemented without changing the topology or relying 75

on auxiliary circuits and can be used for power scaling as 76

well. The focus of this paper will be on implementation of this 77

novel soft-switching scheme to reduce the overall switching 78

losses of the front-end dc/pulsating-dc bridges of the RHFL 79

converter. In Section II, the basic principles for this ZCS 80

scheme are outlined. Subsequently, an overview of the oper- 81

ating modes and some unique features of the ZCS scheme 82

are outlined. Section III presents an optimization concept 83

that extends the soft-switching range of the ZCS scheme. Fi- 84

nally, Section IV shows simulation and validating experimental 85

results. 86

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Fig. 1. Topology of the three-phase high-frequency-link (HFL) PWM converter.

II. OPERATING MODES OF THE ZCS SCHEME87

For the power-conversion system shown in Fig. 1, the input88

dc voltage is first converted into three bipolar square-wave volt-89

age waveforms VU, VV, VW by three primary-side full-bridge90

converters operating using sinusoidal pulse-width modulation.91

The pulse width for each of the bipolar output phase voltages is92

fixed while the phase shift between the leading and the lagging93

phases vary to gain the six-pulse-modulated waveform Vrec at94

the output of Bridge II based on the following relation:95

Vrec = Max(VU,VV ,Vw) − Min(VU,VV ,Vw). (1)

In (1), Vrec has a six-pulse-like low-frequency component and96

is modulated using the patented hybrid-modulation scheme [1],97

[2] to activate Bridge III. In doing so, the soft-switching range is98

limited by the modulation index and the reference magnitude.99

Therefore, we extend the scheme in [11] using both variable100

pulse-width and pulse-position modulations. The modified ZCS101

scheme is based on the idea of generating the optimal voltage102

overlaps between the leading and the lagging phases to realize103

zero-current condition. The waveforms corresponding to the104

ZCS scheme are illustrated above in Fig. 2. The current wave-105

forms on the transformer primary side of each phase are shown106

in Fig. 3. Symbols U1T, U2T, V1T, V2T, W1T, and W2T are the107

gate signals for the top switches of Bridge I while the bottom108

switches are controlled in a complementary manner. Symbols109

refW, refU, and refV represent the modulation references to110

realize a six-pulse-modulated nonzero pulsating dc voltage111

Vrec. Symbols VU, VV, and VW represent the phase voltages112

on the primary side of the transformers. Overall, there are113

12 modes of operation, of which Modes 1 through 8 are shown,114

respectively, in Fig. 4(h); Modes 9 through 12 are similar to115

Modes 3 through 6.116

Mode 1 (t0 − t1): During this mode, top switches U2T and117

W1T turn on, which yield, respectively, Vu and Vw equal118

to −Vdc and +Vdc. In addition, switches V1B and V2B119

are also turned on yielding Vv equal to zero. Because the120

other two phases handle the positive and negative currents,121

phase V lies idle.122

Mode 2 (t1 − t2): At t1, V2T turns on and hence VV along123

with VU supply negative voltage to Bridge II. Initially, the124

negative current from the load side flows through DUB 125

and the leakage inductance of the transformer prevents 126

the change and transfer of the current, clamping the diode 127

DVB to turn-on. Consequently, a ZCS turn-on condition is 128

created because iV is equal to zero. This enables V2T to 129

undergo a lossless turn-on transition. 130

Mode 3 (t2 − t3): At t2, U2T turns off and the voltage VU 131

equals zero. The diode DVB handles a negative current 132

that transfers from DUB. As such, U2T undergoes a hard 133

switching in this mode. Further, since VV is already neg- 134

ative, DVB endures zero voltage, which creates a ZVS 135

condition for DVB turn-on. 136

Mode 4 (t3 − t4): During this mode, only phase W supplies 137

positive voltage, and the rest provide zero voltage to the 138

secondary side. Further, V1T turns on under ZCS condi- 139

tion since the antiparallel diode of V1T supports negative 140

current. 141

Mode 5 (t4 − t5): In this interval, U1T switches on, which 142

yields VU equal to +Vdc. Diodes DWT and DVB sup- 143

port positive and negative currents, respectively. Further, 144

following Mode-2 operation, the current iU is set to zero 145

that results in a ZCS turn-on for U1T. 146

Mode 6 (t5 − t6): In this mode, W2T turns on under ZCS. U1T 147

starts picking up the positive current while V2T continues 148

to handle the negative portion of the current. Further, 149

because VU continues to be positive and DUT endures zero 150

voltage, ZVS of DVB is ensured. 151

Mode 7 (t6 − t7): At t6, W1T turns off, W2T begins to handle 152

negative current, and the antiparallel diode of W1T handles 153

the negative current during the transition. Hence, W1T 154

undergoes a ZCS turn-off in this interval. Clearly, Mode 7 155

is similar to Mode 1. Further, following the same principle, 156

one can deduct that DWB undergoes a ZVS on. 157

Mode 8 (t7 − t8): Mode 8 is similar to Mode 2. In this mode, 158

V2T is off, and diodes DUT and DWB handle positive and 159

negative currents on the secondary side. Although VV is 160

positive (and equals +Vdc), the current flowing through 161

V1T is zero, which enables a ZCS turn- off for V2T. 162

Mode 9 (t8 − t9), Mode 10 (t9 − t10), Mode 11 (t10 − t11), 163

and Mode 12 (t11 − t12): These modes are similar to 164

Modes 3, 4, 5, and 6, respectively. 165

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 3

Fig. 2. Critical waveforms of the proposed ZCS scheme.

Fig. 3. Current waveforms on the transformer primary-side corresponding to each phase.

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4 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Fig. 4. (a)–(e) Modes of operation corresponding to the ZCS scheme.

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 5

Fig. 4. (Continued). (f)–(h) Modes of operation corresponding to the ZCS scheme.

Fig. 5. Definitions of modulation parameters.

III. OPTIMIZATION FOR EXTENDED ZCS RANGE166

As shown in Fig. 5, in every switching cycle, voltage VU,167

VV, and VW have pulse widths denoted by αi(t) and the phase168

difference between VU and VV or VV and VW is denoted by169

βi(t). These phase voltages are six-pulse modulated using the170

reference ref6(t) as defined by171

ref6(t) =

w(t) − v(t) P1 : −π/6 ≤ ωt < π/6u(t) − v(t) P2 : π/6 ≤ ωt < 3π/6u(t) − w(t) P3 : 3π/6 ≤ ωt < 5π/6v(t) − w(t) P4 : 5π/6 ≤ ωt < 7π/6v(t) − u(t) P5 : 7π/6 ≤ ωt < 9π/6w(t) − u(t) P6 : 9π/6 ≤ ωt < 11π/6

. (2)

The obtained Vrec on the secondary side has only two voltage 172

levels: 2 · N · Vdc and N · Vdc but no zero level. The length of 173

N · Vdc denoted as γ(t). Note that Vrec equals N · Vdc only if 174

two of three voltages Vu, Vv, and Vw are equal to zero and the 175

rest is Vdc or −Vdc. This scheme can achieve ZCS for all the 176

three full-bridges in Bridge I. To achieve the ZCS condition, 177

the output voltages on the primary side should have overlaps, 178

which can help the current of the leading phase leg in Bridge I 179

keep on flowing in place of the lagging phase leg. Further, 180

in order to get the N · Vdc portion in the output voltage of 181

Vrec, additional constraint should be satisfied. Guided by this 182

background and following Fig. 5, the mathematical inequality 183

and equality constraints involving αi(t), βi(t), and ref6(t) (by 184

normalizing the carrier period to 1) are given by the following: 185

− α1 + β1 < 0− α2 + β2 < 0α3 + β1 + β2 < 2α1 − β1 − β2 < 0α2 − α3 − β2 < 0− β1 − β2 < −10 < αi < 1(i = 1, 2, 3)0 < βi < 1(i = 1, 2, 3)α3 + β1 + β2 = 2 ref6. (3)

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6 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Fig. 6. Prototype of the 1-kVA RHFL converter.

The functional relationships in (3) will now be used to solve186

the following “optimization problem” (in a linear programming187

optimization format [17]) to obtain the maximum overlap range188

for ZCS condition:189

minx

(−fTx

)= min(−α1 − α2 + β1 + β2) (4)

subject to the inequality and equality constraints190

Ax < b

Aeq · x = beq. (5)

It is noted that (5) is the condensed version of (3). That is,191

A=

−1 0 0 1 00 −1 0 0 10 0 1 1 11 0 0 −1 −10 1 −1 0 −10 0 0 −1 −1

and b=

00200−1

(6)

and Aeq · x = beq represents α3 + β1 + β2 = 2ref6 for satisfy-192

ing the six-pulse modulation.193

IV. RESULTS194

A 1-kVA RHFL-converter prototype (shown in Fig. 6) is195

designed to validate the proposed soft-switching scheme. The196

input voltage is 36-V dc, and the rated output voltage is 208-V197

ac (line to line). Switching frequency of Bridges I and III are198

21.6 kHz and 43.2 kHz, respectively. Transformer turns ratio199

is around 1 : 8.4. Components used for the converter are listed200

in Table I.201

By solving the optimal problem outlined in Section III and202

the system parameters, the optimal values for αi(t) and βi(t)203

are obtained using a simple linear programming solver. The204

TABLE IMAIN COMPONENTS USED IN THE PROTOYPE

Fig. 7. Plot of optimal value for parameters using the linear programmingalgorithm (rated at the FPGA clock signal frequency). Parameter γ is obtainedusing redundancy constraint illustrated in Fig. 5.

plot of the solutions is shown in Fig. 7. The parametric values 205

are referenced to a carrier period of 1112, which is determined 206

by dividing the clock frequency of the field programmable 207

gate array (FPGA) by the switching frequency of the Bridge-I 208

converter. The table with the optimal parameters is embedded 209

in the DSK-based controller and is fed to the FPGA along 210

with the modulation references refU, refV, and refW. Fig. 8 211

demonstrates the experimental implementation of the optimiza- 212

tion scheme with regard to the switching pulses U, V, and W. 213

Using the optimal values, the experimental results shown in 214

Fig. 9(c) are obtained showing the effect of the soft switching. 215

In Fig. 9(a), the drain-to-source voltages and the phase U 216

current (with positive and negative current portions, represented 217

by IU+ and IU−, and obtained using math function of the scope) 218

are demonstrated. Clearly, U1T has ZCS turn-on and turn- off, 219

and U2T has ZCS turn-on. In Fig. 9(b) and (c), similar results 220

are shown for phase V and W that demonstrate ZCS for the 221

respective phases. 222

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 7

Fig. 8. Switching voltage pulses for phases U, V, and W.

Fig. 9. Demonstration of the effectiveness of the ZCS conditions for Bridge-Iphases (a) U, (b) V, and (c) W. Positive and negative current portions of currentsof Bridge-I phases U, V, and W are represented by IU+ and IU−, IV+ and IV−,and IW+ and IW−.

Fig. 10. Comparison of experimentally measured efficiency using ZCSscheme (top trace) with and (bottom trace) without optimization.

In Fig. 10, experimentally measured efficiency of the 1-kVA 223

converter prototype using the extended ZCS scheme and its 224

comparative evaluation with the results obtained using scheme 225

outlined in [9] and a hard-switched scheme for Bridge I is 226

demonstrated. For all of these cases, Bridge III operates using 227

the hybrid modulation scheme [1], [3]. 228

V. SUMMARY AND CONCLUSION 229

An improved ZCS for the front-end dc/pulsating-dc converter 230

of an isolated three-phase RHFL power converter has been 231

outlined. It can be implemented without relying on auxiliary 232

circuits and can be used for power scaling as well. The ex- 233

tension in the range of the ZCS is achieved by modulating 234

not only the width of the switching pulses but also their 235

placement. The condition for optimality is achieved by solving 236

a simple optimization problem using linear programming. An 237

experimental prototype of the multiphase inverter is developed, 238

and the experimental results demonstrate the soft-switching 239

results and improvement in efficiency as compared to a related 240

benchmark scheme that does not exploit the pulse-placement 241

aspect of the scheme outlined in this paper. 242

REFERENCES 243

[1] S. K. Mazumder and R. Huang, “Multiphase converter apparatus and 244method,” USPTO Patent 7 768 800 B2, Aug 3, 2010. 245

[2] S. K. Mazumder, “A novel hybrid modulation scheme for an isolated high- 246frequency-link fuel cell inverter,” in Proc. IEEE Power Eng. Soc. Conf., 2472008, pp. 1–7. 248

[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, 249J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial 250applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, 251no. 8, pp. 2553–2580, Aug. 2010. 252

[4] S. K. Mazumder, “Hybrid modulation based scalable high-frequency-link 253power-conversion mechanisms,” in Proc. IEEE Ind. Electron. Conf., 2008, 254pp. 435–441. 255

[5] M. K. Das, B. A. Hull, and J. T. Richmond, “Ultra high power 10 kV, 25650 A, SiC PiN diodes,” in Proc. 17th Int. Symp. Power Semicond. Devices 257IC’s, Santa Barbara, CA, May 23–26, 2005, pp. 299–302. 258

[6] S. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, and 259A. Hefner, “10 kV, 5A 4H-SiC power DMOSFET,” in Proc. 18th Int. Symp. 260Power Semicond. Devices IC’s, Naples, Italy, Jun. 4–8, 2006, pp. 1–4. 261

[7] T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, “Optimization of on- 262state and switching performances for 15–20-kV 4H-SiC IGBTs,” IEEE 263Trans. Electron Devices, vol. 55, no. 8, pp. 1920–1927, Aug. 2008. 264

[8] W. A. Reass, J. D. Doss, and R. F. Gribble, “A 1 megawatt polyphase 265boost converter-modulator for klystron pulse application,” in Proc. Pulsed 266Power Plasma Sci., 2001, pp. 250–253. 267

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[9] J. Biela, D. Aggeler, S. Inoue, H. Akagi, and J. W. Kolar, “Bi-directional268isolated DC-DC converter for next-generation power distribution—269Comparison of converters using Si and SiC devices,” IEEJ Trans.,270vol. 128-D, no. 7, pp. 1–10, 2008.271

[10] R. Huang and S. K. Mazumder, “A soft-switching scheme for an isolated272dc/dc converter with pulsating dc output for a three-phase high-frequency-273link PWM converter,” IEEE Trans. Power Electron., vol. 24, no. 10,274pp. 2276–2288, Oct. 2009.275

[11] R. Huang and S. K. Mazumder, “A soft switching scheme for multiphase276dc/pulsating-dc converter for three-phase high-frequency-link PWM in-277verter,” IEEE Trans. Power Electron., vol. 25, no. 7, pp. 1761–1774,278Jul. 2010.279

[12] S. K. Mazumder, R. Burra, R. Huang, M. Tahir, K. Acharya, G. Garcia,280S. Pro, O. Rodrigues, and E. Duheric, “A high-efficiency universal grid-281connected fuel-cell inverter for residential application,” IEEE Trans. Ind.282Electron., vol. 57, no. 10, pp. 3431–3447, Oct. 2010.283

[13] S. K. Mazumder and T. Sarkar, “Optically-activated gate control for power284electronics,” IEEE Trans. Power Electron., vol. 26, no. 10, pp. 2863–2886,285Oct. 2011.286

[14] J. Arrillaga, Y. H. Liu, N. R. Watson, and N. J. Murray, Self-Commutating287Converters for High Power Applications. Singapore: Wiley, 2009.288

[15] C. Liu and A. Johnson, “A novel three-phase high-power soft-switched289DC/DC converter for low-voltage fuel cell applications,” IEEE Trans. Ind.290Appl., vol. 41, no. 6, pp. 1691–1697, Nov./Dec. 2005.291

[16] D. S. Oliveira, Jr. and I. Barbi, “A three-phase ZVS PWM dc/dc converter292with asymmetrical duty cycle for high power applications,” IEEE Trans.293Power Electron., vol. 20, no. 2, pp. 370–377, Mar. 2005.294

[17] A. Ruszczynski, Nonlinear Optimization. Princeton, NJ: Princeton Univ.295Press, 2006.296

Liang Jia received the M.A.Sc. degree in electrical 297engineering from the Queen’s University, Kingston, 298ON, Canada, in 2011. He was a Doctoral student 299in the Department of Electrical and Computer En- 300gineering at the University of Illinois, Chicago, be- 301tween 2008 and 2009. 302

Currently, he serves as a Design Engineer at 303Philips, Chicago, IL. 304

Sudip K. Mazumder, Sr. (SM’03) received the 305M.S. degree in electrical power engineering from 306the Rensselaer Polytechnic Institute, Troy, NY, in 3071993 and the Ph.D. degree in electrical and computer 308engineering from the Virginia Polytechnic Institute 309and State University, Blacksburg, in 2001. 310

At the University of Illinois, Chicago, he is cur- 311rently the Director of the Laboratory for Energy and 312Switching Electronics Systems and a Professor at the 313Department of Electrical and Computer Engineering. 314

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AUTHOR QUERY

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1

A Loss-Mitigating Scheme for DC/Pulsating-DCConverter of a High-Frequency-Link System

1

2

Liang Jia and Sudip K. Mazumder, Sr., Senior Member, IEEE3

Abstract—This paper outlines a soft-switching scheme based4on zero-current-switching (ZCS) principle with extended range5for the front-end isolated dc/pulsating-dc converter of an isolated6three-phase rectifier-type high-frequency-link power converter.7General modulation methodology and optimization conditions are8presented, and with the help of linear programming, the opti-9mum solution for a particular objective function can be achieved10to implement the proposed ZCS scheme. In conjunction with11a back-end ac/ac converter operating with a novel patent-filed12hybrid modulation scheme [1], [2], which reduces the number13of hard-switched commutation per switching cycle, the proposed14ZCS scheme can also realize zero-voltage-switching on secondary-15side rectifier to improve the overall efficiency further. With the16nonzero pulsating-dc output, the proposed ZCS scheme is effective17even without an active-clamp circuit, and it is suitable for applica-18tions where low-voltage dc to high-voltage three-phase ac power19conversion is required.20

Index Terms—High-frequency link, isolated three-phase con-21verter, power conversion, pulsating-dc, zero-current switching22(ZCS).23

I. INTRODUCTION24

THE need for realizing power-dense compact power-25

conversion systems (e.g., shown in Fig. 1) that sup-26

port bidirectional power flow is an important factor for Navy27

and Defense from the standpoints of reduced-footprint-space,28

weight, labor cost, and mobility. The existing megawatt-class29

converters typically operate at low switching frequency due to30

the limited turn on/off performances of the high-voltage power31

semiconductor devices resulting in bulky and costly magnetic32

materials and filters. An overview of such topologies is pro-33

vided in [3], [4]. The development of fast power semiconductor34

devices and advanced magnetics (e.g., SiC power devices [5]–35

[7] and nanocrystalline transformers [8]) yield the possibility36

of efficient high-frequency compact power-conversion systems37

[9]–[12]. However, such systems are expected to encounter38

Manuscript received July 5, 2010; revised October 12, 2010, December 8,2010 and February 13, 2011; accepted March 16, 2011. This work wassupported in part by the U.S. National Science Foundation (NSF), receivedby Prof. S. K. Mazumder. However, any opinions, findings, conclusions,or recommendations expressed herein are those of the authors and do notnecessarily reflect the views of the NSF.

L. Jia is with the Philips, Rosemont, IL 60018 USA (e-mail: liang.jia@queensu.ca).

S. K. Mazumder, Sr. is with the Laboratory for Energy and Switching-Electronics Systems and also with the Department of Electrical and ComputerEngineering of the University of Illinois at Chicago, Chicago, IL 60607 USA(e-mail: mazumder@uic.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2181130

enhanced electromagnetic emission and interference, switching 39

loss, and device stresses [13]. The origin of these problems 40

can be traced back to the switching dynamics of the power 41

semiconductor devices. For instance, the three-phase rectifier- 42

type high-frequency-link (RHFL) converter (shown in Fig. 1), 43

which comprises two full-bridge converters (Bridges I and II) 44

followed by an ac/ac converter (Bridge III), yields a compact 45

system owing to high-frequency operation, but may suffer 46

from additional switching losses because of three-stage high- 47

frequency operation. To address this issue, several approaches, 48

based on square-wave and continuous-sine-wave modulations 49

have been proposed [10], [11], [14]–[16]. In [10], an active- 50

snubber-based soft-switching scheme for Bridges I and II is 51

proposed that is applicable for single as well as higher number 52

of phases. However, an additional power semiconductor and 53

associated circuitry is required. References [14], [15] out- 54

line zero-voltage-zero-current-switching (ZVZCS) and zero- 55

voltage-switching (ZVS) converter for Bridges I and II yielding 56

a dc output instead of a pulsating-dc output for the direct- 57

power-conversion topology in Fig. 1. The ZVZCS scheme for 58

the unidirectional power-flow topology (i.e., Bridge II is a 59

diode rectifier) is based on a varying-width and constant-phase- 60

shift scheme along with forced commutation of the Bridge III 61

converter. The scheme in [15] is based on varying phase-shift 62

modulation. Reference [16] also discusses a similar topology 63

for a dc/dc converter operating using an asymmetrical duty 64

cycle to achieve ZVS. 65

In [11], a varying-phase-shift and constant-width asymmet- 66

rical soft-switching scheme was proposed for the front-end 67

isolated dc/pulsating-dc converter (with a diode-rectifier-based 68

Bridge II) along with a loss-mitigating hybrid-modulation 69

scheme for Bridge III [1], [2]. However, the ZCS range of 70

[11] is limited by the modulation index. In this paper, using an 71

optimization method, an improved symmetrical ZCS scheme 72

(based on variable pulse-width and variable pulse-placement) 73

is outlined to further extend the soft-switching range of [11]. It 74

can be implemented without changing the topology or relying 75

on auxiliary circuits and can be used for power scaling as 76

well. The focus of this paper will be on implementation of this 77

novel soft-switching scheme to reduce the overall switching 78

losses of the front-end dc/pulsating-dc bridges of the RHFL 79

converter. In Section II, the basic principles for this ZCS 80

scheme are outlined. Subsequently, an overview of the oper- 81

ating modes and some unique features of the ZCS scheme 82

are outlined. Section III presents an optimization concept 83

that extends the soft-switching range of the ZCS scheme. Fi- 84

nally, Section IV shows simulation and validating experimental 85

results. 86

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Fig. 1. Topology of the three-phase high-frequency-link (HFL) PWM converter.

II. OPERATING MODES OF THE ZCS SCHEME87

For the power-conversion system shown in Fig. 1, the input88

dc voltage is first converted into three bipolar square-wave volt-89

age waveforms VU, VV, VW by three primary-side full-bridge90

converters operating using sinusoidal pulse-width modulation.91

The pulse width for each of the bipolar output phase voltages is92

fixed while the phase shift between the leading and the lagging93

phases vary to gain the six-pulse-modulated waveform Vrec at94

the output of Bridge II based on the following relation:95

Vrec = Max(VU,VV ,Vw) − Min(VU,VV ,Vw). (1)

In (1), Vrec has a six-pulse-like low-frequency component and96

is modulated using the patented hybrid-modulation scheme [1],97

[2] to activate Bridge III. In doing so, the soft-switching range is98

limited by the modulation index and the reference magnitude.99

Therefore, we extend the scheme in [11] using both variable100

pulse-width and pulse-position modulations. The modified ZCS101

scheme is based on the idea of generating the optimal voltage102

overlaps between the leading and the lagging phases to realize103

zero-current condition. The waveforms corresponding to the104

ZCS scheme are illustrated above in Fig. 2. The current wave-105

forms on the transformer primary side of each phase are shown106

in Fig. 3. Symbols U1T, U2T, V1T, V2T, W1T, and W2T are the107

gate signals for the top switches of Bridge I while the bottom108

switches are controlled in a complementary manner. Symbols109

refW, refU, and refV represent the modulation references to110

realize a six-pulse-modulated nonzero pulsating dc voltage111

Vrec. Symbols VU, VV, and VW represent the phase voltages112

on the primary side of the transformers. Overall, there are113

12 modes of operation, of which Modes 1 through 8 are shown,114

respectively, in Fig. 4(h); Modes 9 through 12 are similar to115

Modes 3 through 6.116

Mode 1 (t0 − t1): During this mode, top switches U2T and117

W1T turn on, which yield, respectively, Vu and Vw equal118

to −Vdc and +Vdc. In addition, switches V1B and V2B119

are also turned on yielding Vv equal to zero. Because the120

other two phases handle the positive and negative currents,121

phase V lies idle.122

Mode 2 (t1 − t2): At t1, V2T turns on and hence VV along123

with VU supply negative voltage to Bridge II. Initially, the124

negative current from the load side flows through DUB 125

and the leakage inductance of the transformer prevents 126

the change and transfer of the current, clamping the diode 127

DVB to turn-on. Consequently, a ZCS turn-on condition is 128

created because iV is equal to zero. This enables V2T to 129

undergo a lossless turn-on transition. 130

Mode 3 (t2 − t3): At t2, U2T turns off and the voltage VU 131

equals zero. The diode DVB handles a negative current 132

that transfers from DUB. As such, U2T undergoes a hard 133

switching in this mode. Further, since VV is already neg- 134

ative, DVB endures zero voltage, which creates a ZVS 135

condition for DVB turn-on. 136

Mode 4 (t3 − t4): During this mode, only phase W supplies 137

positive voltage, and the rest provide zero voltage to the 138

secondary side. Further, V1T turns on under ZCS condi- 139

tion since the antiparallel diode of V1T supports negative 140

current. 141

Mode 5 (t4 − t5): In this interval, U1T switches on, which 142

yields VU equal to +Vdc. Diodes DWT and DVB sup- 143

port positive and negative currents, respectively. Further, 144

following Mode-2 operation, the current iU is set to zero 145

that results in a ZCS turn-on for U1T. 146

Mode 6 (t5 − t6): In this mode, W2T turns on under ZCS. U1T 147

starts picking up the positive current while V2T continues 148

to handle the negative portion of the current. Further, 149

because VU continues to be positive and DUT endures zero 150

voltage, ZVS of DVB is ensured. 151

Mode 7 (t6 − t7): At t6, W1T turns off, W2T begins to handle 152

negative current, and the antiparallel diode of W1T handles 153

the negative current during the transition. Hence, W1T 154

undergoes a ZCS turn-off in this interval. Clearly, Mode 7 155

is similar to Mode 1. Further, following the same principle, 156

one can deduct that DWB undergoes a ZVS on. 157

Mode 8 (t7 − t8): Mode 8 is similar to Mode 2. In this mode, 158

V2T is off, and diodes DUT and DWB handle positive and 159

negative currents on the secondary side. Although VV is 160

positive (and equals +Vdc), the current flowing through 161

V1T is zero, which enables a ZCS turn- off for V2T. 162

Mode 9 (t8 − t9), Mode 10 (t9 − t10), Mode 11 (t10 − t11), 163

and Mode 12 (t11 − t12): These modes are similar to 164

Modes 3, 4, 5, and 6, respectively. 165

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 3

Fig. 2. Critical waveforms of the proposed ZCS scheme.

Fig. 3. Current waveforms on the transformer primary-side corresponding to each phase.

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Fig. 4. (a)–(e) Modes of operation corresponding to the ZCS scheme.

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 5

Fig. 4. (Continued). (f)–(h) Modes of operation corresponding to the ZCS scheme.

Fig. 5. Definitions of modulation parameters.

III. OPTIMIZATION FOR EXTENDED ZCS RANGE166

As shown in Fig. 5, in every switching cycle, voltage VU,167

VV, and VW have pulse widths denoted by αi(t) and the phase168

difference between VU and VV or VV and VW is denoted by169

βi(t). These phase voltages are six-pulse modulated using the170

reference ref6(t) as defined by171

ref6(t) =

w(t) − v(t) P1 : −π/6 ≤ ωt < π/6u(t) − v(t) P2 : π/6 ≤ ωt < 3π/6u(t) − w(t) P3 : 3π/6 ≤ ωt < 5π/6v(t) − w(t) P4 : 5π/6 ≤ ωt < 7π/6v(t) − u(t) P5 : 7π/6 ≤ ωt < 9π/6w(t) − u(t) P6 : 9π/6 ≤ ωt < 11π/6

. (2)

The obtained Vrec on the secondary side has only two voltage 172

levels: 2 · N · Vdc and N · Vdc but no zero level. The length of 173

N · Vdc denoted as γ(t). Note that Vrec equals N · Vdc only if 174

two of three voltages Vu, Vv, and Vw are equal to zero and the 175

rest is Vdc or −Vdc. This scheme can achieve ZCS for all the 176

three full-bridges in Bridge I. To achieve the ZCS condition, 177

the output voltages on the primary side should have overlaps, 178

which can help the current of the leading phase leg in Bridge I 179

keep on flowing in place of the lagging phase leg. Further, 180

in order to get the N · Vdc portion in the output voltage of 181

Vrec, additional constraint should be satisfied. Guided by this 182

background and following Fig. 5, the mathematical inequality 183

and equality constraints involving αi(t), βi(t), and ref6(t) (by 184

normalizing the carrier period to 1) are given by the following: 185

− α1 + β1 < 0− α2 + β2 < 0α3 + β1 + β2 < 2α1 − β1 − β2 < 0α2 − α3 − β2 < 0− β1 − β2 < −10 < αi < 1(i = 1, 2, 3)0 < βi < 1(i = 1, 2, 3)α3 + β1 + β2 = 2 ref6. (3)

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Fig. 6. Prototype of the 1-kVA RHFL converter.

The functional relationships in (3) will now be used to solve186

the following “optimization problem” (in a linear programming187

optimization format [17]) to obtain the maximum overlap range188

for ZCS condition:189

minx

(−fTx

)= min(−α1 − α2 + β1 + β2) (4)

subject to the inequality and equality constraints190

Ax < b

Aeq · x = beq. (5)

It is noted that (5) is the condensed version of (3). That is,191

A=

−1 0 0 1 00 −1 0 0 10 0 1 1 11 0 0 −1 −10 1 −1 0 −10 0 0 −1 −1

and b=

00200−1

(6)

and Aeq · x = beq represents α3 + β1 + β2 = 2ref6 for satisfy-192

ing the six-pulse modulation.193

IV. RESULTS194

A 1-kVA RHFL-converter prototype (shown in Fig. 6) is195

designed to validate the proposed soft-switching scheme. The196

input voltage is 36-V dc, and the rated output voltage is 208-V197

ac (line to line). Switching frequency of Bridges I and III are198

21.6 kHz and 43.2 kHz, respectively. Transformer turns ratio199

is around 1 : 8.4. Components used for the converter are listed200

in Table I.201

By solving the optimal problem outlined in Section III and202

the system parameters, the optimal values for αi(t) and βi(t)203

are obtained using a simple linear programming solver. The204

TABLE IMAIN COMPONENTS USED IN THE PROTOYPE

Fig. 7. Plot of optimal value for parameters using the linear programmingalgorithm (rated at the FPGA clock signal frequency). Parameter γ is obtainedusing redundancy constraint illustrated in Fig. 5.

plot of the solutions is shown in Fig. 7. The parametric values 205

are referenced to a carrier period of 1112, which is determined 206

by dividing the clock frequency of the field programmable 207

gate array (FPGA) by the switching frequency of the Bridge-I 208

converter. The table with the optimal parameters is embedded 209

in the DSK-based controller and is fed to the FPGA along 210

with the modulation references refU, refV, and refW. Fig. 8 211

demonstrates the experimental implementation of the optimiza- 212

tion scheme with regard to the switching pulses U, V, and W. 213

Using the optimal values, the experimental results shown in 214

Fig. 9(c) are obtained showing the effect of the soft switching. 215

In Fig. 9(a), the drain-to-source voltages and the phase U 216

current (with positive and negative current portions, represented 217

by IU+ and IU−, and obtained using math function of the scope) 218

are demonstrated. Clearly, U1T has ZCS turn-on and turn- off, 219

and U2T has ZCS turn-on. In Fig. 9(b) and (c), similar results 220

are shown for phase V and W that demonstrate ZCS for the 221

respective phases. 222

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JIA AND MAZUMDER: LOSS-MITIGATING SCHEME FOR DC/PULSATING-DC CONVERTER OF A HIGH-FREQUENCY-LINK SYSTEM 7

Fig. 8. Switching voltage pulses for phases U, V, and W.

Fig. 9. Demonstration of the effectiveness of the ZCS conditions for Bridge-Iphases (a) U, (b) V, and (c) W. Positive and negative current portions of currentsof Bridge-I phases U, V, and W are represented by IU+ and IU−, IV+ and IV−,and IW+ and IW−.

Fig. 10. Comparison of experimentally measured efficiency using ZCSscheme (top trace) with and (bottom trace) without optimization.

In Fig. 10, experimentally measured efficiency of the 1-kVA 223

converter prototype using the extended ZCS scheme and its 224

comparative evaluation with the results obtained using scheme 225

outlined in [9] and a hard-switched scheme for Bridge I is 226

demonstrated. For all of these cases, Bridge III operates using 227

the hybrid modulation scheme [1], [3]. 228

V. SUMMARY AND CONCLUSION 229

An improved ZCS for the front-end dc/pulsating-dc converter 230

of an isolated three-phase RHFL power converter has been 231

outlined. It can be implemented without relying on auxiliary 232

circuits and can be used for power scaling as well. The ex- 233

tension in the range of the ZCS is achieved by modulating 234

not only the width of the switching pulses but also their 235

placement. The condition for optimality is achieved by solving 236

a simple optimization problem using linear programming. An 237

experimental prototype of the multiphase inverter is developed, 238

and the experimental results demonstrate the soft-switching 239

results and improvement in efficiency as compared to a related 240

benchmark scheme that does not exploit the pulse-placement 241

aspect of the scheme outlined in this paper. 242

REFERENCES 243

[1] S. K. Mazumder and R. Huang, “Multiphase converter apparatus and 244method,” USPTO Patent 7 768 800 B2, Aug 3, 2010. 245

[2] S. K. Mazumder, “A novel hybrid modulation scheme for an isolated high- 246frequency-link fuel cell inverter,” in Proc. IEEE Power Eng. Soc. Conf., 2472008, pp. 1–7. 248

[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, 249J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial 250applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, 251no. 8, pp. 2553–2580, Aug. 2010. 252

[4] S. K. Mazumder, “Hybrid modulation based scalable high-frequency-link 253power-conversion mechanisms,” in Proc. IEEE Ind. Electron. Conf., 2008, 254pp. 435–441. 255

[5] M. K. Das, B. A. Hull, and J. T. Richmond, “Ultra high power 10 kV, 25650 A, SiC PiN diodes,” in Proc. 17th Int. Symp. Power Semicond. Devices 257IC’s, Santa Barbara, CA, May 23–26, 2005, pp. 299–302. 258

[6] S. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, and 259A. Hefner, “10 kV, 5A 4H-SiC power DMOSFET,” in Proc. 18th Int. Symp. 260Power Semicond. Devices IC’s, Naples, Italy, Jun. 4–8, 2006, pp. 1–4. 261

[7] T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, “Optimization of on- 262state and switching performances for 15–20-kV 4H-SiC IGBTs,” IEEE 263Trans. Electron Devices, vol. 55, no. 8, pp. 1920–1927, Aug. 2008. 264

[8] W. A. Reass, J. D. Doss, and R. F. Gribble, “A 1 megawatt polyphase 265boost converter-modulator for klystron pulse application,” in Proc. Pulsed 266Power Plasma Sci., 2001, pp. 250–253. 267

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[9] J. Biela, D. Aggeler, S. Inoue, H. Akagi, and J. W. Kolar, “Bi-directional268isolated DC-DC converter for next-generation power distribution—269Comparison of converters using Si and SiC devices,” IEEJ Trans.,270vol. 128-D, no. 7, pp. 1–10, 2008.271

[10] R. Huang and S. K. Mazumder, “A soft-switching scheme for an isolated272dc/dc converter with pulsating dc output for a three-phase high-frequency-273link PWM converter,” IEEE Trans. Power Electron., vol. 24, no. 10,274pp. 2276–2288, Oct. 2009.275

[11] R. Huang and S. K. Mazumder, “A soft switching scheme for multiphase276dc/pulsating-dc converter for three-phase high-frequency-link PWM in-277verter,” IEEE Trans. Power Electron., vol. 25, no. 7, pp. 1761–1774,278Jul. 2010.279

[12] S. K. Mazumder, R. Burra, R. Huang, M. Tahir, K. Acharya, G. Garcia,280S. Pro, O. Rodrigues, and E. Duheric, “A high-efficiency universal grid-281connected fuel-cell inverter for residential application,” IEEE Trans. Ind.282Electron., vol. 57, no. 10, pp. 3431–3447, Oct. 2010.283

[13] S. K. Mazumder and T. Sarkar, “Optically-activated gate control for power284electronics,” IEEE Trans. Power Electron., vol. 26, no. 10, pp. 2863–2886,285Oct. 2011.286

[14] J. Arrillaga, Y. H. Liu, N. R. Watson, and N. J. Murray, Self-Commutating287Converters for High Power Applications. Singapore: Wiley, 2009.288

[15] C. Liu and A. Johnson, “A novel three-phase high-power soft-switched289DC/DC converter for low-voltage fuel cell applications,” IEEE Trans. Ind.290Appl., vol. 41, no. 6, pp. 1691–1697, Nov./Dec. 2005.291

[16] D. S. Oliveira, Jr. and I. Barbi, “A three-phase ZVS PWM dc/dc converter292with asymmetrical duty cycle for high power applications,” IEEE Trans.293Power Electron., vol. 20, no. 2, pp. 370–377, Mar. 2005.294

[17] A. Ruszczynski, Nonlinear Optimization. Princeton, NJ: Princeton Univ.295Press, 2006.296

Liang Jia received the M.A.Sc. degree in electrical 297engineering from the Queen’s University, Kingston, 298ON, Canada, in 2011. He was a Doctoral student 299in the Department of Electrical and Computer En- 300gineering at the University of Illinois, Chicago, be- 301tween 2008 and 2009. 302

Currently, he serves as a Design Engineer at 303Philips, Chicago, IL. 304

Sudip K. Mazumder, Sr. (SM’03) received the 305M.S. degree in electrical power engineering from 306the Rensselaer Polytechnic Institute, Troy, NY, in 3071993 and the Ph.D. degree in electrical and computer 308engineering from the Virginia Polytechnic Institute 309and State University, Blacksburg, in 2001. 310

At the University of Illinois, Chicago, he is cur- 311rently the Director of the Laboratory for Energy and 312Switching Electronics Systems and a Professor at the 313Department of Electrical and Computer Engineering. 314

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