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10HDL Based Design

In this chapter we show a design done in Verilog and implemented on UP2. We

describe a circuit at the behavioral level and test it with an HDL simulator. Thetested design is then brought into Quartus II and incorporated into a completedesign. The Quartus II compiler synthesizes our behavioral code and generatesa device programming file that contains the synthesized parts as well as othercomponents used in the complete design. The final design is used to programthe MAX device of the UP2 board.

10.1 High Level Description and Simulation

The design that will

be used in this chapter is a sequence detector. After

describing the functionality of this circuit we will describe it in Verilog test oursynthesizable Verilog design with an HDL simulator and ready it for being usedin programming a programmable device. This section describes the design ofthe sequence detector and the next section discusses its preparation for device

programming.

10.1.1 State Machine Description

The core of the design that will be used to program the MAX device of UP2 is asequence detector that detects asequence of1011on its xserial input. Whenthis sequence is detected it generates a complete one clock duration pulse onits zoutput. The machine has a reset input (rst) that forces the machine intoits initial or reset state. The state machine for implementing this design is aMoore machine the state diagram of which is shown in Figure 10.1.

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220 Digital Design and Implementation with Field Programmable Devices

Figure 10.1 Moore 1011 State Diagram

'timescale 1ns/100ps

modulemoore1011 ( x rst clk z );inputx rst clk;outputz;

parameter[2:0] a= 0 b = 1 c = 2 d = 3 e = 4;

reg [2:0] p_state n_state;

always@( p_state or x )begin:combinationalcase( p_state )

a:if( x == 1 ) n_state = b;elsen_state = a;

b:if( x == 0 ) n_state = c;elsen_state = b;

c:if( x == 1 ) n_state = d;elsen_state = a;

d:if( x == 1 ) n_state = e;elsen_state = c;

e:if( x == 1 ) n_state = b;elsen_state = c;

default:

n_state = a;endcase

end

assignz = (p_state == e);

always@(posedgeclk )begin:sequential

if( rst ) p_state = a;elsep_state = n_state;end

endmodule

Figure 10.2 Moore Detector Verilog Code

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10.1.2 Moore Machine Verilog CodeThe synthesizable Verilog code of our Moore machine is shown in Figure 10.2.As shown three concurrent statements describe transitions output andclocking of this machine. The combinational always block describes thetransitions shown in the state diagram of Figure 10.1 while the sequentialalways block describes the clocking of our machine. The other concurrentstatement in this description is an assign statement that is used for assigningvalues to thezoutput of the circuit.

The description shown usesp_state for the present state of the machineandn_statefor its nextstate.Because our machine has fivestatesparameterandregdeclarations are three bits wide.

10.1.3 Moore Machine Verilog Testbench

The testbench of Figure 10.3 is used for testing the Verilog code of Figure 10.2.In this testbench a 19-bit wide buffer holds serial data that are applied to thexinput of the circuit being tested. Two concurrent always blocks in thisdescription produce the circuit clock and simultaneously rotatebufferbits outintox.

'timescale1ns/100ps

moduletest_moore1011;regx,rst, clk;wirez;reg[18:0] buffer;

moore1011 uut( x, rst, clk, z );

initial buffer = 19'b0001101101111001001;

initial beginclk = 0;x = 0; rst = 1;#29 rst = 0;#500$stop;

endalways@(posedgeclk) #1 {x, buffer} = {buffer, x};always#5 clk = ~clk;

endmodule

Figure 10.3 Moore Detector Testbench

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10.1.4 Behavioral Simulation

The Moore1011.v(Figure 10.2) design description file and its testbench,

Moore1011Tester.v (Figure 10.3) are simulated in a ModelSim 5.7c project. Thesimulation run waveform is shown in Figure 10.4.

The present state of the machine (p_state) is displayed in the waveformshown. The output of the machine becomes 1 when p_state is 100 thatcorrespond to stateeof our Moore machine.

10.2 Design Implementation

This section discusses how Quartus II environment is used for hardware

implementation of the Moore design of the previous section. Steps involved inthis implementation include project creation in Quartus II. generation of properinterfaces for our tested description of Moore machine porting or adapting theVerilog code of our design to the Quartus II environment design compilationand device programming. After completion of these steps using UP2

pushbuttons and LEDs our UP2 prototype will be able to verify waveformsshown in Figure 10.4.

Figure 10.4 Moore Machine Simulation Run (Partial View)

10.2.1 Project Definition

The Quartus II project for harware implementation of our Moore machine isDetector. This project uses ourBookLibraryas its pre-defined user library. Auser library can either be specified during creation of a project or in theSettingswindow after a project is created. To add a user library in the Settingswindowopen theAssignmentspull-down menu from the Quartus II main window andselectSettings. When the Settingswindow opens underFiles&Directoriesclick onUserLibrariesto set your libraries.

10.2.2 Symbol Generation from Verilog Code

In order to be able to use our tested Verilog code of Figure 10.2 in Quartus asymbol has to be created for it. The generated symbol becomes available in theProjectlibrary and can be used like any other symbol is a block diagram.

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For generating a symbol forMoore1011module of Figure 10.2, copy itscode to the directory of the Quartus II Detectorproject. Then open this fileusing Quartus II text editor (File Openand select Moore1011.v to open it).While this file is open open theFilepull-down menu and follow links to createsymbol for the current file. As with other symbols we can edit the symbol thatis so generated. The edited symbol for ourMoore1011Verilog code is shownFigure 10.5.

10.2.3 Schematic Entry

The schematic file for Quartus II Detector project is Detector.bdf. In thisschematic themoore1011 symbol of Figure 10.5 its necessary interfaces forUP2 resources and the Detector pins are entered and proper interconnectionsmade. Components fromBookLibraryare used for interfacing pushbuttons ofUP2 to the inputs of moore1011 circuit. Figure 10.6 shows the completeschematic of theDetectorcircuit for programming a UP2 device.

Figure 10.5 Moore Detector Symbol

Figure 10.6 Detector System Description

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After the completion of design entry phase the design is compiled inQuartus II. This phase synthesizes the Verilog parts of the design and pulls

together other cell-based and gate-level parts into a complete deviceprogramming file.

10.2.4 Compilation and Synthesis

By compiling the design of Figure 10.6 it is synthesized and properprogramming files are created for it. In addition various timing and floorplanviews become available. For the moore1011 component a portion of its RTLview that is its post-synthesis netlist is shown in Figure 10.7. This netlist isgenerated for the FLEX 10K device being used as the synthesis target. Thisschematic shows the use of three flip-flops for implementing states of ourdetector circuit. AND-OR logic is used for flip-flop inputs.

Figure 10.7 RTL View ofmoore1011

10.2.5 Device Programming and Testing

As previously discussed either of the two UP2 devices can be programmed withthe hardware of Figure 10.6. We have chosen the EPM7128S device for this

design and Table 10.1 shows its corresponding pin settings. Pin numbers arealso shown in Figure 10.6 in block IO tables. The complete design ofDetectorincluding moore1011 and its pushbutton interfaces uses 34 of the 128macrocells of the EPM7128S device.

For testing the design the input and the clock are connected to UP2pushbuttons and the circuit reset is connected to a UP2 switch. Use of apushbutton for the clock allows manual slow operation of the circuit and thus

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pushbuttons are debounced by usingPulser2 from our BookLibrary. Thedebounced PB2 is put into OnePulser so that with each release of the

pushbutton a positive pulse is generated. This output provides the clock signalformoore1011. The other debounced output ofPulser2 that corresponds to PB1is directly connected to the Moore machinesXininput (this is a level input).The circuit operates when its reset input switch is in the off position (SW1 mustbe down).

To test the circuit hold down both pushbuttons and release and push PB2several times to make sure the machine is in its initial state. Then release PB1(this puts a 1 onXin) and release and push PB2 to clock the circuit. Repeatthis process for clocking a 0 and then two 1s into the circuit through itsXin

input. With the release of PB2 (rising edge of the clock) the a-segment ofSSD1 ofMAX turnoff which means that Zouthasbecome1.Since the circuit is clocked and allXinvalues are taken on the edge ofClk,

we could test the circuit without using a debouncer for PB1 (theXin input).

10.3 Summary

This chapter used a state machine example to demonstrate how a behavioralVerilog that is synthesizable could be used in a design and after synthesis

incorporated with the other components of the design. We showed theprocedure for simulating our behavioral design outside of Quartus II and afterverifying itbringing it into Quartus II.

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