Front-End Buck Rectifier With Reduced Filter Size and Single-Loop Control

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 10, OCTOBER 2013 4359

Front-End Buck Rectifier With Reduced Filter Sizeand Single-Loop Control

Poonam Chaudhary and Parthasarathi Sensarma, Member, IEEE

Abstract—This paper presents a transformerless solution forfront-end rectification, which is particularly suitable for tractionapplications, requiring high voltages to be stepped down to appro-priate dc voltage. The proposed topology is based on pulsewidth-modulation buck rectifier (current source inverter topology) andis capable of rectification and stepping down of single-phase acsupply, in a single stage. A new control scheme is proposed toachieve constant dc output voltage and sinusoidal source current,irrespective of large ripples in the dc inductor current. The pro-posed scheme is configured in single-loop voltage control mode.The relevant small-signal model is derived from the large-signalmodel using multiorder decomposition. An elaborate procedure ofdc filter design is discussed, for circuit operation with minimumenergy storage. All analytical results are validated by numericalsimulation for sinusoidal and distorted source voltage. Experi-mental verification is achieved through a 1.2-kW grid-connectedlaboratory prototype.

Index Terms—Buck rectifier (BR), single-loop control, singlephase, traction, transformerless.

I. INTRODUCTION

INTERNATIONALLY, the most preferred network suppliesfor ac traction are 50 Hz–25 kV and 60 Hz–25 kV. Some

parts of European railway networks also use 16.7 Hz–15 kV.These high voltages from catenary need to be stepped downand rectified to a suitable dc stage (3 kV–500 V), which eitherdirectly supplies dc motors or constitutes the input stage oftraction inverters [1]. The consequent step-down requirement ismet by a line-frequency (low-frequency) transformer, followedby a rectifier bank. This renders the system bulky and impairsthe overall efficiency. Motivation of a compact and efficienttraction converter guided the research in two directions. Oneperspective proposes the replacement of low-frequency trans-formers by medium-frequency transformers (MFTs) in [2]–[4],and the other introduces transformerless topologies [5]. MFTtopologies are particularly suitable for 16.7 Hz–15 kV (low-frequency) lines, as they offer reduction in the bulk of the linetransformer [4]. However, the bulk reduction is achieved atthe expense of reduced reliability (higher number of switches).Transformerless topologies, as shown in Fig. 1, employ the

Manuscript received May 23, 2012; revised August 18, 2012; acceptedAugust 22, 2012. Date of publication September 19, 2012; date of currentversion May 16, 2013. This work was supported by the research grant underNational Mission for Power Electronics Technology, initiative of the Depart-ment of Information Technology, Government of India.

The authors are with the Department of Electrical Engineering,Indian Institute of Technology Kanpur, Kanpur 208016, India (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2012.2217724

Fig. 1. Series-connected H-bridges for transformerless traction drive.

series connection of H-bridges [voltage source inverter (VSI)or boost-type topology], where each H-bridge powers one ofthe motor drives of the traction system [6].

Considering traction application, buck-rectifier (BR) circuitsoffer an inherent advantage of reduced dc voltage [7], andalso, the use of series-connected BR circuits leads to significantreduction in the number of switching devices assuring higherreliability. For instance, with a 1.5-kV dc link in a 25-kV ac/1.5-kV dc, 5-MVA drive system, 26 modules or 104 switches(3 kV/566 A) are required with boost-type topology. The num-ber of modules reduces to 11 or 44 switches (6.6 kV/606 A),with a buck-type topology, considering identical safety factorin both cases.

Several BR topologies and control strategies for single andthree phases are reported in [8]–[21]. However, single-phaseBR topologies have not received much attention in recent times,due to substantial filtering requirement on the dc side forattenuation of even harmonics (second and higher components)[7]. Even with large filters, even harmonic ripples in dc currentreflect as odd harmonics in the source current. Simultaneousreduction of odd harmonics in the source current and thedc filter size is therefore a major problem challenging thecommercial deployment of this topology. Source current waveshaping is proposed in [19]–[21]. The concept of hysteresis-current-controlled boost-type rectifier is extended to current-source converter in [19]. Single-loop inductor voltage controlis proposed in [20]. However, due to hysteresis control (variableswitching frequency), input filters are slightly larger, sincethey have to be designed for lowest possible steady-stateswitching frequency. Input filter design criterion and constraints

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4360 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 10, OCTOBER 2013

Fig. 2. Basic BR circuit.

for pulsewidth-modulation (PWM) current-source rectifiers arediscussed in [22]. Owing to the high-quality source currentrequirement, for a given switching frequency, there is littlescope of alteration in source filter design. Active modulationtechnique for single-phase grid-connected CSI is proposed in[21]. Design procedure for dc filter is given, assuming thedc current ripple to be very low. However, that assumption isviolated when, for improved power density, the energy storageby dc inductance is desired to be low. Also, this requires theextraction of dc component from the output dc filter currentthrough a low-pass filter, which leads to poor dynamic response.

Considering these problems, a new method of active waveshaping of source current for BR circuit is proposed in thispaper, which ensures sinusoidal near-unity-power-factor (UPF)source current. The control method is capable of maintainingsinusoidal current irrespective of large ripples in dc current,hence facilitating lighter dc filter with reduced energy storage.The proposed control strategy makes the BR topology partic-ularly suitable for traction applications, which demand mini-mal source current distortion and energy storage components.Analytical foundations of dc filter and controller design aredescribed which are validated by simulation and experimentalresults with a 1.2-kW laboratory prototype.

II. CONVENTIONAL BR CIRCUIT

Basic single-phase BR circuit is shown in Fig. 2. Input acvoltage to the single-phase BR circuit is rectified and appliedto a stiff current link, maintained by the dc inductor Ld. Outputcapacitor Cd provides a stiff voltage front end to subsequentstages, which could comprise a direct load or a second power-conversion stage. Absence of a stiff voltage across the converterdc terminals necessitates two-quadrant switches with bidirec-tional voltage blocking capability. This is achieved with theseries combination of a single-quadrant controlled switch (e.g.,IGBT) and a diode for higher switching frequencies. GTOs orIGCTs are used for switching frequencies below 3 kHz. Directconnection to the input ac source causes injection of switchingripple currents, which are attenuated by the input side ripplefilters Ls and Cs.

A. Conventional Switching Strategy

Necessity to maintain continuity of the dc link current idcand to ensure no loss of control allows just two independentswitching functions S1(t) and S2(t) applied to switches S1

and S2 in Fig. 2. These switching functions must satisfy thefollowing rule:

Sj(t) ={1 if ON0 if OFF

, jε[1, 2]. (1)

Sufficient overlap in complementary switching functions en-sures continuity of the dc link current. From the BR circuittopology, input current ist(t) and output voltage vdc(t) arerelated to the dc current idc(t) and ac voltage vac(t) as[

vdc(t)

ist(t)

]= [S1(t)− S2(t)]

[vac(t)

idc(t)

]. (2)

Neglecting the input filter drop at fundamental frequency

vac � vs = Vm sin(ωt). (3)

For ease of filter design in BR, the sine PWM (SPWM) tech-nique is most appropriate. In a canonical SPWM, the switchingfunctions are [23]

Sj(t) = 0.5{1 + (−1)j+1M sin(ωt)

}+ h.f terms, j ∈ {1, 2}

(4)

where M is the modulation index and high-frequency (h.fterms) components comprise multiples of switching frequencyand their sidebands. Presence of an input frequency term in (4)is essential to obtain a nonzero dc output.

B. Harmonics in Source Current

Using (2), (3), and (4), the rectifier output voltage is

vdc(t) = 0.5MVm {1− cos(2ωt)}+ h.f terms

=Vdc0 − Vdc2 cos(2ωt) + h.f terms (5)

where Vdc0 = Vo (load voltage).Consequently, the linear dc filter ensures that idc(t) has both

dc and second harmonic terms. Also, for large values of Ld, theh.f terms are practically absent. Thus

idc(t) = Idc0 − Idc2 sin(2ωt) = Idc0 {1−K sin(2ωt)} (6)

where

Idc0 = Io (load current)

Idc2 � MVm/(4ωLd) (7)

K =Idc2Io

(8)

is the second harmonic ripple factor.Using (2), (4), and (6), the input current is found to be

ist(t) = Is1 sin(ωt− φ) + Is3 cos(3ωt) + h.f terms (9)

where

Is1 = MIdc0

√1 +

(Idc22Idc0

)2

φ = tan−1

(Idc22Idc0

)(10)

Is3 = 0.5MIdc2. (11)

CHAUDHARY AND SENSARMA: FRONT-END BR WITH REDUCED FILTER SIZE AND SINGLE-LOOP CONTROL 4361

Fig. 3. Energy storage requirement for given third harmonic distortion.

C. Filter Requirement With SPWM

Clearly, the second harmonic current magnitude directly de-cides the third harmonic in the source current. It also causes theinput PF to deviate from unity. Hence, with SPWM, the dc filterinductance is principally designed to attenuate the second har-monic current. For a well-designed dc filter, (Idc2/2Idc0)2 �1. Under this condition, from (7), (10), and (11), ratio of thirdharmonic to fundamental components in the input current is

Is3Is1

≈ MVm

(8ωLdIo)(12)

which is stated in terms of output power Po(= VoIo) and energystored by Ld, Es(= LdI

2o/2) as

Is3Is1

≈ Po

(8ωEs). (13)

Energy storage requirement of the inductor is determined bypower rating of the rectifier and harmonic current injectionlimit, as shown in Fig. 3, for 50- and 60-Hz grid frequencies.Requirement of high-quality source current invariably leads tolarge filter volume and, hence, the motivation of the modifiedmodulation strategy.

III. MODIFIED MODULATION STRATEGY

Defining the low-frequency ac components of the switchingfunction as the modulation signal m(t), (4) is expressed asfollows:

Sj(t) = 0.5{1 + (−1)j+1m(t)

}+ h.f terms, j ∈ {1, 2}

(14)

where m(t) is not constrained to have only the grid frequencycomponent. With a well-designed input filter, the source currentis(t) comprises the low-frequency component of the inputcurrent ist(t). From (2), therefore

is(t) = m(t)idc(t). (15)

From (15), it follows that if idc(t) is a current source with valueIdc, then, for a sinusoidal source current is(t), m(t) is requiredto be

m′(t) =Is sin(ωt)

Idc. (16)

Constant dc link current can only be maintained when rectifieroutput voltage vdc is constant, requiring the modulation signalto be given as

m′′(t) =Vdc

{Vm sin(ωt)} =

(Vdc

Vm

)csc(ωt). (17)

From (16) and (17), it is inferred that constant dc link currentand sinusoidal source current cannot be simultaneously realizedthrough a unique switching function. Therefore, a new modula-tion method is suggested, which directly allows control of thesource current, ensuring good waveform quality irrespective ofripples in dc current. For sinusoidal UPF source current

is = Is1 sin(ωt) (18)

the modulation signal m(t) is evaluated as

m(t) =Is1 sin(ωt)

{idc(t)}. (19)

Obviously, the proposed modulation strategy is applicablefor continuous conduction mode. Deviation from (17) indicatesthe unavoidable presence of harmonics in the dc current idcwhich is accordingly generalized as

idc(t) = Io +∑n

[Idcns sin(nωt) + Idcnc cos(nωt)] (20)

where Io is the dc component and is completely decided by theload. From (19), the modulation signal has the form

m(t) =

(Is1Io

)μ(t) sin(ωt) = Mμ(t) sin(ωt) (21)

where

μ(t) =1

1 +∑n

[(IdcnsIo

)sin(nωt) +

(IdcncIo

)cos(nωt)

] . (22)

Since the denominator in (22) is periodic, for continuous con-duction, μ(t) is also periodic with the same frequency. Hence,the harmonic orders in m(t) are ±1 of those in the dc current.A first-order approximation of μ(t) is obviously

μ(t) = 1−∑n

[(IdcnsIo

)sin(nωt) +

∑n

(IdcncIo

)cos(nωt)

]︸︷︷︸

mh(t)

(23)

which is valid only for Idcn � Io and so cannot be assumeda priori. A correction term δm(t) is defined as follows to equateto the exact solution:

μ(t) = μ(t) + δm(t). (24)

The iterative procedure, detailed subsequently, implicitly re-duces δm(t) to a negligible level. Using (24)

vdc(t) = vs(t)m(t)

= vs(t) {M −Mmh(t) +Mδm(t)} sin(ωt)= 0.5MVm+

∑n

[Vdcnccos(nωt)+Vdcnssin(nωt)] (25)


as the source voltage comprises the fundamental, vdc(t) con-tains even harmonics and m(t) comprises odd harmonics. From(19), to ensure linear operation with unit amplitude triangle-carrier modulation, the following must be satisfied:

|is1(t)| ≤ idc(t) ∀t. (26)

Intersection of the two waveforms idc(t) and rectified is(t) isdetermined by the normalized ripple content of idc(t), relativeto the load current Io. For a flat output voltage vo(t), amplitudeof the nth harmonic component in this normalized ripple is

Kns =IdcnsIo

=Vdcnc

nωLdIoand Knc =

IdcncIo

=Vdcns

nωLdIo(27)

where Vdcnc and Vdcns are the amplitudes of the cosine and sineterms of the nth harmonic in vdc(t), respectively.

Now, from (19), (25), (27), and the limiting equality of (26),the solution vector [m(t) idc(t) vdc(t) Ld]

T is determined asdetailed as follows.

A. Iterative Solution of idc

From an initial description of m(t) : m[0] = M sin(ωt), (25)is solved to obtain the first estimate of the function vdc(t).This (first) iteration reveals only second harmonic terms andthe associated ripple factors

K[1]2s = −K K

[1]2c = 0 (28)

where K is as defined in (8). Both these coefficients are stillobtained as functions of Ld, which remains to be determined.

The equality condition of (26) is then employed to determinethe numerical value of K, which signifies the control limit onsource current wave shape. For a given M , the unique real root(θ) of the normalized limiting equation (NLE)

M sin(θ) +mh(θ) = 1, θ = ωt (29)

is a function of K. Considering that 0 ≤ K ≤ 1 and M isknown from the design specifications, this yields a uniquenumerical solution for K = K [1], which completely definesmh(t)

[1]. Since δm is not known, μ is used instead of μ. Thisdefines the first estimate of the modulation signal

m(t)[1] = M{1−mh(t)

[1]}sin(ωt) (30)

which is used to solve (25), leading to a more elaborate NLE.Since the coefficients K [2]

nc and K[2]ns appear as functions of K,

the unique real solution again leads to a second estimate of K =K [2]. The numerical difference

δ[1]K = K [2] ∼ K [1] (31)

is an indicator of convergence. The detailed steps of the iter-ative process are mentioned as a pseudocode in Appendix A.The normalized waveforms of idc(= idc/Io), as derived inAppendix B, and is1(= is1/Io) are shown in Fig. 4(a). Since0 < M ≤ 1, the aforementioned process is repeated for regularincrements in M . This yields distinct (M,K) pairs, which areplotted in Fig. 4(b). These normalized curves are applicable for

Fig. 4. (a) Normalized dc and source currents. (b) Boundary of distortion.

all power ratings and grid parameters and reduce the optimalinductor design problem to simple table lookup.

B. Filter Design

Second-order filters are used at both ends, as shown in Fig. 2,for optimal filter size at the required level of attenuation. Thegeneralized filter transfer function is

Gfk =1(

sω0k

)2+ s/(Qkω0k) + 1

, k ∈ {s, d} (32)

where subscripts “s” and “d” indicate input (ac) and output (dc)filters. The following relations pertain to the dc filter:

GfdΔ=

vo(s)

vdc(s)ω0d =

1√LdCd

Qd =1

rd

√Ld

Cd. (33)

Corresponding relations for the input filter are

GfsΔ=

is(s)

ist(s)ω0s =

1√LsCs

Qs =1

rs

√Ls

Cs(34)

where {Ls, Cs, rs} and {Ld, Cd, rd} are the inductance, ca-pacitance, and inductor coil resistance of the input and outputfilters, respectively.

1) DC Filter: In a given application, the range of M isdefined by the given source voltage values and the outputvoltage requirement. For the minimum inductance value inthis range, the corresponding K from Fig. 4(b) defines themaximum allowable ripple in idc. The dc inductance can hencebe designed using

Ld =Vo

2ωKIomin(35)

where Iomin is the specified minimum load current. For the BRcircuit considered here (M � 0.65), with parameters listed inTable I, the corresponding value of K from Fig. 4(b) is 0.55.Using (35), variation of required minimum value of Ld for thepresent rated power and partial loads is shown in Fig. 5. Theexact value of Ld chosen, also listed in Table I, therefore allowsgood source current wave shape up to 27.7% load.

DC capacitor Cd, listed in Table I, is selected for secondharmonic attenuation. For a stated maximum load current Io,rated ripple current of Cd is governed by ripple factors Knc andKns in addition to Io. Usually, for aluminum electrolytic capac-itors, design using ripple current ratings ensures adequately low


TABLE IDESIGN SPECIFICATION AND DC SIDE FILTER

Fig. 5. Variation of minimum Ld versus M for present system at variousloads.

TABLE IICOMPARISON OF DC FILTERS

voltage ripple and need not be separately addressed. However,in general, the capacitance value must additionally ensure avoltage ripple of less than 1%.

2) Comparative Evaluation of Magnetics: Table II lists thespecific energy stored in the dc link inductor, normalized withrespect to power rating of CSI, for various existing controlstrategies. Minimum loading condition and dc inductance men-tioned in [21] violate the boundary condition of (29) and hencewere not considered for comparison. Clearly, the proposedmethod ensures lowest specific stored energy and, hence, min-imum inductor core area product Ap = f(Edc) for a givenfrequency and power rating.

In the conventional boost-rectifier approach, step-downtransformer offers major contribution to the weight of thesystem. Referring to Table I, the conventional VSI topology willrequire a 230/43.5-V 1200-VA 50-Hz step-down transformer,which contributes most to the total weight. Likewise, in theproposed solution, the major contribution to the total weight isfrom the dc inductance Ld. Since the B−H loop in a dc induc-tor is minor, its design is driven only by copper losses, while, fortransformers, the core losses are comparatively larger. Hence,for similar core material, the inductor can be designed for a sig-nificantly higher flux density, very near to saturation. In the pro-posed method, it is, in fact, advantageous since the consequentreduction in inductance at higher loads does not affect the waveshaping properties. Comparative estimation of a 50-Hz traction

TABLE IIICOMPARISON OF WEIGHT AND LOSSES

Fig. 6. Equivalent BR circuit as seen through source terminals.

transformer and a dc inductor, designed for identical rated load,is given in Table III in terms of specific weight, volume, cost,and efficiency. CRGO grade M-0H is used for both the designs.From Table III, it is seen that the proposed topology offersapproximately 30.4% reduction in weight and 30.7% reductionin volume, while the efficiencies are comparable.

3) Source Filter: The input filter is designed to attenuatethe h.f terms in the source current. The exact configuration isslightly different, with a damping resistor placed as shown inFig. 6. Consequently, the filter transfer function gets modified to

Gfs =r{s/(

rLs

)+ 1}

(s

ω0s

)2+ s/(Qsω0s) + 1

Qs = r

√Cs

Ls. (36)

Concerns about overall efficiency are adequately addressed byensuring that, at fundamental frequency ω

ωLs � r. (37)

IV. DYNAMIC MODEL

Assuming ideal switches and neglecting equivalent seriesresistance of capacitors, the BR circuit of Fig. 2, with resistiveload, is described by

dx

dt=

⎡⎢⎢⎣

0 1Cd

0 0

−1/Ld 0 mLd

0

0 −m/Cs 0 1Cs

0 0 −1/Ls 0

⎤⎥⎥⎦x

+

⎡⎢⎣

0001Ls

⎤⎥⎦ vs +

⎡⎢⎣−1/Cd

000

⎤⎥⎦ io (38)

where

x = [vo idc vac is]T uc = m ud1 = vs ud2 = io. (39)

Product of the control input m and states vac and idc renderthe system nonlinear; hence, steady-state responses have fre-quency components, different from the excitation. Large-signal


Fig. 7. Large-signal model of BR circuit.

model of the system can be visualized as a superposition ofN subsystems, each operating at different steady-state frequen-cies [24], as shown in Fig. 7. Although N should be infinite fortheoretically accurate reconstruction, low-pass nature (inertialelements) of the system ensures that higher order (highersteady-state frequencies) subsystems are practically inconse-quential. A simplified, yet realistic, analysis of the dc subsystemis carried out under the following assumptions.

1) Switching frequency fs � system frequency f .2) Ls offers negligible impedance at frequency f .3) vs has constant magnitude and no harmonics.Dynamic equations modeling the dc subsystem are derived

from Fig. 7(c) as follows:

d

dt

[vo0idc0

]=

[−Ro

Cd

1Cd

− 1Ld

0

] [vo0idc0

]+

[01Ld

]vdc0. (40)

From (40), the voltage gain of the dc subsystem evaluates to

Gv(s) =vo0(s)

vdc0(s)=

1(s2LdCd + s

(Ld

Ro

)+ 1) . (41)

From power balance and ignoring losses in converter and filter

0.5VmIs1 = vdc0idc0. (42)

Considering small perturbations (vdc0, vo0, Is1, idc0) around anequilibrium point (Vdc0, Vo0, Is1, Idc0), (42) is linearized toobtain

Is1(s) =2

Vm

(Vdc0idc0(s) + Idc0vdc0(s)

)

=

(2IoVm

+M

Zo(s)

)vdc0(s) (43)

Fig. 8. Bode plot for control transfer function.

Fig. 9. Block diagram of the proposed control scheme.

where

Zo(s) =vdc0(s)

idc0(s). (44)

Using (41) and (43), the control transfer function is

G(s)=vo0(s)

Is1(s)

=vo0(s)

vdc0(s)· vdc0(s)Is1(s)

=VmRo

4Vo {(0.5LdCd)s2+0.5(Ld/Ro+CdRo)s+1} . (45)

Bode plot of G(s), using the parameters listed in Table I, isshown in Fig. 8. Opting for a slow closed-loop performanceand no steady-state error, a proportional–integral controller isadequate

H(s) = kp + ki/s. (46)

Bode plot for the loop gain G(s)H(s) is also shown in Fig. 8.Gain crossover frequency of 35 rad/s indicates a closed-loopsettling time of 114 ms.

Fig. 9 shows a simplified control block diagram of theBR circuit. This is a single-loop structure, where the errorin vo drives the controller output, which directly decides thesource current amplitude. The reference source current is gen-erated after multiplication with the fundamental voltage wave-form template, obtained through a phase-locked loop (PLL).


TABLE IVCIRCUIT AND CONTROLLER PARAMETERS

TABLE VBASIC RATINGS

Description of the PLL is omitted here for brevity; however, therelated equations are derived from [25] and [26]. Modulationsignal is generated per (19), using a measurement of idc.

V. CIRCUIT SIMULATION

The BR circuit, shown in Fig. 2, is simulated using EMTP.Exact switching is modeled; however, losses are not considered.Parameter values used are listed in Tables I and IV.

Considering a 5-MVA 25-kV ac/1.5-kV dc traction drivesystem and availability of 6.6-kV IGBTs, 11 BR modules arerequired, each sharing 2.27 kV on the ac side. Specificationsfor both the traction module and the exact scaled down module(corresponding to 230-V ac) are given in Table V. With thegiven operating condition (M = 0.93) and using Ld as given inTable I, the corresponding value of K, derived from Fig. 4(b),sets the Iomin limit to 8.06 A (0.26 p.u.). Hence, wave shaping isachieved up to 26.5% of the rated load. However, with the use ofactual parameters, as listed in Table I, wave shaping is achievedup to 27.7% of the rated load. Since the aim of the proposedcontrol method is to verify the suitability of BR circuit at lowerloads, the parameters used for simulation and experimentalresults correctly emulate the low load phenomenon of an actualtraction module.

A. Sinusoidal Source Voltage

Fig. 10(a) shows the steady-state simulation results underrated conditions. Input ac source voltage of 230 V is steppeddown to 100-V dc while maintaining sinusoidal and UPF sourcecurrent. Fig. 10(b) shows that the third harmonic in sourcecurrent is 0.11% of fundamental, thus satisfying IEEE 519-1992 limits. Steady-state simulation results under minimumload conditions (Io = 3.3 A) and sinusoidal source voltage areshown in Fig. 11. It is concluded that, as long as the boundarycondition requirement is fulfilled, third harmonic content insource current is not dependent upon load, unlike conventionalcontrol topologies.

Dynamic response to a positive and negative step command(50 V) in the output voltage reference is shown in Fig. 12,

Fig. 10. (a) Simulation results: Steady-state operation. vs (160 V/div); is(5 A/div); idc (5 A/div); vo (160 V/div); time (5 ms/div). (b) Harmonicspectrum of is (percentage of fundamental).

Fig. 11. (a) Simulation results: Steady-state operation at boundary condition.vs (160 V/div); is (5 A/div); idc (5 A/div); is1 (5 A/div); time (5 ms/div).(b) Harmonic spectrum of is (percentage of rated fundamental).

Fig. 12. Simulation results: Dynamic performance with step change in voreference. idc (8 A/div); v∗o (25 V/div); vo (25 V/div); time (40 ms/div).

Fig. 13. Simulation results: Dynamic performance with step change in vs. vs(200 V/div); is (10 A/div); idc (5 A/div); vo (100 V/div); time (20 ms/div).

where the output voltage settles in approximately 114 ms. Thisaccords well with the analytical design. Dynamic performancewith step change of 20% in source voltage is shown in Fig. 13.

B. Effect of Source Voltage Distortion

The distorted source voltage is expressed as

vs = v(1)s + v(h)s (47)


Fig. 14. Simulation results with distorted source. (a) vs (120 V/div); is(5 A/div); time (5 ms/div). (b) Harmonic spectrum of is (percentage offundamental).

where the second term includes the harmonic components. Forthe nth harmonic, the modulation signals generate vdc(n±1)

terms in the dc voltage vdc and, consequently, idc(n±1) termsin dc current idc. However, since the modulation signal m(t) iscalculated by active division of Is1 sin(ωt) and idc(t), hence,presence of lower order harmonic terms in idc does not affectthe quality of source current ist. From Fig. 6, the input filter isseen to provide a linear circuit, in parallel with the converter.Thus, the source current harmonics are a superposition of thefollowing components:

i(h)s = i(h)st + i

(h)sf (48)

where isf is the source current with rectifier circuit discon-nected, ist is the low-frequency component of ist, and thesuperscript (h) denotes the harmonic order. Simulation resultswith distorted source voltage are shown in Fig. 14. The har-monic spectrum of source current is also presented. The thirdharmonic component of is is observed to have increased to1.8% of the fundamental. This difference is attributed to thepresence of source voltage harmonics.

VI. EXPERIMENTAL RESULTS

A 1.2-kW laboratory prototype BR is developed using volt-age bidirectional IGBT–diode switches. The controller is re-alized on FPGA (Altera Cyclone II)-based platform, using asampling frequency of 10 kHz. Other component values andcompensator gains are listed in Table IV. Hall effect currenttransducers and optical isolation amplifiers are used for currentand voltage sensing, respectively.

Steady-state experimental results under rated conditions areshown in Fig. 15(a), where almost-UPF (PF = 0.999) operationis observed. The slight leading PF at lower loads is observeddue to the leading reactive current drawn by the input filtercapacitor. The harmonic spectrum of the source current is isshown in Fig. 15(b). It reveals that all the lower harmonicsare within 4% of the rated fundamental (IEEE 519-1992 limit).Fig. 15(c) shows another view of steady-state operation, wherethe PLL output and modulation signal m(t) are also shown. Theharmonic spectrum of the source voltage is shown in Fig. 15(d).Source current PF and total demand distortion (TDD) curvesplotted with load variations are shown in Fig. 16. Measuredefficiency of the BR module is 91.8%. Steady-state experi-mental results at boundary condition (Io = 3.4 A) are shownin Fig. 17(a). The harmonic spectrum of the source current as

Fig. 15. (a) Experimental results: Steady-state operation. vs (200 V/div);is (10 A/div); idc (10 A/div); vo (200 V/div). (b) Harmonic spectrum of is(percentage of fundamental). (c) PLL output (10 V/div); m(t) (10 V/div).(d) Harmonic spectrum of vs (percentage of fundamental); time (5 ms/div).

Fig. 16. PF and TDD variations with load.

Fig. 17. (a) Experimental results: Steady-state operation at boundary condi-tion. vs (200 V/div); is (10 A/div); idc (10 A/div); is1 (10 A/div). (b) Harmonicspectrum of is (percentage of rated fundamental); time (5 ms/div).

percentage of rated fundamental current is shown in Fig. 17(b).From Fig. 17, it is clear that BR circuit is capable of maintainingsinusoidal source current under variable load conditions, wheredc inductor design is the deciding factor for the minimum load,as given by (35). Experimental results for boundary conditionviolation are shown in Fig. 18. With parameters mentioned inTable VI, the revised value of Iomin is 7.9 A. From Fig. 18(b),it is seen that the percentage of third harmonic with boundarycondition violation has increased to 5.5%. It is obviously higher


Fig. 18. (a) Experimental results: Steady-state operation below boundarycondition. vs (200 V/div); is (10 A/div); idc (10 A/div); is1 (10 A/div).(b) Harmonic spectrum of is (percentage of rated fundamental); time (5 ms/div).

TABLE VICIRCUIT PARAMETERS FOR BOUNDARY CONDITION VIOLATION

Fig. 19. Experimental results: Dynamic response to step (50 V) in out-put voltage reference. idc (10 A/div); vo (50 V/div); v∗o (50 V/div); time(100 ms/div).

than the conditions, when experiments are conducted withoutviolation.

Experimental results for transient conditions are shown inFig. 19. A positive and negative step command of 50 V(50%) is given to the output voltage reference, and the responseis recorded. The observed settling time (ts) is around 114 ms,which validates both analytical and simulation results.

VII. CONCLUSION

In this paper, a single-loop control scheme for single-phaseBR has been presented. A nonlinear modulation scheme isproposed, and its effect is analyzed using a multiorder systemdecomposition. The effectiveness of the proposed scheme isproved by simulation and experimental results. From experi-mental results, it is clear that the proposed control scheme iscapable of maintaining sinusoidal source current and near-UPFoperation with optimum filter volume, even under distorted gridconditions. Generalized design of the dc inductor, which isthe most critical element, is presented in detail. Since sourcecurrent wave shape is maintained despite ripples in dc current,requirement of an inner current loop is rendered superfluous.Apart from justifying the single-loop control scheme, this alsoentails greatly simplified controller design and realization.

APPENDIX A

Pseudocode for estimation of steady-state profile of idc(t) isas follows.

Step 1) Initialize m[0] = M sin(θ),vs = Vm sin(θ) and K [0] = 1.Define error δk.

Step 2) Calculate v[i]dc using: v[i]dc = m[i−1] · vs

From v[i]dc, using (27), calculate

i[i]dc = Io

⎧⎪⎨⎪⎩1 +

n1=i∑n1=1n=2n1

Knc cos(nθ) +

n1=i∑n1=1n=2n1

Kns sin(nθ)

⎫⎪⎬⎪⎭ .

Step 3) Calculate K [i] using

1 = M sin(θ) +

n1=i∑n1=1n=2n1

Knc cos(nθ) +

n1=i∑n1=1n=2n1

Kns sin(nθ).

Step 4) If |K [i] −K [i−1]| ≤ δk,StopElse set K [i] = K [i−1],Calculate m[i] = Is1 sin(θ)/i

[i]dc and

Set i = i+ 1.Go to Step 2).

APPENDIX B

The use of pseudocode leads to convergence of K after sixthiteration. At seventh iteration δk = 0.023, K = 0.6 and idc(t)is given as

idc(t)=Io

⎧⎪⎨⎪⎩1+

3∑n1=1n=2n1

Knc cos(nωt)+3∑

n1=1n=2n1

Kns sin(nωt)

⎫⎪⎬⎪⎭

where

K2c =

(−1

dK2 +

21

16bcdK4 − 1063

576gK6

)1

f

K4c =

(1

4dK2 − 23

48bcdK4 +

9787

13824gK6

)1

f

K6c =

(11

144abcK4 − 5599

41472gK6

)1

f

K2s =

(−K +

9

8cdK3 − 149

96gK5 +

60811

27648gK7

)1

f

K4s =

(− 3

8cdK3 +

169

288gK5 − 140857

165888gK7

)1

f

K6s =

(1

24cdK3 − 367

3456gK5 +

412247

2488320gK7

)1

f

a =(2−K2)

2

b =(2− aK2)

2


c =1− ab

(K2

2

)+ 21ab

(K4

32

)

d =1− bc

(K2

2

)+ 21abc

(K4

32

)

f =1− cd

(K2

2

)+ 21g

(K4

32

)− 1063g

(K6

1152

)g = abcd.

Higher order harmonics (� Io) are ignored.

ACKNOWLEDGMENT

The authors would like to thank A. K. Basu andNandkishore for their support during development of the ex-perimental hardware.

REFERENCES

[1] M. Brenna, F. Foiadelli, and D. Zaninelli, “New stability analysis fortuning PI controller of power converters in railway application,” IEEETrans. Ind. Electron., vol. 58, no. 2, pp. 553–543, Feb. 2011.

[2] M. Carpita, M. Marchesoni, M. Pellerin, and D. Moser, “Multi-level converter for traction applications: Small-scale prototype test re-sults,” IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 2203–2212,May 2008.

[3] P. Drabek, Z. Peroutka, M. Pitterman, and M. Cedl, “New configurationof traction converter with medium-frequency transformer using matrixconverters,” IEEE Trans. Ind. Electron., vol. 58, no. 11, pp. 5041–5048,Nov. 2011.

[4] A. Rufer, N. Schibli, C. Chabert, and C. Zimmermann, “Configurablefront-end converters for multicurrent locomotives operated on 16 2/3 Hzand 3 kV DC systems,” IEEE Trans. Power Electron., vol. 18, no. 5,pp. 1186–1193, Sep. 2003.

[5] S. Dieckerhoff, S. Bernet, and D. Krug, “Power loss-oriented evaluation ofhigh voltage IGBTs and multilevel converters in transformerless tractionapplications,” IEEE Trans. Power Electron., vol. 20, no. 6, pp. 1328–1336,Nov. 2005.

[6] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu,J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrialapplications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57,no. 8, pp. 2553–2580, Aug. 2010.

[7] M. F. Schlecht, “Harmonic-free utility/DC power conditioning inter-faces,” IEEE Trans. Power Electron., vol. PEL-1, no. 4, pp. 231–239,Oct. 1986.

[8] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, andD. P. Kothari, “A review of single-phase improved power quality AC–DCconverters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981,Oct. 2003.

[9] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, andD. P. Kothari, “A review of three-phase improved power quality AC–DCconverters,” IEEE Trans. Ind. Electron., vol. 51, no. 3, pp. 641–660,Jun. 2004.

[10] A. A. Badin and I. Barbi, “Unity power factor isolated three-phase rectifierwith two single-phase buck-rectifiers based on the Scott transformer,”IEEE Trans. Power Electron., vol. 26, no. 9, pp. 2688–2696, Sep. 2011.

[11] T. C. Green, M. H. Taha, N. A. Rahim, and B. W. Williams, “Three-phase step-down reversible AC–DC power converter,” IEEE Trans. PowerElectron., vol. 12, no. 2, pp. 319–324, Mar. 1997.

[12] H. F. Bilgin, K. N. Kose, G. Zenginobuz, M. Ermis, E. Nalcaci, andH. Kose, “A unity-power-factor buck-type PWM rectifier for medium/high-power DC motor drive applications,” IEEE Trans. Ind. Electron.,vol. 38, no. 5, pp. 1412–1425, Sep./Oct. 2002.

[13] Z. Wang, B. Wu, D. Xu, and N. R. Zargari, “A current-source-converter-based high-power high-speed PMSM drive with 420-Hz switching fre-quency,” IEEE Trans. Ind. Electron., vol. 59, no. 7, pp. 2970–2981,Jul. 2012.

[14] E. Al-nabi, B. Wu, N. R. Zargari, and V. Sood, “Input power factorcompensation for high-power CSC fed PMSM drive using d-axis statorcurrent control,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 752–761,Feb. 2012.

[15] R. Itoh, K. Ishizaka, H. Oishi, and H. Okada, “Single-phase buck rectifieremploying voltage reversal circuit for sinusoidal input current waveshap-ing,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 146, no. 6, pp. 707–712, Nov. 1999.

[16] K. Hirachi and Y. Tomokuni, “Improved control strategy to eliminatethe harmonic current components for single-phase PWM current sourceinverter,” in Proc. INTELEC, 1997, pp. 189–194.

[17] Y. Lo and R. J. King, “High frequency ripple feedback for the buck unity-power rectifier,” IEEE Trans. Power Electron., vol. 10, no. 2, pp. 158–163,Mar. 1995.

[18] G. Ertasgin, D. M. Whaley, N. Ertugrul, and W. L. Soong, “Analysisand design of energy storage for current-source 1-ph grid-connected PVinverters,” in Proc. APEC, 2008, pp. 1229–1234.

[19] B. M. M. Mwinyiwiwa, P. M. Birks, and B. Ooi, “Delta-modulated buck-type PWM converter,” IEEE Trans. Ind. Appl., vol. 28, no. 3, pp. 552–557,May/Jun. 1992.

[20] R. Oruganti and M. Palaniapan, “Inductor voltage control of buck-typesingle-phase AC–DC converter,” IEEE Trans. Power Electron., vol. 15,no. 2, pp. 411–416, Mar. 2000.

[21] R. T. H. Li, H. S. Chung, and T. K. M. Chan, “An active modulation tech-nique for single-phase grid-connected CSI,” IEEE Trans. Power Electron.,vol. 22, no. 4, pp. 1373–1382, Jul. 2007.

[22] N. R. Zargari, G. Joos, and P. D. Ziogas, “Input filter design for PWMcurrent-source rectifiers,” IEEE Trans. Ind. Appl., vol. 30, no. 6, pp. 1573–1579, Nov./Dec. 1994.

[23] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Con-verters. New York: Wiley-IEEE, 2003.

[24] R. Tymerski, V. Vorpérian, F. C. Y. Lee, and W. T. Baumann, “Nonlinearmodeling of the PWM switch,” IEEE Trans. Power Electron., vol. 4, no. 2,pp. 225–233, Apr. 1989.

[25] R. K. Sinha and P. Sensarma, “A pre-filter based PLL for three-phase gridconnected applications,” Elect. Power Syst. Res., vol. 81, no. 1, pp. 129–137, Jan. 2011.

[26] I. Carugati, P. Donato, S. Maestri, D. Carrica, and M. Benedetti, “Fre-quency adaptive PLL for polluted single-phase grids,” IEEE Trans. PowerElectron., vol. 27, no. 5, pp. 2396–2404, May 2012.

Poonam Chaudhary received the B.E. degree inelectrical engineering from Rajiv Gandhi TechnicalUniversity, Bhopal, India, in 2001 and the M.E.degree in power electronics from Samrat AshokTechnological Institute, Vidisha, India, in 2006. Sheis currently working toward the Ph.D. degree in theDepartment of Electrical Engineering, Indian Insti-tute of Technology Kanpur, Kanpur, India.

Her research interests include power convertertopologies, modeling, and control techniques.

Parthasarathi Sensarma (M’00) received theB.E.E. degree in electrical engineering fromJadavpur University, Calcutta, India, in 1990, theM.Tech. degree in electrical engineering from theIndian Institute of Technology (IIT) Kharagpur,Kharagpur, India, in 1992, and the Ph.D. degree inelectrical engineering from the Indian Institute ofScience, Bangalore, India, in 2001.

He was with Bharat Bijlee Ltd., Thane, India,Calcutta Electric Supply Corporation, Calcutta,and ABB Corporate Research, Baden-Daettwil,

Switzerland, where he was a Staff Scientist with the Power Electronics Depart-ment. Since 2002, he has been with the Department of Electrical Engineering,IIT Kanpur, Kanpur, India, where he is currently an Associate Professor. Hisresearch interests include design and control of power converters, custom powerapplications, integration of renewable energy, and microgrids.

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