From 2D to 3D with SOI and Layer Transfer Technologies...2011/10/19 · key modules • N-P Trench Isolation Module • Oxide deposition / Oxide etch / CMP • Nwell lithography

Carlos Mazure

Santa Clara, October 19th, 2011

From 2D to 3D with SOI and Layer Transfer Technologies

GSA 3D WG – Santa Clara Oct. 19, 2011 2

Outline

IC Industry is introducing several disruptions in the scaling race

• Fully Depleted Transistors: planar and FinFET

• Integration of layer transfer in FEOL

• Wafer to Wafer Stacking

• Summary


• VT variability has strongly impacted IC design– VT mismatch

– SRAM cell scalability: 6T 8T 10T

– Limitation of Vmin

– Limitation of low VDD operation at acceptable performance

• MOSFET Ioff leakage is an increasing concern– Slow down of LG scaling increasing complexity of contact

– Tradeoff power consumption vs. performance

• CMOS: Increasing complexity of bulk process– Bulk based CMOS no longer good enough for low VDD applications

Shrinking to 22/20nm and beyond


Ultra-ThinBody

Ultra-Thin Si. FilmBuried Oxide

Planar FD-SOI

GS D

Base Si

Planar

FinFET / TriGate

Non-Planar Lg

S DG

Base Si

H=TsiW

Buried Oxide

Courtesy of IBM

Courtesy of IMEC

The Scaling Path: Ultra-Thin Body Devices


Fully Depleted 2D : UTSOI 12nm / BOX 25nm substrates

The Substrate for fully depleted 2D technology is ready

• Wafer to wafer top Si control: – 6 Sigma: ±3Å Wafer-to-Wafer in production mode

• Within wafer Si thickness control– Full wafer range (6 Sigma) < 7Å

– Surface roughness 30x30µm² RMS <2.0Å

Best thickness mapSi Range = 4 Å

RMS 2.0

RMS 1.8RMS 2.0

RMS 1.8 A


Fully Depleted 3D substrates: Faster, Cheaper, Better

Process & statistical variability• Process induced fin height variability• Implant induced RDF

Bulk

Bulk-based Isolation adds several key modules• N-P Trench Isolation Module • Oxide deposition / Oxide etch / CMP• Nwell lithography / pFET isolation

doping• Pwell lithography / nFET isolation

doping

Si etch

Transistor

BEOL

• No fin height variability• No RDF• Simplest Fin formation• Shorter cycle times• Significant cost savings

FD 3D Substrate

Tim

e to

Mar

ket

1. Development Lead Time– SOI-based Isolation is much simpler

2. Cost and Cycle time for FinFET– SOI-based Isolation goes directly into fin module

and device integration

SOI is compelling on Key Fronts


True Fully Depleted 3D Transistors

• Faster development & faster cycle times– Lower R&D cost

– 1 year earlier readiness

• Cheaper POR & Simpler process– Lower opex & capex

– Same MOL & BEOL

– Same design environment

• Better Manufacturing– Lowest variability

– Higher yields

• Lower power ICs for mobile– Lower VDD & Vmin

– Better Ion & significantly lower Ioff leakage

10/19/2011 7


XTREME SOI

2010 2011 2012 2013FAMILY PRODUCTS LAYERS (nm)

PREMIUMSOI

SOI : 30 – 90BOX : 145

High Volume Manufacturing

FD3D

20 nm readiness 15 nm readiness

HVMRampUTBOX10SOI : 10 – 20BOX : 10

Dev

sSOIsSOI : 10 – 15BOX : 25

RampDevR&D

UTBOX25 High Volume Manuf. RampDevSOI : 10 – 20BOX : 20 – 50

High Volume Manuf. SOI : 35BOX : 145

PDSOI devices

FDSOI (FD2D) devices

FinFET (FD3D) devices

10/19/2011 8

Product Roadmap


Why does it matter for fabless?

• Cheaper POR and simplest solutionSubstrates for FD 2D and 3D pre-integrate device process steps

• Faster time to market– Shorter R&D,

– Re-use Mid of the line & BEOL

• Better manufacturing– Robust and competitive

– Less variability drive lower power and lower Vdd operations

Both FD Substrates are ready nowCost competitive substrate enabling a significantly

cheaper technology scaling.

10/19/2011 9


Outline





• Summary


• Smart StackingTM

– Dielectric Bonding

– Metal-Metal Bonding

• Smart CutTM

– Thin crystalline film stack transfer onto a processed wafers

Bonding Process Schematic Principle

Direct oxide bonding

Mechanicalbond only

Non-Thermo compression: Metal to metal & Metal to oxide

Electrical + mechanical

bond

Direct Bonding Technologies

CMOS waferCrystalline Si

CMOS

Crystalline -Sioxide

Soitec Layer Stacking Building Blocks for 3D Integration


Low-Temp Smart Cut™: Enable Layer Transfer in FEOL


400

600

800

10001018 1019 1020 1021 1022

Concentration ( H/cm3 )

Dep

th(n

m)

H implantation profileH implantation profile

Initial Initial SiliconSilicon

OxidationOxidation

Smart Smart CutCutImplantationImplantation

AA

AA

AA

BB

Concentration (cm-3) C. Maleville et al., SOI Conf. 2001.

implated zone

Smart Cut™ Fundamentals: Thin Layer Definition


BB

AA

AA

BB

SOI waferSOI wafer

CleaningCleaning & & BondingBonding

SplittingSplitting

AnnealingAnnealing & & FinishingFinishing

Example: SOI 76nm Si on 20nm SiO2 C. Maleville et al., SOI Conf. 2001.

Smart Cut™ Fundamentals: Layer Transfer


• 300mm low temp Si layer transfer demonstrated on patterned wafers – 200nm ± 15nm top layer transferred

•Good R&D results– Good quality Si film– Defectivity typical of R&D phase– Tmax < 500°C

•Post splitting & surface-smoothing– TSi = 200nm ±15nm– Low micro-roughness = 1.2Å RMS

SP2 @ 1.2um threshold2x2µm2 AFM scan

Low Temp Smart Cut: Very thin layer transfer onto a patterned wafer


Smart Cut + Metal-Metal Direct Bonding

• Demonstration of low temperature Smart Cut with Ti-Ti bonded interface

• Strong bonding energy after 500°C annealing (>2J/m²)• Total Ti thickness ~100nm

300mm Ti-Ti after 500°°°°C annealing


Outline





• Summary


C2W W2W

Laser Drilling Electroplating Adhesive, fusion oxide or

metal-metal bonding Adhesive, fusion oxide or metal-metal bonding

Grinding

DRIE CVD CMP

Photolithography Photolithography Wet Etching Chip alignment Wafer alignment

Wafer/Chip Bonding

TECHNOLOGY

Via Drilling Via Filling Thinning

Soitec Offer

3D Layer Transfer Technologies

• Soitec has expertise and know-how in layer Transfer technologies• Soitec focus is wafer level stacking solutions


Metal-Metal, Metal-Ox & Ox-Ox

1 2 3 4 5

Starting substrate:

– 200 or 300mm

Low CTE mismatch/ sub micron alignment accuracyLow stress / mechanical deformationHigh Bonding strength & uniformity Compatible with processed waferHigh throughput processes w high align accuracy

& alignment

Smart StackingTM Technology


• Low thermal budget (<400oC)• Compatibility with:

– Several metals: Cu, Al, W, Ti– Via last– F2F & F2B

• Oxide type optimized for high bond strength + planarization

• Low Temp bonding/alignment• Thinning

CMOS

CMOS

oxide

CMOS

oxide

CMOS

oxide

CMOS

CMOS

TS

VOxide Dep + Planarization

Bond/Align + Anneal

Thin + TSV

TS

V

oxide

oxide

Oxide-Oxide Bonding for 3D Integration

Smart StackingTM Technology


0

0.5

1

1.5

2

2.5

3

3.5

4

As Bonded 400oC anneal

Post Bonding Treatment

Bo

ndin

g S

tren

gth

(J/

m2)

Oxide 1

Oxide 2

Oxide 3

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

100 150 200 250 300 350 400 450Temperature ( oC)

Bon

ding

Ene

rgy

(mJ/

m2 ) Process A

Process B

Process C

High Bonding Energy @ Low Temp

Optimum Oxide Type for LT Bonding

•Wafer-to-wafer alignment accuracy < 0.5μm with EVG Smart ViewNT® (5 sites)

•Room temperature bonding (ox-ox & Cu-Cu bonding) ⇒ best alignment accuracy (less CTE mismatch)

Smart StackingTM: Robust Low Temp Ox-Ox Bonding


Defects Free Bonding

Acoustic microscopy (source: Tracit BU)

High Bonding Energyat <400°C for post

processing and reliability

1µm

Low Stress BondingCompatible with CFA for

any pixel size

SEM cross section of transferredcircuit layer for BSI image sensors(Courtesy: e2v)

Map overlay (courtesy: F.Roy STM)

Smart StackingTM for Backside Imagers

Large Edge Exclusion

Small Edge Exclusion


• In production for Back Side Illuminated Image Sensor applications• Compliant with military reliability standards (MIL-STD883)

• Passed Vibration, Mechanical Shock & Pull test

Test Condition Pass/Fail

Operating life test (endurance) 125oC/2000h √

High temperature storage 150oC/1000h √

Temperature cycling -55oC, +125oC, 15o/min √

Moisture resistance 65oC, -10oC, 90-100% RH- 10 days √(Courtesy of e2v)

Defect Free

Smart StackingTM for Backside Imagers: HVM


Cu-Cu direct bonding

• Direct hydrophilic bonding

• Room Temperature & ambient air

• No external force/pressure

• Post bond annealing: 150-400oC

• High thru-put/Low cost of ownership

• Compatibility with:

–Via 1st, middle & last

–F2F, F2B

1

2

3

CMOS

CMOS

CMOS

CMOS

CMOS

Std copper dual damascene

Surface planar + Bond/Align + Anneal

Thin + TSV

TS

V

TS

V

Smart StackingTM enables 3D Direct Cu-Cu Bonding


Cu inter-diffusion

Non-annealed

Annealed 400oC

• High bond strength @ low temp anneal

-100 -50 0 50 100

-0,6

-0,4

-0,2

0,0

0,2

0,4

0,6

V(m

V)

I(mA)

1 11 2 12 3 13 4 14 5 15 6 16 7 17 8 18 9 19 10 20

Kelvin Structure 10x10µm² contact area

0

1

2

3

4

5

6

7

8

9

0 100 200 300 400

Anneal Temperature ( oC)

Bon

ding

Ene

rgy

(J/m

2 ) Cu/Cu full sheet

SiO2 / SiO2 full sheet

Cu / SiO2 full sheet

Patterned Cu

Rc_mean = 5 mΩ ±0.2mΩ

Contact Resistance (m Ω)Ω)Ω)Ω)

0

5

10

15

20

process A Process B Best process

RT@200°C@400°C

VML VMH I

I

K. N. Chen et al

• 10x10µm² contact area• Top substrate

completely removed to access pads

Kelvin structure

3D Direct Cu-Cu Bonding: mechanical & electrical data


• Memory & Logic Stacking

– Ox-Ox or Cu-Cu bonding

– Circuit partitioning

• Advantages

– Lower RC delay

– Lower Memory latency

– Higher Bandwidth

– Smaller Form factor

Source: Gabriel H. Loh-Georgia Tech, 2008

Source: Puttaswamy & Loh-Georgia Tech+Intel, 2009

Source: S.S. Iyer-IBM- 3D ASIP conf Dec 2010

Applications of W2W


Patterned optical layer performed on SOI stacked onto a fully processed 200mm CMOS wafer

• Emerging memory or image sensor on logic

– Photodiode, PCRAM, MRAM, RRAM

– Stacking: ox-ox bonding & thinning or LT SmartCut

– Advantages: Density & performance

• MEMS & CMOS Stacking

• Photonics on CMOS

Source: Sasago et. al, Hitachi Central Research Lab 2009

CMOS

oxideCrystalline -Si

Source: S. Kim et. al- Dongbu HiTek, 2009

Image Sensor-diode on top

PCM driven by Poly-Si Diode

Applications of W2W: 3D Memory, Photonics


Summary

• Direct W2W technologies have proven their first industrial application capability.

• BSI Image sensor is 1st application in production.

• Smart Stacking Technology offers flexibility and reliability, enables wafer to wafer 3D integration.

• Low Temperature Smart Cut has proven to be a powerful technology for 3D integration into FEOL.

Soitec can help you designing, developing and bringing to

manufacturing your 3D stacking requirements


Acknowlegdements

• Soitec teams from Corporate, R&D and Business Units, in particular Olivier Bonnin, Ionut Radu, Mariam Sadaka, Walter Schwarzenbach, Jocelyne Wasselin

• Leti teams

Documents

From 2D to 3D with SOI and Layer Transfer Technologies...2011/10/19 · key modules • N-P Trench Isolation Module • Oxide deposition / Oxide etch / CMP • Nwell lithography