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Frequency Planning Part 2 TI Precision Labs – Clocks and Timing
Presented by Rob Rodrigues
Prepared by Hao Zheng
1
156.25MHz
R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
25 MHz
Frequency calculation quick review
2
R = 1
4.8 to 5.4 GHz
D = 31,
32,
33,
34
5000 MHz
N = 200
25 MHz
32,
4800 / 156.25 = 30.72
5400 / 156.25 = 34.56
IBS frequency
350 kHz
56.61 MHz
12.87 MHz
1/P
PrescalerVCO
1/CH
Channel divider
VCO selection and spur mitigation
3
2 to 8
31
32 = 4 x 8
33 = 3 x 11
34 = 2 x 17
156.25 MHz + 70 ppm =
156.2609375 MHz
1/D
4.8 to 5.4 GHz
VCO frequency
5000.35 MHz
5156.6109375 MHz
5312.871875 MHz
fIBS = fVCO % fPFD
How to generate 156.25 MHz + 70 ppm from 100 MHz PFD frequency?
R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)156.25MHz
25 MHz
Frequency calculation and PFD frequency
5
R = 1
4.8 to 5.4 GHz
5000 MHz
N = 200
25 MHz
25 MHz 24 MHz
R Divider
x2 1/R
Reference Oscillator
Doubler
Setting PFD frequency
6
24 MHz
x2 /1 = 48 MHz
x1 /1 = 24 MHz
x2 /3 = 16 MHz
. . .
PFD Frequency
Short Quiz
1
1. True or False:
The Integer Boundary Spur should be as close to the carrier frequency as possible.
Short Quiz
2
1. True or False:
The Integer Boundary Spur should be as close to the carrier frequency as possible.
Short Quiz
3
2. True or False:
The PFD frequency should be as low as possible for the PLL to always work in integer mode.
Short Quiz
4
2. True or False:
The PFD frequency should be as low as possible for the PLL to work in integer mode.
Short Quiz
5
3. True or False:
Channel crosstalk is intrinsic and cannot be improved or worsened by board design.