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Getting to Work with OpenPiton
Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Nguyen,
Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs,
Samuel Payne, Xiaohua Liang, Matthew Matl, David Wentzlaff
Princeton University
OpenPit
http://openpiton.org
FPGA Prototyping
2
Supported Development Boards
3
4 boards supported by toolchain:
Xilinx VC707
Digilent Genesys2
Digilent NexysVideoDigilent Nexys4DDR** doesn’t have DDR controller and FPU
Comparison of Supported Boards
4
Development Board,FPGA name,
Part
Core Clock(1 core)
# Cores DDR Type,Size,
Data Width
Price (nonacademic/
academic)
Xilinx VC707Virtex-7
XC7VX485T-2FFG1761C67 MHz 4
DDR31 GB
64 bits$3,495
Digilent Genesys2Kintex-7
XC7K325T-2FFG900C60 MHz 2
DDR31GB
32 bits
$1,299/$600
Digilent NexysVideoArtix-7
XC7A200T-1SBG484C29 MHz 1
DDR3512MB16 bits
$490/$250
Digilent Nexys 4 DDRArtix-7
XC7A100T-ACSG324C29MHz 1
DDR2128MiB16 bits
$320/$160
I/O Interfaces
5
OpenPitonCore
DRAM
SD MasterAXI4-
Lite UART
I/O Interfaces
6
Wishbone SD Master:• Up to 2GB SD (microSD) cards• Storage for boot/OS/tests• Optional
OpenPitonCore
DRAM
SD MasterAXI4-
Lite UART
UART:• Terminal I/O• Loading of assembly test
DDR controller:• Xilinx’s MIG• Configurable data width• Used as main memory• Optional
Demo
7
Recommended Configurations
8
BRAM with assembly test• fast verification of architecture• directed tests• main memory emulated in BRAMs
BRAM with OpenBoot PROM (OBP)• verifies basic I/O operations• main memory emulated in BRAMS
SD with OS image• full power of SW stack• performance tests with benchmarks
CORE
MEM/ I/O
DDR
SD
UART / SD
UART
CORE
BRAMTEST
UART / TEST
UARTCORE
MEM/ I/O
DDR
BRAMBOOT
UART /BOOT
UART
Recommended Configurations
9
SD with OS
BRAM_TEST BRAM_BOOT
BRAM with test + bram_map module
BRAM with OBP +bram_map_obp module
DDR memory controller
SD card controller
UART 16550
Tools
• Source located at piton/tools/src/proto/
• protosyn
– All encompassing tool
• make_mem_map
• image2stream
10
make_mem_maptest log.coe
bram_map.v
image2stream.coe .stream
protosynboard type, design, config.xpr
.bit
protosyn Flow
11
bram test?
*.v.pyv -> *tmp.v
sims build
sims run
RTL
make_mem_map
create project?
mem.imagesims.log
test_proto.coe
project creation .xpr
synthesis
mapping, placing, routing, bitstream generation, STA
NO
YES
implement?
YES
NO
IP cfg (.xci),constraints (.cdc),obp.coe,defines
YES
NO
.xpr
.bit,
.ltx
LegendControl FlowData Flowpyv preprocessorSims scriptMake_mem_map scriptVivadoinput/output filesflow step conditions
Running FPGA Flow
12
Running FPGA Flow
12
Running FPGA Flow
12
Running FPGA Flow
12
piton/tools/src/proto/block.list
Running FPGA Flow
12
Running FPGA Flow
12
Running FPGA Flow
12
Running FPGA Flow
12
FPGA Flow Hello World Example
13
FPGA Flow Hello World Example
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FPGA Flow Hello World Example
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FPGA Flow Hello World Example
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FPGA Flow Hello World Example
13
FPGA Flow SD Example
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FPGA Flow SD Example
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FPGA Flow SD Example
14
FPGA Flow SD Example
14
FPGA Flow Runtimes
• System including DDR controller
– ~1 hour including IP generation
– ~20 mins excluding IP generation
15
FPGA Flow Outputs
16
FPGA Flow Outputs
16
FPGA Flow Outputs
16
FPGA Flow Outputs
16
FPGA Flow Outputs
16
FPGA Flow Outputs
16
FPGA Flow Outputs
17
FPGA Flow Outputs
17
FPGA Flow Outputs
17
FPGA Flow Outputs
17
FPGA Flow Outputs
18
FPGA Flow Outputs
18
FPGA Flow Outputs
18
FPGA Flow Outputs
18
Opening FPGA Design
19
Opening FPGA Design
19
Opening FPGA Design
19
Opening FPGA Design
20
Opening FPGA Design
20
Opening FPGA Design
20
Opening FPGA Design
20
Writing OS Image to SD Card
21
Writing OS Image to SD Card
21
Writing OS Image to SD Card
22
Writing OS Image to SD Card
23
Writing OS Image to SD Card
23
Hands-on with FPGA
24
FPGA Programming
25
FPGA Programming
25
FPGA Programming
25
FPGA Programming
25
FPGA Linux Boot
26
FPGA Linux Boot
26
FPGA Linux Boot
27
FPGA Linux Boot
28
FPGA Linux Boot
29
FPGA Linux Boot
30
FPGA Linux Boot
31
FPGA Linux Boot
32
