FPGA Calculator Core

Final Presentation

Chen ZukermanLiran Moskovitch

Advisor : Moshe Porian

Duration: semesterialDecember 2012

Contents

• Project Overview• Top Architecture• Micro Architecture• Testability• Synthesis Results• Hardware Debugging• Project Educational Value• Project Movie• Lab Demo

Project OverviewHardware implementation of calculator core :

• Positive integers

• Operands: ‘+’ , ’-’ , ’x’, ‘^’ , ‘ { ‘ , ‘ } ‘

• Precedence rules compatible

• Manually acquisition Input via Matlab GUI

• Result display + debugging feedback on GUI screen

FPGACalculator Core

Result

Top Architecture

Implemented

integrated

Wis

hbon

e In

terc

on

TX PATH

WN

B2

WBS2

RX PATH

WBM

1

WBS1

CALC_CORE

WBS3

WBM3

Altera Cyclone II FPGA

GUI - MATLAB

Uart Out115200 bits/sec

Uart In 115200 bits/sec

Clock &Reset

FPGA Clock, 50[MHZ]

FPGA Reset

Sys_clk, 100[MHZ]

Sys_reset

Wis

hbon

e In

terc

on

TX PATH

WN

B2

WBS2

RX PATH

WBM

1

WBS1

CALC_CORE

WBS3

WBM3

Altera Cyclone II FPGA

GUI - MATLAB

Uart In 115200 bits/sec

Uart Out115200 bits/sec

Implemented

integrated

Postfix Data..

FF

Infix - Data ..

FF

Result

Type

Address

Data Length

Result

Type

Address

Data Length

Result

SOF

Type

Address

Data Length

CRC

EOF

Data Flow

Clock &Reset

FPGA Clock, 50[MHZ]

FPGA Reset

Sys_clk,100[MHZ]

Sys_reset

SOF

Type

Address

Data Length

Postfix Data..

FF

CRC

EOF

Infix - Data..

FF

Micro Architecture

Calculator Core in action

detailed view

0200070A

1

1

070A

0A

09

090982

0A8209FF

0A

0A

09

09

82 09

09

0A

0A

5A5A

FF

FF 5A

5A

00 00 00 5A

11

03

00

03

1

005A

Testability• Top Level Testing and simulating

environment :

Goals : 1. functionality verification (in system boundaries)2. verification that hardware and software calculation results are equal

• Multi-Level testing environments were implemented

PLL BYPA

SS

PLL Vs. PLL Bypass

• The top level contains PLL unit that produces system clock

• Simulating The top level with PLL unit is slow

• PLL BYPASS

Disables PLL unit and produce system clock manually

Implemented one hierarchy above the PLL unit

in order to get faster simulation time (if … generate)

Choosing between PLL and PLL BYPASS is done by generic

sim_clk_gen_g (if true – PLL is disabled, otherwise enabled)

GUI

Method select

Enter the exercise

Exhibit the data to transmit

Exercise display

Software result

Hardware result

Gui messages

GUI - Capabilities

Operational features:• Receive data from the user• Data abstraction – easy and simple operation• Generates only correct packets with legal values• Method choosing.

Debug features:• Transferred data display• Messages display• Generates text files available for simulation

Operation Table

Select value Hex code Binary code Operation

- 85 10010101 (

- 86 10010110 )

011 83 10000011 ^

010 82 10000010 x

000 80 10000000 +

001 81 10000001 -

- FF 11111111 End of Postfix\infix

Text FilesCalculation string txt file format :• General comment – desired test literally, explanation,

Clarifications etc.• Different notations comment: infix , postfix , postfix in hex + operator

conversion• Data line - full packet calculation string

Postfix data Infix data End of postfix

Wishbone signals

TGA – Client TypeTGD – data lengthADR – Client inner address

SOF CRCEnd of infix EOF• General comment – desired test literally, explanation, Clarifications etc.

Result string txt file format :• Comment : infix notation + result [hex]• Data line – full packet expected result string

Wishbone signals Expected resultSOF EOFCRC

Text File• Calculation string txt file example (4

strings):

String generator + checker

• Allows simple & fast testing and simulation

• Automatic feedback – message in the transcript window

• Working with multiple strings one after the other

String generator + checker example

Full packet calculation stringFull packet result string

String Generator opens the input txt file String Generator closes the input txt file End of successful top level test

String Generator and Checker simulation reports – Transcript Window

Power basic tests:Adder basic tests: Multiplier basic tests:Subtractor basic tests:

Test Plan

• Blocks Basic Tests (inputs/outputs limits and special cases):

• General Tests (inputs/outputs limits and special cases):

Simple string using each operator once

Strings using same operator all along

Strings using different operator in the beginning of the

string

Each operator used twice in a single string

Short string

Long string

Brackets testing (in different location along the string)

Bigger\Smaller Right\Left Operand

• For simulation and hardware as well

Synthesis Results

Max Frequency

• Required frequency : 100 [MHz]• Actual Max frequency : 133.87 [MHz]

Hardware Debugging

• Problem : first programming on FPGA … nothing happens (GUI does not receive the returned full packet result string) .

• Source : The reset button on the DE2 board is active low while the PLL reset polarity (predefined by the MegaWizard) is active high .• Solution : adding the pll_reset signal which insures, that when the FPGA reset button is active ('0'), the PLL reset would be active as well with the appropriate polarity ('1') .• Conclusion :

Fundamental principle - system synthesis MUST come only AFTER successful simulation - Early detection of the problem .

MegaWizard PLL RESET (areset) is always active high ('1'). Special attention should be paid to the reset polarity issue .

Programming indication led could be useful .

• Planning and Specifying a Project

• Writing reusable generic code

• Profound acquaintance with communication protocols : UART,

Wishbone

• Integration of many components

• Verifying logic correctness using smart simulators, waveforms,

text files and scripts (do files)

• Using the GUI for hardware Testing and also as a producer of

text files which are used later by the smart simulators

• Documentation of the work done

• SVN is a very useful tool

• Seriousness, Persistence, spending time and a will to learn and

understand are a Guarantee of success

Project Educational Value

Project Movie

http://www.youtube.com/watch?v=0POkQuCi9Tk

Lab Demo