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PROGRAMMABLE LOGIC DEVICE 1

Fpga Basics

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Some Overview of FPGA

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FPGA BASICS

PROGRAMMABLE LOGIC DEVICE1PLDAn IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different functions is called a Programmable Logic Device 2Programmable logic devices3

PROMs4

PROM example5

PLA6

PAL7

CPLD8PAL-likeblock I/O block PAL-likeblock I/O block PAL-likeblock I/O block PAL-likeblock I/O block Interconnection wires FPGA9FPGA?FIELD PROGRAMMABLE GATE ARRAYSINTEGRATED CIRCUITS(ICS)CONFIGURABLE(PROGRAMABLE)10Elements of FPGAFPGA mainly consist of three elementsCombinational logicsInterconnectsI/O pins

11

CONT..12

Field programmableProgramming in the FIELD Modify device function in the lab.At the site where device is installed.13IMPORTANT POINTS Inexpensive , easy realization of logic networks in hardware ->as easy as software This can be used in academicsStudents can use to verify logic networks in hardwareHardware of FPGA contains PLDsLogic gates -> xor gates, nand gatesRAMOthers ->DCM

14CONTDifferences

Physical means of implementing programmability.Interconnection arrangementsBasic functionality of logic blocks16example1a b f0 0 10 1 0 0 1 11 1 0aba and b acts like memory address pointer101018example2Y = a & b | !cabyc19example321

CONT.22

CONT..

A transmission gate based LUT23PRAGRAMMABILITY?Three programming methodsSRAM based XILINK,ALTERAAntifuse technology ACTEL,QUICK LOGICEPROM/EEPROM NOT VERY COMMONLY SEEN

2424SRAM based programmingPass transistorsTransmission gatesmultiplexers25CONT.Making or braking cross point connection2626CONTSRAMSRAMSRAM2701CONT.LUTFFSRAM2801CONT.

IMPLEMENT

BIT files29ANTIFUSE TECHNOLOGYOne time programmableLinks in configurable pathsHigh resistance(un programmed) open circuit30CONTmetal1metal2Oxide layerNon conducting siliconConducting siliconBefore programmingafter programming31Why antifuse?Antifuse SRAMLess area extra areaHigh speed delays are high32

CONT.Micro processorDSP processorFPGA33ROUTING CHANNELS

34CONT..35

VIRTEX 36

CLBS IN VIRTEX One CLB consist of two slices37CLBSLICESLICESLICE CONSIST OF?Two 4-input function generatorsCarry logicTwo storage elements

38CONT.39

IOBsStorage elementsFF/LATCHMODESynchronous set/resetAsynchronous preset/clear

CONFIGUREInput pathOutput path

40CONT.

41RAM BLOCKS

42Clock trees and clock managersClock trees43

Clock managers44

DCMJitter removalFrequency synthesisPhase shiftingAuto-skew correction45DCMJitter removal46

DCMFrequency synthesis47

PROGRAMMABLE INTERCONNECTSAdjacent to each CLB stands a GRMConnect resources such as CLB/RAM/Multiplier/adders/counters48

DCMPhase shifting49

DCM50

Configurable I/O standards51

WHERE DO FPGA LIES? IC

PLDS ASICS SPLDS CPLDS 52Structured ASICStandard cellsFull customPROGRAMMABLEONE TIME PROGRAMMABLEHighly configurableFast design timeCant support complex logicNo reconfigurationTime consumingExpensiveSupport complex logic FPGAFPGA GENERIC DESIGN FLOW53Design entryDesign implementationDesign verificationsimulatorLogic analyzerFPGA GENERIC DESIGN FLOW54Design requirementsDesign entry through RTL/schematic entrysynthesistranslateDetailed DesignMapping, Place & routeStatic timing analysisBit file generationAdd/modify constraints55

CONT.Design entry simulators ----->ISEsim,modelsim .v/.vhd/.schSynthesisXilink synthesis tool(XST)Produces an netlist file from an HDL/schematic descriptionConverts .v/.vhd/.sch ---->.ngc file(netlist file)Translate NGD(native generic database) buildReads all input design netlist and writes the result in to a single merged file that describes logic and contraints.Converts .ngc ---->.ngd

56NGDif use mux,adder then it will merge in to one file56CONT..MAPPINGMaps the logic on deviceGenerate NCD and PCF file

NCD(native circuit description file) Represents the physical circuit description of the input design as applied to a specific Device

PCF(Physical constraint file)

Place and route

Static timing analysis

57Maps translated logic to the deviceIt take the netlist and groups netlist in to CLBS and IOBsMapping is device dependent57CONT.Bit stream generation

Configuration /programming

58Modulo 4 counter5900101101En=0En=0En=0En=0En=1En=1En=1En=1

Truth table60Enable X1 X2 y1 y20 0 0 0 00 0 1 0 10 1 0 1 00 1 1 1 11 0 0 0 1 1 0 1 1 01 1 0 1 11 1 1 0 0Present statenext stateCONT.61

61CONT.62

INTRODUCTION TO XILINX ISEINTEGRATED SOFTWARE ENVIRONMENTIntegrated collection of tools accessible to GUISupports all the steps required to complete the design.Example ---> XST, PACE, COREGEN, constraint editor, impactSimulators --->XILINK ISEsim,modelsimHDL compiler--- > XSTCore generator and architecture wizard---- > coregenPinout and area constraint editor ---- > PACEImplementation-- >translate/MAP/PARDevice configuration ---- > impact

63Tool provided by xilink to configure fpga provided by xilink63Why FPGA?Inexpensive, easy ,programmable ,time to market.Glue logicGenerating global control signal(reset)Data formattingReduced system complexity, manufacturing cost.64Why manufacturing cost?65Volume of productioncostASICFPGANRE costCOMPARISON66performanceNRESUnit costTTMASICASICFPGAASICFPGAFPGAMPFPGAMPMPASICMP THANK YOU67


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