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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Gate Design
Static complementary logic gate structures. Switch logic. Other Gate issues
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Static complementary gates
Complementary– have complementary pullup (p-type) and
pulldown (n-type) networks. Static
– do not rely on stored charge. Advantage of Static complementary gates
– Simple, effective, reliable; hence ubiquitous.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Static complementary gate structure
Pullup and pulldown networks:
pullupNetwork(P type)
pulldownNetwork(N type)
VDD
VSS
outinputs
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Inverter
If the input voltage is '1' (VCC) – P-type transistor on
top is nonconducting
– N-type transistor is conducting and provides a path from GND to the output.
– The output therefore is '0'.
a out
+
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
NAND gate
+
ba
out
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
NOR gate
+
b
a
out
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
AOI/OAI gates
AOI – and/or/invert
OAI– or/and/invert.
Why ?– Implement larger functions.– Pullup and pulldown networks are compact: – smaller area, higher speed than NAND/NOR network equivalents.
AOI312– and 3 inputs, and 1 input (dummy), and 2 inputs; or together these
terms; then invert.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
AOI example
out = [ab+c]’:
symbol circuit
and
or
invert
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Pullup/pulldown network design
Pullup and pulldown– Networks are duals.
To design one gate– First design one network
– Then compute dual to get other network.
Example: – design network which
» pulls down when output should be 0
– then find dual to get pullup network
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Dual network construction
dum
my
a
b c
dummy
a
b c
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch logic
Can implement Boolean formulas– as networks of switches.
Can build switches– from MOS transistors—transmission gates.
Transmission gates– do not amplify but have smaller layouts.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch logic network
a
b
0
1
a b out
0 0 X
0 1 1
1 0 0
1 1 X
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Another switch logic network
a
b
r
s
a b out
0 0 X
0 1 r
1 0 s
1 1 X
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch-based mux
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Types of switches
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Behavior of n-type switch
n-type switch has source-drain voltage drop when conducting:
» conducts logic 0 perfectly;
» introduces threshold drop into logic 1.
VDD
VDD
VDD - Vt
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
n-type switch driving static logic
Switch underdrives static gate, but gate restores logic levels.
VDD
VDD
VDD - Vt
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
n-type switch driving switch logic
Voltage drop causes next stage to be turned on weakly.
VDD VDD - Vt
VDD
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Behavior of complementary switch
Complementary switch – Products full-supply voltages for both logic 0
and logic 1:» n-type transistor conducts logic 0;
» p-type transistor conducts logic 1.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Charge sharing
Values are stored at parasitic capacitances on wires:
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Charge sharing example
1
1
00 0
1 1
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
DCSL gate
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
MTCMOS gate
