© 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

FPGA Academy I

Vivado 2014.1August 2014 Course Specification

LANG11000-13-ILT (v1.0) updated August 27, 2013 www.xilinx.com

Course Specification 1-800-255-7778

Xilinx Academy I Description:

The Academy I course consists of 3 packaged courses including:

Designing with VHDL (3 days)

Essentials of FPGA Design (2 Day)

Price:

Classroom Learning $2995 + GST (30 TCs)

Live Interactive Online: $2495 + GST (30 TCs)

A Digilent Demo Board may be purchased with an Academic discount when attending this course. See the end of this brochure for details.

Designing With VHDL This comprehensive course is a thorough introduction to the VHDL

language. The emphasis is on writing solid synthesizable code and

enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This

class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design

by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key

concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced

VHDL course.

In this three-day course, you will gain valuable hands-on experience. Incoming students with l ittle or no VHDL knowledge will finish this

course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Course Duration – 3 days

Who Should Attend? – Engineers who want to use VHDL effectively

for modeling, design, and synthesis of digital designs

Prerequisites

▪ Basic digital design knowledge

Software Tools

▪ Vivado® Design or System Edition 2014.1

After completing this comprehensive training, you will have the

necessary skil ls to:

▪ Implement the VHDL portion of coding for synthesis

▪ Identify the differences between behavioral and structural coding styles

▪ Distinguish coding for synthesis versus coding for simulation

▪ Use scalar and composite data types to represent information

▪ Use concurrent and sequential control structure to regulate information flow

▪ Implement common VHDL constructs (Finite State Machines

[FSMs], RAM/ROM data structures)

▪ Simulate a basic VHDL design

▪ Write a VHDL testbench and identify simulation-only constructs

▪ Identify and implement coding best practices

▪ Optimize VHDL code to target specific sil icon resources within the

Xilinx FPGA

▪ Create and manage designs within the Vivado Design Suite environment

Course Outline

Day 1

▪ The "Shape" of VHDL

▪ Lab 1: Using the Tools

▪ Documentation in VHDL

▪ Data Types

▪ Concurrent Operations

▪ Lab 2: Using Concurrent Statements

▪ Processes and Variables

▪ Lab 3: Designing a Simple Process

Day 2

▪ Introduction to Testbenches

▪ ISim Simulation Tool Basics

▪ Lab 4: Simulating a Simple Design

▪ Creating Memory

▪ Lab 5: Building a Dual-Port Memory

▪ Finite State Machines

▪ Lab 6: Building a Moore Finite State Machine

▪ Targeting Xilinx FPGAs

▪ Lab 7: Xil inx Tool Flow

Day 3

▪ Loops and Conditional Elaboration

▪ Lab 8: Using Loops

▪ Attributes

▪ Functions and Procedures

▪ Packages and Libraries

▪ Lab 9: Building Your Own Package

▪ Interacting with the Simulation

▪ Writing a Good Testbench

▪ Lab 10: Building a Meaningful Testbench

Lab Descriptions The labs for this course provide a practical foundation for creating

synthesizable RTL code. All aspects of the design flow are covered in

the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer

reliable and high-performance circuits.

Essentials of FPGA Design Build an effective FPGA design using synchronous design techniques,

instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing

constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.

Course Duration – 2 days

Who Should Attend? – Digital designers who have some knowledge of

HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

▪ Working HDL knowledge (or attending Academy I part 1)

▪ Digital design experience useful

Software Tools

▪ Vivado Design or System Edition 2014.1

Hardware

▪ Demo board: Kintex®-7 FPGA KC705 board**

© 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

FPGA Academy I

Vivado 2014.1August 2014 Course Specification

LANG11000-13-ILT (v1.0) updated August 27, 2013 www.xilinx.com

Course Specification 1-800-255-7778

After completing this comprehensive training, you will have the

necessary skil ls to:

▪ Take advantage of the primary 7 series FPGA architecture resources

▪ Use the Project Manager to start a new project

▪ Identify the available Vivado IDE design flows (project based and non-project batch)

▪ Identify fi le sets (HDL, XDC, simulation)

▪ Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer

▪ Synthesize and implement an HDL design

▪ Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)

▪ Build custom IP with the IP Library utility

▪ Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)

▪ Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and

report_timing_summary)

▪ Describe and analyze common STA reports

▪ Identify synchronous design techniques

▪ Describe how an FPGA is configured

Course Outline Day 1

▪ Design Methodology Summary

▪ Basic FPGA Architecture

▪ Introduction to the Vivado Design Suite

▪ Vivado Design Flows

▪ Lab 1: Vivado Tool Overview

▪ Visualization for Analysis

▪ Designing with IP

▪ Basic Timing Constraints and Reports

▪ Lab 2: Vivado Synthesis, Implementation, and Timing Closure

Day 2

▪ Designing with FPGA Resources

▪ Clocking Resources

▪ Lab 3a: Designing with FPGA Resources

▪ Lab 3b: Designing with IP – IP Integrator Flow

▪ Basic Timing Constraints (XDC)

▪ Timing Reports

▪ Lab 4: Basic XDC and Timing Reports

▪ Synchronous Design Techniques

▪ FPGA Configuration

Lab Descriptions ▪ Lab 1: Vivado Tool Overview – Create a project in the Vivado

Design Suite. Add fi les, simulate, and elaborate the design. Review the available reports, analyze the design with the

Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.

▪ Lab 2: Vivado Synthesis, Implementation, and Timing Closure – Synthesize and analyze the design with the Schematic viewer, apply a systematic approach to applying timing constraints and

timing closure (i.e., understand the Xilinx baselining recommendation). Run basic static timing analysis using the

check_timing and report_clock_utilization reports. Implement the design and analyze some timing-critical paths with

the Schematic viewer. Download the bitstream to the demonstration board.

▪ Lab 3a: Designing with FPGA Resources – Use the Xilinx Clocking Wizard to configure a clocking subsystem to provide

various clock outputs and clock buffers to connect clock signals to global clock networks.

▪ Lab 3b: Designing with IP – IP Integrator Flow – Use the IP Vivado IP integrator to create a subsystem for a design. Generate the output products of the subsystem.

▪ Lab 4: Basic XDC and Timing Reports – Use timing constraints to improve design performance. Perform static timing analysis before and after implementation to validate the performance

results.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand, and live, instructor led training

to attendee’s worldwide via a browser based delivery solution, using world class instructors based around the world.

Black Box Consulting is the sole Authorized Xilinx Training Provider for

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For more information, such as our range of courses, current schedules,

and other services including consulting and training packages, please use one of the contact methods below:

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Tel: + 61 7 3137 0905 Fax: +61 7 3 3103 4297

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