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Forward Calorimeter Layer Sum BoardsPhase I UpgradeLAr Internal Review
J. Rutherfoord29 May 2015
23 September 2014 J. Rutherfoord 2
FCal LSBs for Phase I
Goals of the Phase I upgradeDescription of the baselinePresent status
J. Rutherfoord 3
One FCal1 -slice
28 May 2015
Now
Proposed
Now just 4 trigger towers per -slice
Will be 12 trigger towers per -slice
FCal front-end is different
Trigger summing No summing in depth All LSB inputs are individually weighted
by sin() – Of order 10 variation
23 September 2014 J. Rutherfoord 4
FCal Layer Sum Bds
Layer Sum Boards will provide finer segmentation, i.e. less summing.Will maintain legacy summing
23 September 2014 J. Rutherfoord 5
Layer Sum Board
FCal1 LSB Schematic
23 September 2014 J. Rutherfoord 6
FCal1 Phase I Layer Sum Board
23 September 2014 J. Rutherfoord 7
23 September 2014 J. Rutherfoord 8
Dynamic range
Table is everywhere in units of ET
In FCal, kinematic limit determined at s = 14 TeVChoose pT = 512 GeV as upper limit for all FCal trigger towers for now No saturation!Use shaper linear mixer output upper limit of 3.0 VSet linear mixer gains as low, hi, hi
Resistor values assuming 512 GeV pT and linear mixer 3.00 V
23 September 2014 J. Rutherfoord 9
Test (dummy) boards
Front-End Board (with LSB slots)Calibration board Input from pulse generator to mux
which drives 128 lines
LTDB with mux from inputs to output to digital scope
23 September 2014 J. Rutherfoord 10
“Dummy” Front End Board layout
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FCal1 prototype Phase 1 LSB
23 September 2014 J. Rutherfoord 12
Input: pin 02Output: pin 49
Rise: 35 nsAmp: 2.5 Vpp
Only one power and one ground pin connected for this test.
100 ns
2.5 V
FCal1 LSB prototype: Normal x-talk
23 September 2014 J. Rutherfoord 13
Input: 2.5 VppOutput: 3 mVpp
0.1% x-talk
100 ns
5 mV
2.5 V
FCal1 LSBOnly case of bad x-talk
23 September 2014 J. Rutherfoord 14
Input: 2.5 VppOutput: 50 mVpp
2% x-talk
100 ns
50 mV
2.5 V
23 September 2014 J. Rutherfoord 15
Present status
FCal1 LSB pcb stuffed and tested Flaw – One channel in one location has
cross-talk exceeding specs. Easy to fix. Possible mix-up on which pair to sum.
Three dummy FEB pcbs stuffed – ready to test
