Foreword - · PDF fileI-2 Foreword I-1 Introduction to EPTC I-9 Organizing Committee I-10 Technical Committees I-12 Keynote Address I-16 Panel Session I-21 Professional

I-1

Foreword

The Organizing and Technical Committees of the Electronics Packaging Technology Conference (EPTC) welcome you to the18th event at the Suntec Singapore Convention &Exhibition Centre, Singapore. This premier international conference is organ-ized by the Reliability/CPMT/ED Singapore Chapter of the IEEE Singapore Section and sponsored by the IEEE Components,Packaging and Manufacturing Technology Society (CPMT).

EPTC 2016 consists of technical program, professional development courses, and technology exhibition corner. Over 195 highquality technical papers will be presented in 35 oral sessions and 2 interactive sessions. Technical papers and participations fromindustries, research institutes, and universities in nearly 22 countries make EPTC 2016 a truly global packaging conference. Theprogram covers a wide spectrum of topics, including advanced packaging, interconnect technologies, wafer level packaging,materials, processing, assembly, manufacturing, quality, reliability, modelling, and simulation.

In addition to the technical sessions, an evening panel session chaired by Prof. Zhu Wenhui (Suzhou Speed Semiconductor tech-nology Co., Ltd.) is organized to discuss about “Rise of China Semiconductor” covering the topics “Semiconductor industrystatistics and projections in China, Government policies, Supply chain, Semiconductor manufacturing and Packaging technolo-gies, Opportunities & Challenges for China and for other countries/areas”. Six professional development courses will beconducted on 30 November 2016 by experts from Industry and academia. It is an opportunity for the participants to learn newtechnologies and broaden their knowledge base. Also, there will be an exhibition corner from leading semiconductor compa-nies showcasing their latest technologies and products. Exhibit hours are 08:30 to 16:30 hrs on 1st to 2nd December 2016 and3rd December visit to SUTD,campus tour (Cohort classroom, ARMS lab, Fab Lab, IDC and DManD).

This is another great opportunity to network and discuss technical and business matters.

EPTC 2016 will have six keynotes deliberating on technology trends/advancement by Kanji OTSUKA, Meisei University;Jagadish CV, Systems on Silicon Manufacturing Company Pte Ltd; Tom Dolbear, AMD; Wenhui Zhu, Central South University,China; Shi-Wei Ricky Lee, Professor of Mechanical & Aerospace Engineering, HKUST, Director of Center for AdvancedMicrosystems Packaging, Director of HKUST LED-FPD Technology R&D Center at Foshan; and Bill Chen, ASE Group.

We thank our corporate sponsors Lam Research, SPIL, PacTech, Indium, Applied Materials, ASM Technology, Accurus, NihonSuperior, SPTS, Kulicke&Soffa, ASE Group and Supporting Agency Workforce Singapore fortheir generous gesture in promotingtechnical events such as EPTC. We appreciate our partnering publishers : Springer & WSPC for their books contribution, partner-ing associations: AEIS, SSIA,SSEA, media partners : Solid State, MEMS Journal , Yole for publicity and promotion of EPTC.

Also thank the authors, speakers, professional development course instructors, session chairs, committee members, board mem-bers, conference secretary, website management team, souvenir sponsor, publicity team, suppliers & vendors as well as all theconference Associates & volunteers for their support and hard work. We also thank all conference delegates for making the eventa success. We hope the 18th Electronics Packaging Technology Conference (EPTC 2016) in vibrant Singapore is an informa-tive and memorable event, and we are grateful for your feedback.

Gaining knowledge, is the first step to wisdom.Sharing it, is the first step to humanity.

– Unknown

General ChairMr. RANJAN Rajoo

GLOBALFOUNDRIES

Technical ChairDr. ZHANG Xueren

Program ChairDr. YOON Seung Wook

Stats Chippac

eptc2016-pbk.qxd 28/11/2016 2:43 PM Page I-1

Xilinx

I-2

Foreword I-1

Introduction to EPTC I-9

Organizing Committee I-10

Technical Committees I-12

Keynote Address I-16

Panel Session I-21

Professional Development Courses I-23

Invited Presentations I-30

Sponsors I-48

Partnerships I-53

Exhibitors I-57

General Floor Plan – LEVEL 3 I-61

Conference Venue I-62

Conference Hotel I-63

Conference Location I-64

SUTD Visit I-65

General Information I-68

About Singapore I-69

Conference Banquet I-71

Technical Sessions 1

Wednesday, 30th November 2016 1

Thursday, 1st December 2016 2

Friday, 2nd December 2016 19

Saturday, 3rd December 2016 47

Author Index 48

Contents



Ball Drop

DEK Galaxy

LASER1205(UV Grooving)

LASER1205(UV Dicing)

SUNBIRD

Encapsulation

Singulation

Test and Finishing

Low-K Grooving

Large Format Packaging Solutions

www.asmpacific.com

FLOWlineFLOWlineTMTM

ORCAS

Flexi-test Laser ORCAS for WLP package line

Pick &PlacePick &Place

SIPLACE CA

NUCLEUSWafe

r Lev

el

Fan O

ut


©2016 Indium Corporation

A S I A • C H I N A • E U R O P E • U S A

Please contact Irene Leow at: [email protected] more: www.indium.com/EPTC

From One Engineer To Another®

Soldering Materials forSystem-in-Package (SiP)

System-in-PackageLidded MEMS

3D Logic / Memory and Flip-chip

Lidded MEMSy p p

Embedded Active and Passive Devices

Wafer Level CSPUltra-small Passives

Ball Grid

Array

Wafer Level Ball-Attach Flux• Water-soluble• Halogen-free

Ultrafine-Pitch Solder Paste• Water-soluble and

ultra-low residue no-clean • Halogen-free

Dispensable Fine-Pitch Solder Paste• Solvent cleanable• Halogen-free

Ball-Attach Flux• Water-soluble• Pin transfer and printing• Halogen-free

Flip-Chip Flux• Water-soluble and

ultra-low residue no-clean• Dipping, spraying, and jetting• Halogen-free and halogenated

Wafer Bumping (Bump Fusion) Flux• Water-soluble• Spin-on and jetting• Halogen-free


www.pactech.com

PacTech USA Inc.328 Martin Avenue, Santa Clara, CA 95050, USA

PacTech Asia Sdn. Bhd.No 14, Medan Bayan Lepas, Technoplex, Phase 4 Bayan Lepas Industrial Zone, 11900 Bayan Lepas,Penang, Malaysia

PacTech - Packaging Technologies GmbHAm Schlangenhorst 15-17, 14641 Nauen, Germany

Global Services forWafer Level Packaging

ElectroplatingWafer Level Redistribution, Cu Pillars, NiFe for MEMS

Solder Rework & Reballingfor 4”-12” Wafers, BGA, CSP, LGA, CLCC, PCB, MEMS ...,No Tooling Required

Electroless NiAu &NiPdAu UBMNiAu for Low Cost Bumping, High Reliability NiPdAu,Cu & Au Wire Bonding

Solder Ball Bumping6”-12” Wafers,for WLCSP and FlipChip applications

Wafer Backend ServicesBackside Metallization, Thinning and Dicing,Tape & Reel

Contact us at [email protected]

ISO 9001ISO TS 16949

ISO 14001




The 18th Electronics Packaging Technology Conference (EPTC 2016) is an International event organized by theIEEE Reliability/CPMT/ED Singapore Chapter and sponsored by IEEE CPMT Society.

EPTC 2016 will feature technical sessions, short courses/forums, an exhibition, social and networking activities.

It aims to provide a good coverage of technological developments in all areas of electronic packaging from designto manufacturing and operation. It is a major forum for the exchange of knowledge and provides opportunities tonetwork and meet leading experts in the field.

Since its inauguration in 1997, EPTC has developed into a highly reputed electronics packaging conference in Asiaand is well attended by experts in all aspects related to packaging technology from all over the world.

• Advanced Packaging: Flip-chip, multiple array leadframepackage, POP, System in Packaging, etc.• TSV/Wafer Level Packaging:Fan-in/Fan-out, embedded chip packaging, 2.5D/3D integration, TSV, Silicon

& Glass interposer, RDL, bumping technologies, etc.• Interconnection Technologies: Au/Ag/Cu/Al Wire-bond technology, Flip-chip & Cu pillar technology, sol-

deralternatives, Wafer level bonding & die attachment etc. • Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, Internet of things,

photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc.• Materials and Substrates/Leadframes: from polymer to solder materials, and Substrates / Interposer /

Leadframes / PCB etc. • Processes and Automation/Equipments: new process as well as equipment automation development. • Electrical Modeling & Simulations:Power plane modeling, signal integrity analysis of substrate/package.• Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, shock and

dropmodeling, Chip-package interaction, etc.• Thermal Characterization & Cooling Solutions: Component, system and product level thermal management,

characterization and simulation• Quality & Reliability:Component, board, system and product level reliability assessment, Interfacial adhesion,

accelerated testing, failure characterization, etc.• Wafer/Package level & TSV Testing and Characterization: High-speed test architectures and systems design,

2.5D & 3D test methodologies, probe card design, package-test interaction, high-throughput testing etc. • Others are also welcomed, e.g. market trends, environmental conscious, legislation, patents, education, and

cost analysis.

EPTC Past General Chairs

EPTC Year Past General Chairs Venue

1st 1997 Prof Andrew Tay Pan Pacific Hotel2nd 1998 Prof Andrew Tay Raffles City Convention Centre3rd 2000 Dr Thiam Beng Lim Sheraton Towers4th 2002 Mr Charles Lee Grand Copthorne Waterfront Hotel5th 2003 Dr Mahadevan Iyer Pan Pacific Hotel6th 2004 Prof Kok Chuan Toh Pan Pacific Hotel7th 2005 Mr Yew Cheong Mui Grand Copthorne Waterfront Hotel8th 2006 Prof John Pang Pan Pacific Hotel9th 2007 Dr Kripesh Vaidyanathan Grand Copthorne Waterfront Hotel

10th 2008 Dr Tong Yan Tee Grand Copthorne Waterfront Hotel11th 2009 Mr James How Shangri-La Hotel12th 2010 Dr Yoon Seung Yoon Shangri-La Hotel13th 2011 Dr Albert Lu Shangri-La Hotel14th 2012 Mr Navas Khan Resorts World Sentosa15th 2013 Mr Ashok Anand Resorts World Sentosa16th 2014 Mr Alfred Yeo Marina Bay Sands17th 2015 Mr Chin Hui Choong Marina Mandarin

I-9

Introduction to EPTC


I-10

Organizing Committee

General ChairMr. RANJAN Rajoo

GLOBALFOUNDRIES

Past General ChairMr. CHONG Chin HuiMicron Semiconductor

Technical ChairDr. ZHANG Xueren

Program ChairDr. YOON Seung Wook

Stats Chippac

Facilities ChairDr. NG Hong Wan

Micron Semiconductor

Professional Development Course ChairDr. Riko I MADE

Singapore-MIT Alliance for Researchand Technology

Finance ChairDr. TOH Chin Hock


Xilinx

I-11

Organizing Committee

Committee MemberMr. Vempati Srinivas Rao

IME, A*star

Committee MemberDr.JUNG Boo Yang

Global Foundries, Singapore

Committee MemberMs. Adeline LIM

K&S

Committee MemberMr. WONG Wui Weng

AMD (S) Pte Ltd

Committee MemberMr. YANG Yong Bo

Infineon

Professor Andrew TaySingapore University of Technology and Design

EPTC BOARD

Mr. Ra. SankaranResearch Publishing, Singapore (RPS)

Secretariat & Conference Management System


I-12

Technical Committees

T1 Advanced Packaging

Chair Navas Khan NXP SemiconductorCo-chair Rainer Dudek Fraunhofer ENASMember V.P. Ganesh Infineon TechnologiesMember Aditya Kumar GLOBALFOUNDRIESMember Jean-Charles Souriau LETIMember Vempati Srinivas Institute of MicroelectronicsMember C.S. Foong NXP SemiconductorMember Bok Eng Cheah Intel MicroelectronicsMember KIM Hyoung Joon Samsung Electro-Mechanics (SEMCO)Member Jatinder Kumar SemtechMember Chris Bae SamsungNew Member Vasarla Nagendra Sekhar Institute of Microelectronics

T2: TSV/Wafer Level Packaging

Chair Dr. YOON Seung Wook Statschippac Pte LTDCo-Chair Dr. Mark Huang Suzhou SPEED Semiconductor Tech.nology Pte Ltd), ChinaMember Mr. Ranjan Rajoo Global Foundries, SingaporeMember Dr. CHEN Kuoming UMC, TaiwanMember Dr. GAURAV Sharma Global Foundries, USMember Mr. YANG Seung Taek SK Hynix Semiconductor, KoreaMember Mr. KIDA Tsuyoshi MGC, JapanMember Dr. Lee Jaesik Oracle, USMember Mr. JIN Yong GangMember Dr. Mingliang Huang Dalian University of Technology, ChinaMember Mr. John Hunt ASE, USMember Dr. Jung Boo Yang Global Foundries, SingaporeMember Mr. Thorsten Meyer Infineon AG, GermanyMember Mr. Yann Guillou Semi EuropeNew Member Kroehnert Steffen Nanium, PortugalNew Member Mr. Santosh Kumar Yole Development,France

T3: Interconnect Technologies

Chair David Hutt Loughborough UniversityCo-chair Liming Shen Kulicke & Soffa, SingaporeMember Horst Clauberg KnSMember Wei Fan Singapore Institute of Manufacturing TechnologyMember Hong Meng Ho STATS ChipPAC, SingaporeMember James How SingaporeMember Poi Siong Teo Infineon Technologies Asia Pacific, SingaporeMember John Lau ASMTMember Yew Cheong Mui Advanced Micro Devices, Singapore


I-13


Member Nga Phuong Pham IMEC, BelgiumMember Daquan Yu Chinese Academy of Science, ChinaMember Jack Xiong Qorvo, SingaporeNew member Tanemasa Asano Kyushu UniversityNew member Kyung W. Paik KAIST

T4: Emerging Technologies

Chair Kripesh Vaidyanathan ITE, SingaporeCo-chair Martin Oppermann Dresden University of TechnologyMember Perceval Coudrain STMicroelectronicsMember Andreas Fix Robert Bosch GmbHMember Matthias Hutter Fraunhofer Institute for Reliability and MicrointegrationMember Toni Mattila Aalto University EspooMember James E Morris Portland State UniversityMember Nga Phuong Pham IMECMember Wolfgang Reinert Fraunhofer Institute for Silicon TechnologyMember Thomas Zerna Dresden University of TechnologyNew member Riko I Made Singapore MIT Alliance for Research and TechnologyNew member Yufeng Yao Broadcom Ltd (Avago Technologies)New member Rama Krishna Kotlanka Analog Devices, USA

T5: Materials and Substrates/Leadframes

Chair Dr Chin Hock Toh SingaporeCo-chair Dr Won Kyoung Choi STATS ChipPAC Ltd, SingaporeMember Prof. Robert Gao National Taiwan University, TaiwanMember Jun Dimaano United Test & Assembly Center Limited, SingaporeMember Prof. Chee Lip Gan Nanyang Technological University, SingaporeMember Prof. Sungdong Kim Seoul National University of Science & Technology, KoreaMember Dr Kim Shyong Siow University Kebangsaan Malaysia, MalaysiaMember Alvin Lee Brewer Science, TaiwanMember Prof. Changqing Liu Loughborough University, UKMember Prof. Young-Bae Park Andong National University, South KoreaMember Dr Lim Chong Sim Robert Bosch Sdn Bhd, MalaysiaMember Prof. Chuan Seng Tan Nanyang Technological University, SingaporeMember Bart Vandevelde IMEC, BelgiumMember Vempati Srinivasa Rao IME, SingaporeMember Dr Jun Wei Singapore Institute of Manufacturing Technology, SingaporeMember John Oviso PEP Innovation Pte Ltd, SingaporeMember Chin-Yu (Max) Lu Siliconware Precision Industries Ltd, TaiwanMember Dr Suan Hui Pu University of Southampton, MalaysiaMember Chunte Tu Accurus, Taiwan


I-14


T6: Electrical Modeling & Simulations

Chair Wui Weng Wong AMDCo-chair Mihai Rotaru U. of Southampton, U.K.Member Aoyagi Masahiro AIST, JapanMember Weerasekera Roshan University of the West of England (UWE)Member Xiang Yin Zeng Avago TechnologiesMember Chee Parng Chua Jabil Circuit, SingaporeMember Engin Ege San Diego State University , USAMember Fujiang Lin USTC, ChinaMember Jianyong Xie Intel Assembly & Test Techology Development, PheonixMember Chetan Verma Freescale, IndiaMember Mattew Shajan Global Foundries, SingaporeMember Jackson Kong Intel, Malaysia

T7: Mechanical Modeling & Simulations

Chair Andrew Tay Singapore of Technology and DesignCo-chair Shan Gao GLOBALFOUNDRIES, USAMember Ephraim Suhir Portland State University, USAMember Daoguo Yang Guilin University of Electronic Technology, ChinaMember Suresh Sitaraman Georgia Institute of Technology, USAMember Kuo Ning Chiang National Tsing Hua University,TaiwanMember Leo Ernst Ernst ConsultantMember Yong Liu Fairchild, USAMember Juergen Auersperg Fraunhofer ENAS, GermanyMember Wei Zhou Micron, SingaporeMember Azhar Aripin On Semi, MalaysiaMember Eric Yong Infineon Technologies Asia Pacific, SingaporeMember Premachandran CS GlobalfoundriesMember Xiaowu Zhang Institute of Microelectronics,SingaporeMember Christopher Bailey University of Greenwich, UKMember Rathin Mandal Advanced Micro Devices Singapore, Singapore

T8: Thermal Characterization & Cooling Solutions

Chair Rathin Mandal Advanced Micro Devices Singapore, SingaporeCo-chair Marta Rencz Mentor Graphics – MicReD, HungaryMember Wataru Nakayama Therm Tech International, JapanMember Yogendra Joshi Georgia Institute of Technology, USAMember Sandeep Tonapi Anveshak Technology and Knowledge Solutions, USAMember Justin A. Weibel Purdue University, USAMember Yong Jiun Lee CAD-IT Consultants (Asia) Pte Ltd, SingaporeMember Yong Sheng Chua DSO National Laboratories, Singapore


University

I-15

Member Melvin Tan Siow Pin Continental Automotive Singapore Pte Ltd, SingaporeNew member Edwin Teo Nanyang Technological University, SingaporeNew member Hengyun Zhang Shanghai University of Engineering Science, ChinaNew member Marcin Janicki Lodz University of Technology, PolandNew member Yong Han Institute of Microelectronics (A-star), Singapore

T9: Quality & Reliability

Chair Alfred Yeo Infineon, SingaporeCo-Chair Tong Yan Tee SMARTS Enterprise, SingaporeMember Christian Birzer Infineon Technologies, GermanyMember Liqiang Cao Chinese Academy of Science, ChinaMember Xuejun Fan Lamar University , United StatesMember Yi-Shao Lai ASE, TaiwanMember Stefano Mariani Politecnico di Milano, ItalyMember Keith Newman Hewlett Packard, United StatesMember Hong Wan Ng Micron, SingaporeMember Shaw Fong Wong Intel, MalaysiaMember Chong Chin Hui Micron, Singapore

T10: Wafer/Package Level & TSV Testing & Characterization

Chair Bruce Kim City University of New YorkCo-chair Sang-Bock Cho University of Ulsan, South KoreaNew member Prem Chahal Michigan State UniversityMember Sungho Kang Yonsei University, KoreaMember En-Xiao Liu Institute of High Performance Computing, SingaporeMember Sock-Ho Noh Andong National University, KoreaMember Abhilash Goyal Oracle (Sun Microsystems) USAMember Xiaoxiong Gu (Kevin) IBM T.J. Watson Research Center, NY, USAMember Li Li Cisco IncMember Nanju Na IBMMember Seungbae Park The State University of New York at BinghamtonMember W. L. Chong Advanced Micro Devices, SingaporeNew Member Santosh Kumar Yole Développement

T11: Processes and Automation/Equipments:

Chair James How SingaporeCo-chair Dr He Yunbo Guangdong University of TechnologiesNew Member Lee, Chee Ping LAM ResearchNew Member Dr Xu Hui K&STransferred from Dr Loke Yuen Wong Applied Materials, Singapore

TC5



I-16

Keynote Address

Keynote IPackaging Matters by Mr. Tom Dolbear, AMDDate / Time Thursday, 1 December 2016 / 09.00 to 09.30 hrs (30 minutes)Venue MR331-332, Level 3

AMD historically was primarily in the business of designing computer processors. Today, its business is diversifiedinto three operating segments: computing, graphics, and enterprise, embedded and semi-custom. The computingand graphics segments design processors and graphics cards that are incorporated into the laptops and desktop com-puters. The enterprise, embedded and semi-custom segment designs processors for servers and “embedded”devices, as well as semi-customized processors for the gaming market. The market shift for increased mobility andenergy-efficiency has motivated the company to diversify into new markets. Multiple driving factors of new prod-ucts include increasing processing speeds and graphics fidelity, 4K video, virtual and augmented reality , conformingto unique size of new devices, and higher reliability requirements.

AMD has developed “System-on-Chip” (SoC) solutions combining a CPU and GPU onto a single silicon device.The unique requirements of each segment offer opportunities and challenges to semiconductor packaging. Thepackaging technology strategies have to accommodate low cost solutions using standard packaging solutions wherepossible to advanced technologies for product differentiation. Examples of product differentiation include thin andsmall packages for mobility, large packages for high density and high functionality, thin core substrates, Si inter-posers, and high density organic interconnect. This keynote will address the packaging challenges and the strategiesto overcome the diverse and complex demands on development, characterization, and high-volume manufacturing.

Tom is an Senior Director and AMD Fellow in the Thermal/Mechanical/ PackageEngineering organization within AMD. He and his team are responsible for the design, devel-opment, and ramp to high volume production of these aspects of AMD products at the silicon,package, socket, and platform-level. Prior to joining AMD, he was a Member of Technical Staffat MCC. He holds fifteen patents in the field of electronic packaging. He graduated from TheUniversity of Texas at Austin with a BS in Mechanical Engineering and from StanfordUniversity with a MS in Mechanical Engineering.

Keynote IIHow to Feed Enough to Greedy IoT Monsterby Prof. Kanji Otsuka, Meisei UniversityDate / Time Thursday, 1 December 2016 / 09.30 to 10.00 hrs (30 minutes)Venue MR331-332, Level 3

IoT changes greedy monster now-a-day. That seems to be uncontrollable world. Mega-data centers (DC’s) are try-ing to catch the monster mainly in the US. These systems included even edge center ones are in blind as like fogweather because the DC’s providers have been developed by own inside technologies. In our historically seen, theconcept has been undergoing as “high-end technologies automatically shift to low-end ones”. So we want to knowwhat the blind out. In my experiences, some of specific examples show by that could reveal the blinds and get theevidence.


I-17

Keynote Address

The most important element on their thought is communication bandwidth that is directly affected the data pro-cessing performance and communicating each other. The way for getting wider bandwidth involves threeapproaches which are high speed clocking, many lanes and high data compression. The first two issues relate withpackaging technology which would be presented some. We additionally consider data compression technology. Thesystem performance balance should put together the three issues. Let’s focus in the three issues now.

While power saving is another one of the most important things in not only DC’s but mobiles. Higher bandwidthintroduces saving power that we should know. Architecture of data processing with low power is managed by pack-aging issues which focus in also.

If you well done of it, the world’s highest-volume IoT platforms, the largest commercial health data clouds, thelargest commercial video platforms and so on even in mobile fields could be taken as far as technological basis.

Prof. Kanji OTSUKA, Graduated the Kyoto Institute of Technology in 1958. Receiving doctor grade of materialscience from Tokyo Institute of Technology. IEEE Fellow in 1998.

Hitachi Ltd., from 1959, since thirty four years, in semiconductor group firstly. That wasdawn period for semiconductor technology, so learned from solid-state physics to basic pro-duction process with original technology development. And also charged in computertechnologies belong main-frame group late of the period especially in high speed IO inter-face circuit and CPU-memory interconnection. Then large system design technology got forhis knowledge. In such job experiences, having wide technologies in materials, wafer process-ing, packaging, circuit technologies and system design for the semiconductors andcomputers. Since 1992, Meisei University, Faculty of Informatics, Dept. of Electronics and

Computer Science as a professor. Also the Director of Graduate of Informatics from 1999 to2000, and Dean of Faculty of Informatics from 2001 to 2003.

Currently he is an Executive Researcher and Emeritus Professor of Meisei University from 2006, Invited Professorof Osaka University (2011-now) and Guest Instructor of the University of Tokyo (2011). His recent job includes,in the large system so-called concurrent total system design with high speed processing logic, memory LSIs andincluding wafer processing, packaging and materials.

Keynote IIIAdvances of 3D Integration in CHINAby Dr. Wenhui Zhu, Central South University, ChinaDate / Time Thursday, 1 December 2016 / 10.30 to 11.00 hrs (30 minutes)Venue MR331-332, Level 3

With Moore’s law coming to end, 3D integration becomes an approach to extend package performance. Thiskeynote will report most recent progress in 3D integration packaging in China,mainly on multi-scaling thermal andreliability design, new process technologies for high aspect ratio micro-via manufacturing, and extreme wafer thin-ning. Formation of organic insulation layer in TSV(through silicon via) based on self-assembly chemical reactionwill be discussed, simulation results of controllable via-filling through additives-energy- interaction will be pre-sented. Selective-removing of Si-Cu- composed heterogeneous wafer by using nano-particles for back-grinding willbe proposed and analyzed. A short review will also be given to TSV-CIS(CMOS Image Sensor) and Fingerprintsensors, the most important application areas of TSV technology.


I-18

Dr. Wenhui Zhu is the CEO of Speed Suzhou Semiconductor Technology Pte Ltd. andprofessor of Central South University, China. He is the Chief Scientist of “FundamentalResearch on Wafer-Level 3D Integration for 20/14nm ICs” which is the 1 st National BasicResearch Program(973) in 3D IC integration. He was elected as Specially invited “1000Elite Plan Expert(2011)” under top class Talent plan of China. Previously he was ChiefTechnology Officer of Tian Shui Hua Tian Technology Co. Ltd, CEO of Kun Shan QTechnology Limited Co. He has been working in TSV packaging, DFR (design for reliabil-ity), DFM (design for manufacturability) and DFP (design for performance), packaging

materials and 3D nano-/micro-electronics packaging in leading semiconductor and packag-ing companies including Infineon,UTAC and TSHT. Dr. Zhu chaired many key projects in advanced packagingand structural integration such as national 863 project, Chinese natural science fund, and state key technology proj-ects and made great achievements in technology innovation and cost-saving. He is a key player of internationalconferences, e.g. IEEE ICEPT(2008-now) and EPTC(2006-2009), as organization committee or technical com-mittee chairman / co-chairman. Dr. Zhu is also reviewer of a few international journals in packaging areas. He hasbeen invited to give keynote talks and short courses in international forums and conferences. Dr. Zhu has publishedmore than 120 technical papers,owns 46 patents and won 3 times of best paper awards.

Keynote IVInnovations in SiP & Heterogeneous Integrationby Mr. William T. Chen, ASE GroupDate / Time Thursday, 1 December 2016 / 11.00 to 11.30 hrs (30 minutes)Venue MR331-332, Level 3

This talk will discuss the crucial role of heterogenous integration of electronic devices through SiP to meet the chal-lenges for the emerging internet of things (IoT), smart devices everywhere, and migration to the cloud. We shallreview the re-invention of core packaging technologies and the emergence of new innovations as developing plat-forms for SiP. In tracing the developments WLCSP and their evolvements into Fan Out, we shall show how thisnew core technology has great potential to play a major role in meeting the difficult challenges in the expandingIoT landscape Finally the talk will end with a brief summary of the Heterogeneous Integration roadmap to enablethe future of our industry in the post ITRS era.

William Chen (Bill) currently holds the position of ASE Fellow and Senior Technical Advisorat ASE Group. Prior to joining ASE, he was the Director at the Institute of MaterialsResearch & Engineering in Singapore. Bill retired from IBM Corporation after a career span-ning over thirty years in various R&D and managerial positions. He has held adjunct andvisiting faculty positions at Cornell University, Hong Kong University of Science andTechnology, and Binghamton University. Bill is the chair of the newly formedHeterogeneous Integration Technology Roadmap for Semiconductors, an initiative address-ing technologies for the IoT, IoE and cloud computing era, jointly sponsored by IEEECPMT, SEMI and EDS. He also chairs SEMI’s Advanced Packaging Committee. In 2009,

Bill received the InterPACK Excellence Award for his contributions, and in 2010, he was pre-sented with the IEEE CPMT Society David Feldman Outstanding Contribution Award. He is a past President ofthe IEEE CPMT Society and he has been elected a Fellow of IEEE and a Fellow of ASME. Bill received B. Sc.from London University, M.Sc. from Brown University and Ph.D. from Cornell University.

Keynote Address


I-19

Keynote VAchieving Automotive Quality Excellence: Zero DefectPerformance – a Foundry’s Perspectiveby Mr. Jagadish CV, Systems on Silicon Manufacturing

Company Pte LtdDate / Time Thursday, 1 December 2016 / 11.30 to 12.00 hrs (30 minutes)Venue MR331-332, Level 3

The automotive industry is well known for its high demand on safety, quality and reliability. Furthermore, the elec-tronic content of an automotive vehicle has been increasing steadily in the last two decades to achieve higher systemintegration of new functions and capabilities. Hence the semiconductor chip, which is at the heart of its electronicsystem, needs to be extremely low in defect (or zero defect) and high in reliability. Automotive SemiconductorManufacturers strive to meet the challenge of developing high quality fabrication processes to support the expan-sion of automotive ICs of future markets.

This keynote presentation will outline a systematic approach to implementing automotive readiness in critical fab-rication processes that help to accelerate the supply chain towards automotive quality excellence. A 360 degreefoundry perspective in achieving the automotive quality goal will be presented. In addition, top must-do actionsfor going beyond zero defect performance, moving from ppm to ppb level, meeting today and future automotivemarket, will be shared.

Mr. Jagadish C.V. was appointed CEO of Systems on Silicon Manufacturing Company(SSMC), a joint venture of TSMC and NXP in December 2006. Jagadish has vast experiencein the business development arena and semiconductor industry. He was a Director with FEICompany of USA before embarking his career with SSMC. Prior to his appointment asCEO, Jagadish served as Vice President, Business Operations of SSMC. He is currently amember of the NXP’s operations management team. Jagadish also serves as the DeputyChairman of the Singapore National Quality Award Governing Council and Power QualityAdvisory Panel (PQAP) of Singapore since 2007. He is also the Vice Chairman of SEMI,

Singapore Regional Advisory Board (RAB) since 2010; and Deputy Chairman of the PUBWater Network Panel since 2015. He is also a member of Singapore SemiconductorIndustry Association (SSIA) Board of Advisors since 2011. He holds a first class honors bachelor’s degree inElectronics & Communication from the National Institute of Engineering Mysore, India; and completed theInternational Executive Program by INSEAD Management School, France.

Keynote Address


Keynote VILight-Emitting Diodes for Non-Lighting Applications~ beyond seeing and being seen ~by Mr. Shi-Wei Ricky Lee, Hong Kong Univ. Science &

TechnologyDate / Time Friday, 2 December 2016 / 17.30 to 18.00 hrs (30 minutes)Venue SUMMIT 2

In the past decade, people witnessed more and more applications of light-emitting diodes (LED) for general light-ing. There is no doubt that solid-state lighting has become commodity in the comercial markets. Many people arewondering about what next waves of LED R&D will be. Based on the speaker’s observation, there are three emerg-ing areas worth noting, namely, UV-LED, visible light communications (VLC), and micro-LED display. All of theseare for non-lighitng applications. This presentation will briefly touch on these emerging areas and then focus onUV-LED. The intention is to bring the on-going technology trends to the awareness of active researchers on LEDso that they can put their resources and efforts on the hot spots. In addition to the fundamentals of UV-LED andrelevant concerns in packaging, certain applications will be introduced to demonstrate the features of UV-LEDwhich are diferente from conventional general lighting.

Ricky Lee received his PhD degree from Purdue University in 1992. He joined the HongKong University of Science & Technology (HKUST) in 1993. During his career of tenure-track faculty at HKUST, Dr Lee once was on secondment to serve as Chief TechnologyOfficer of Nano & Advanced Materials Institute (NAMI) for two and a half years. CurrentlyDr Lee is Professor of Mechanical Engineering and Director of Center for AdvancedMicrosystems Packaging (CAMP) at HKUST. He also has a concurrent appointment asDirector of HKUST LED-FPD Technology R&D Center at Foshan, Guangdong, China.Due to his technical contributions, Dr Lee received many honors and awards over the years.

In addition to being the recipient of 12 best/outstanding paper awards and 5 major profes-sional society awards, Dr Lee is Life Fellow of ASME and IMAPS, and Fellow of IEEE and Institute of Physics(UK). He is also a Distinguished Lecturer and the Senior Past-President of the IEEE Components, Packaging, andManufacturing Technology (CPMT) Society.

I-20

Keynote Address


I-21

Panel Session

Rise of China SemiconductorTopics: Semiconductor industry statistics and projections in China, Governmentpolicies, Supply chain, Semiconductor manufacturing and Packaging technologies,Opportunities & Challenges for China and for other countries/areasDate / Time Wednesday, 30 November 2016 / 17.30 to 19.00 hrs Venue MR3 -3 , Level 3

Panel Chair/ModulatorProf. Zhu Wenhui, Suzhou Speed Semiconductor technology Co., Ltd.

Dr. Wenhui Zhu is the CEO of Speed Suzhou Semiconductor Technology Pte Ltd. and professorof Central South University, China. He is the Chief Scientist of “Fundamental Research on Wafer-Level 3D Integration for 20/14nm ICs” which is the 1 st National Basic Research Program(973)in 3D IC integration. He was elected as Specially invited “1000 Elite Plan Expert(2011)” under topclass Talent plan of China. Previously he was Chief Technology Officer of Tian Shui Hua TianTechnology Co. Ltd, CEO of Kun Shan Q Technology Limited Co. He has been working in TSVpackaging, DFR (design for reliability), DFM (design for manufacturability) and DFP (design forperformance), packaging materials and 3D nano-/micro-electronics packaging in leading semicon-ductor and packaging companies including Infineon,UTAC and TSHT. Dr. Zhu chaired many key

projects in advanced packaging and structural integration such as national 863 project, Chinese natural science fund, andstate key technology projects and made great achievements in technology innovation and cost-saving. He is a key player ofinternational conferences, e.g. IEEE ICEPT(2008-now) and EPTC(2006-2009), as organization committee or technicalcommittee chairman / co-chairman. Dr. Zhu is also reviewer of a few international journals in packaging areas. He has beeninvited to give keynote talks and short courses in international forums and conferences. Dr. Zhu has published more than120 technical papers,owns 46 patents and won 3 times of best paper awards.

SpeakersDr Tan Yong Tsong joined A*STAR in August 2015 as Deputy Executive Director in the Scienceand Engineering Council (SERC), and was concurrently appointed as the Covering ExecutiveDirector of the Data Storage Institute (DSI). On 1 March 2016, Dr Tan was appointed as DeputyExecutive Director of Institute of Microelectronics (IME) in addition to his current appointments.On 1 September 2016, Dr Tan assumed the appointment as Executive Director of Institute ofMicroelectronics (IME) whilst retaining his concurrent appointment of Covering Executive Directorof Data Storage Institute (DSI), and relinquished his concurrent appointment of Deputy ExecutiveDirector of Science and Engineering Council (SERC). Dr Tan obtained his Bachelor degree fromthe National University of Singapore and took up a postgraduate scholarship from National Science

and Technology Board (NSTB) to pursue his Master’s degree and PhD in Physics at the University of Cambridge.

Dr Tan returned to Singapore upon completion of his studies abroad and joined the Institute of Microelectronics (IME)as a Senior Engineer and Business Development Leader. He left IME to join the private sector in 2003. Dr Tan has hadmore than 14 years of experience in technology management and investments, and business development in diverse indus-tries including optical telecommunications, semiconductor components, renewable energy, medical imaging anddiagnostics equipment. He has held various positions such as the Country Manager of Fujikura (Singapore), GeneralManager of FiberTech Ltd (China) and of Mitsui & Co. Ltd. (Japan).

Santosh Kumar is currently working as Senior Technology & Market Research Analyst at YoleDéveloppement. He is involved in the market, technology and strategic analysis of the microelec-tronic assembly and packaging technologies. His main interest areas are advanced IC packagingtechnology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

He received the bachelor and master degree in engineering from the Indian Institute ofTechnology (IIT), Roorkee and University of Seoul respectively. He has published more than


03 04

I-22

Panel Session

40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous confer-ences and technical symposiums related to advanced microelectronics packaging.

Bob Chylak is Vice President, Packaging and Process Integration for Kulicke & Soffa. He isresponsible for the research and development of packaging solutions across all K&S products.Bob has more than 25 years of experience in the semiconductor industry. He has a BS-EE degreefrom Penn State University and completed Executive Management Studies at Stanford University.Bob has published more than 50 papers and holds numerous patents.

As President of SEMI Southeast Asia, Kai Fai Ng oversees the association’s programs, products,and services with the mission to develop the semiconductor industry within Southeast Asia alongwith regional partners and local SEMI members. Additionally, he supports SEMI internationalprograms for members worldwide that have interests in Southeast Asian markets for technologyand materials.

Ng has more than 17 years industry experience, primarily in semiconductor fabrication, R&D,and strategic planning. Prior to joining SEMI, he held several executive and financial manage-ment positions at Axcelis Technologies, KLA-Tencor, and Chartered Semiconductor.

Ng holds three US patents related to semiconductor technologies and processes, as well as an MBA from MacquarieUniversity, Australia.

Albert Lan, Master of industrial & mechanical engineering department, Univ. of Wisconsin,Madison. Over 20 years of job experience on semiconductor industry, especially focus on bump-ing and flip chip advanced assembly technology. Vice Chairman of Semiconductor Equipmentand Materials International Taiwan Association.Chairman of TILA (Taiwan Intelligent LeaderAssociation). Currently Senior Director of Engineering Center of SPIL (Siliconware, Taiwan),which is 3rd biggest assembly house in the world.

As the President of SEMI China, Lung Chu oversees the evolution of SEMI’s programs, com-mittees, products, and services to deliver the highest member value in China’s rapidly changingsemiconductor ecosystem.

Most recently, Chu was President of China Operations for Global Unichip. He has also served asAPAC President at Cadence Design Systems and Magma Design Automation, and held executivepositions at KLA-Tencor, Apple Computer, and Philips Semiconductor. With more than 30 yearsof experience in semiconductor equipment, IC design, EDA/IP, semiconductor manufacturing,and system integration, Chu is uniquely suited to lead SEMI China and deliver on the SEMI 2020

Vision to increase collaboration across the entire manufacturing supply chain. Chu holds a BSEE from National TaiwanUniversity, an MSEE from Case Western Reserve University, and an MSEE and MBA from California State University.Additionally, he has served as President and Chairman of the Chinese American Semiconductor Professional Organizationand currently heads its Shanghai and Hsinchu chapters.


I-23

Professional Development Courses

The conference program includes six half day short courses conducted on 30th Nov 2016. Three courses will beconducted in the morning (PDC 1- 3), and three courses in the afternoon (PDC 4-6). The courses will be con-ducted by leading experts in the field.

PDC 1: [Parallel] Nanotechnologies for Microelectronics Packaging Applications: Currenttrends in IoT, Wearable, 3D, Flex Circuits, Thermal and Embedded passivesby James E. Morris, Portland State University, USADate / Time Wednesday, 30 November 2016 / 08.30 to 12.20 hrs Venue MR300, Level 3

The course begins with an introduction to electronics packaging for context, which includes the current trends inIoT, wearable, 3D, flex circuits, thermal and embedded passives. It then focuses on the application of nanoparticleand CNT properties to the enhancement of packaging materials for reliability, e.g. by melting-point depression, sin-tering, Coulomb blocks, enhanced chemical activities, high mechanical strength, low ballistic resistance, etc. At thesame time it will discuss applications of nanowires and other nanoscale structures.

1. Introduction to Electronics Packaging and current trends: IoT, flex circuits, wearables, 3D thermal, embed-ded passives, etc.

2. Introduction to Nanotechnologies in Electronics Packaging3. Nanoparticle properties: melting point depression, coulomb block, sintering, optical, etc4. Nanoparticle fabrication5. Nanoparticles for high-k dielectric capacitors and resistors for embedded passives6. Nanogranular magnetic core inductors for embedded passives7. Nanoparticles in electrically conductive adhesives,8. Nanoparticles in microvias and conductive inks for SMT interconnect9. Nanoparticles added to lead-free solders and flip-chip underfills

10. CNTs: fabrication, characterization (chirality, etc), and properties11. CNT effects in solders12. CNTs for thermal management and electromagnetic shielding13. Graphene for thermal management14. Nanowires and nanoscale spring interconnects15. Current commercial applications of nanopackaging16. Nanoscale modeling and simulation17. Summary

The course will be beneficial to electrical, mechanical, and materials engineers alike, or anyone with an interest inelectronic device design, fabrication, assembly, or application. The level will be introductory, and accessible to stu-dents and graduates in any of these areas or the physical sciences.

James E. MorrisDepartment of Electrical & Computer Engineering,Portland State University, Portland, OR 97207-0751, USA

[email protected]@ieee.org

Jim is a Professor Emeritus of Electrical & Computer Engineering at Portland StateUniversity, Oregon, and at the State University of New York at Binghamton. His B.Sc. and


I-24


1st Class Honors M.Sc. degrees in Physics are from the University of Auckland, New Zealand, and his Ph.D. inElectrical Engineering is from the University of Saskatchewan, Canada. He has served as Department Chair at bothBinghamton and Portland, and was the founding Director of Binghamton’s Institute for Research in ElectronicsPackaging. Jim has also held faculty positions at Saskatchewan, Victoria University of Wellington (NZ), and SouthDakota School of Mines & Technology, with visiting/sabbatical positions at Loughborough University (UK) as aRoyal Academy of Engineering Distinguished Visiting Fellow, Chemnitz University of Technology (Germany),University of Maryland (USA), University of Bordeaux (France), University of Greenwich (London), ChalmersUniversity of Technology (Sweden), Dresden University of Technology, University of Canterbury (NZ) as anErskine Fellow, and Helsinki University of Technology as a Nokia-Fulbright Fellow, with honorary appointmentsat Shanghai University and Shanghai Jiao Tong University. Other positions have included Senior Technician andPost-Doctoral Fellow at the U of S, brief periods with Delphi Engineering (NZ) and IBM-Endicott (New York),and industrial consulting. He was recognized in 2015 with an honorary doctorate from the POLITEHNICAUniversity of Bucharest.

Jim is an IEEE Fellow and an IEEE Components, Packaging, & Manufacturing (CPMT) Society DistinguishedLecturer. He has served as CPMT Treasurer (1991-1997) and Vice-President for Conferences (1998-2003), andcurrently sits on the CPMT Board of Governors (1996-1998, 2011-2016) and on the joint Oregon CAS/CPMTChapter executive committee, and chairs the CPMT Nanotechnology technical committee. He was awarded theIEEE Millennium Medal and won the CPMT David Feldman Outstanding Contribution Award in 2005. He is anAssociate-Editor of the IEEE CPMT Transactions and has been General Chair of three CPMT-sponsored confer-ences, Treasurer or Technical Chair of others, and serves on several CPMT conference committees. As the CPMTSociety representative on the IEEE Nanotechnology Council (NTC), he instituted a regular Nanopackaging seriesof articles in the IEEE Nanotechnology Magazine, established the NTC Nanopackaging technical committee,(which also acts as a program committee for annual IEEE NANO conferences,) served as the 2010-2012 NTCAwards Chair, chaired the IEEE NANO 2011 conference in Portland, and served as NTC Vice-President forConferences (2013-2014) and currently as Vice-President for Finance. He also co-founded the Oregon Chapter ofthe IEEE Education Society in 2005 and sits on its executive committee, and was Program Chair for the 1st and2nd IEEE Conferences on Technology for Sustainability (2013/14).

His research activities are focused on electrically conductive adhesives, the electrical conduction mechanisms in dis-continuous nanoparticle thin metal films, with applications to nanopackaging and single-electron transistornanoelectronics, and on an NSF-funded project in undergraduate nanotechnology education. He has edited or co-authored five books on electronics packaging and two on nanodevices, and lectures internationally onnanopackaging and electrically conductive adhesives. He is currently putting together the expanded second editionof his book: “Nanopackaging: Nanotechnologies and Electronics packaging” (Springer, 2016.).

PDC 2: [Parallel] 3D Integrated Circuit Failure Analysisby Prof. Ingrid De Wolf, imec, Belgium & KULeuven, BelgiumDate / Time Wednesday, 30 November 2016 / 08.30 to 12.20 hrsVenue MR301, Level 3

DescriptionIn 3D stacked-IC technology, thinned Si wafers/dies are vertically interconnected offering faster and more com-pact electronic circuits with heterogeneous integration capabilities. The stacked wafers/dies are electricallyinterconnected using µ-bumps and Cu Through Silicon Vias (TSVs). However, the introduction of these new mate-rials and new fabrication schemes is associated with new failure mechanisms requiring new failure analysis (FA)techniques. In addition, even for well-known failures in 2D-chips, pin-pointing the failure location becomes


I-25

increasingly challenging because of a combination of inaccessibility of the devices (part of a 2.5D or 3D stack) withsmall dimensions and high density of the devices.

In this course, after a short introduction to 3D technology and failure analysis, various failure analysis techniquesthat can be used for FA of 3D technology are discussed in detail. Their principle is explained, the advantages andlimitations for 3D technology-FA are discussed, and typical case studies are presented. The course will cover wellknown classical techniques, such as for example X-ray, scanning acoustic microscopy (SAM) and magnetic fieldimaging, but also new developments of these techniques. In addition, less conventional techniques (ex. lock-in ther-mography, polariscopy, EOTPR and some recent new electrical test-based techniques) will be covered.

Outline

Introduction3D technology

short introduction to the technology (aim, TSV, micro-bumps, thinning and stacking, Cu pillars,…)overview of expected failure mechanisms in 3D technology

Failure analysiswhat, why, 2D versus 3Dfailure analysis sequencechallenges

Overview of 3D FA techniques (+ case studies)Infra-red microscopyX-ray based techniquesAcoustic techniques (SAM, GHz SAM, acoustic signals)Magnetic field/current imaging methodsTDR and EOTPRPolariscopyPhoton emission microscopyLock-in thermographyNew e-test based techniques

Conclusions

Ingrid De Wolf received the PhD in Physics from the KU Leuven university, Belgium, in1989. In the same year she joined imec in Belgium, where she worked in the field of micro-electronics reliability, with special attention for gate oxide reliability, mechanical stressanalysis using micro-Raman spectroscopy and failure analysis using emission microscopy.From 1999 to 2014, she headed the group REMO, where research is focused on reliability,test and modelling of 3D technology, interconnect, MEMS and packaging. She managed togrow this group from a small team of 3 members to a highly recognized group of about 40people which is involved in several programs within imec (3D, interconnect, Optical IO,

GaN, Litho, PV, MEMS, STT-MRAM…). She authored or co-authored 14 book chaptersand more than 350 publications of which ~30 invited, and won several best paper awards at conferences focusingon reliability and failure analysis (ESSDERC, ESREF, ISTFA, EOS/ESD symposium, IEDM). She was ofteninvolved as session chair or technical committee member of these conferences, and is member of the steering com-mittee of ESREF. She is chief scientist at imec, IEEE senior member and professor at the department of Metallurgyand Materials Engineering of the KU Leuven where she teaches courses on non-destructive testing, MEMS relia-bility and failure analysis, characterization techniques and FMEA.



I-26

PDC 3: [Parallel] Fan-In and Fan-Out in Wafer Level Packagingby Mr. Albert Lan, Senior Director, Engineering Center, SPIL, TaiwanDate / Time Wednesday, 30 November 2016 / 08.30 to 12.20 hrsVenue MR302, Level 3

DescriptionThe Wafer Level Package (WLP) continues to see strong growth driven by mobile phones, tablets, portable play-ers, wearable and IoT devices with its benefits of small form factor and low profile packages.

In this course, we will introduce the innovative solutions of WLP include mold type WLCSP (mWLCSP), Fan-outWafer Level Package (FOWLP). Also, the future trend will be covered Panel Level FO technology.

Outline

1. IntroductionWhat is Wafer Level PackageMarket Trend of Wafer Level Package

2. Innovative Package Solutions Introduction and ChallengeMolded WLP (mWLCSP)Fan-Out WLP (FOWLP)

3. Future Package Solutions Introduction and ChallengePanel Level Fan-Out (PLFO)

4. Summary

Albert Lan obtained his Master of industrial & mechanical engineering department, Univ.of Wisconsin, Madison. Over 20 years of job experience on semiconductor industry, espe-cially focus on bumping and flip chip advanced assembly technology.; Vice Chairman ofSemiconductor Equipment and Materials International Taiwan Association.; and Chairmanof TILA (Taiwan Intelligent Leader Association)

Currently he is a Senior Director of Engineering Center of SPIL (Siliconware, Taiwan),which is 3rd biggest assembly house in the world now

PDC 4: [Parallel] Energy Efficient Thermal Management of Data Centersby Prof. Yogendra Joshi, G.W. Woodruff School of Mechanical Engineering

Georgia Institute of Technology, Atlanta, GA 30332Date / Time Wednesday, 30 November 2016 / . 0 to 1 . 0 hrsVenue MR300, Level 3

DescriptionWhile a number of energy efficiency initiatives have recently resulted in slowing the growth rate of energy consump-tion by data centers, currently about 3% of the electrical energy produced in the world is consumed by data centers.



13 1 7 0

As much as 20%-50% of this is associated with the operation of the cooling hardware. In this course, I will focus onenergy efficient thermal management of data centers. Starting from the trends in energy consumption by cabinetsand data centers, I will discuss the currently used metrics to quantify their energy efficiency and sustainability. I willdiscuss the evolution of the environmental guidelines for data centers, prescribed by the American Society ofHeating refrigeration and Air Conditioning (ASHRAE). I will then focus on approaches to improve energy effi-ciency of air-cooled data centers. Emerging trends such as improved air delivery, aisle containment, and “freecooling” will be discussed. Concepts of model based robust and sustainable design of data center facilities of thefuture will be addressed. A growing segment of data centers are high performance computing (HPC) installations.The growth towards exa-scale computing imposes some of the most serious thermal management and energy effi-ciency challenges for such facilities. Advanced thermal management approaches including hybrid liquid/air cooling,and liquid immersion cooling to handle the projected sharp increases in server heat loads in HPC will be discussed.

Outline

Energy consumption trends by servers, cabinets, and data centersEnergy efficiency metricsEnvironmental control guidelines evolutionCurrent state-of-the-art of data center thermal managementEmerging trends for energy efficiency improvement

Improved tile air deliveryAisle containment“Free cooling”

Energy efficiency enhancements in air cooled data centers through cooling advancesMetrologyModeling and sustainable design

Thermal management for High performance computingHybrid, and indirect liquid coolingDirect liquid cooling

Future thermal management trends

References

Energy Efficient Thermal Management of Data Centers, Yogendra Joshi and Pramod Kumar, Editors, Springer,2012.

Air Flow Management in Raised Floor Data Centers, Vaibhav K. Arghode, and Yogendra Joshi, Springer, 2016.

Yogendra Joshi is Professor and John M. McKenney and Warren D. Shiver DistinguishedChair at the G.W. Woodruff School of Mechanical Engineering at the Georgia Institute ofTechnology. His research interests are in multi-scale thermal management. He received aPh.D. in Mechanical Engineering and Applied Mechanics, from the University ofPennsylvania in 1984. He is the author or co-author of over 320 archival journal and con-ference publications, and is an elected Fellow of the ASME, the American Association for theAdvancement of Science, and IEEE. He was a co-recipient of ASME Curriculum InnovationAward (1999), Inventor Recognition Award from the Semiconductor Research Corporation(2001), the ASME Electronic and Photonic Packaging Division Outstanding Contribution

Award in Thermal Management (2006), ASME J. of Electronics Packaging Best Paper of the Year Award (2008),IBM Faculty Award (2008), IEEE Semitherm Significant Contributor Award (2009), IIT Kanpur DistinguishedAlumnus Award (2011), ASME InterPack Achievement Award (2011), ITherm Achievement Award (2012), andASME Heat Transfer Memorial Award (2013).

I-27



PDC 5: [Parallel] Internet of Things (IoT) focusing on Wireless Sensors Networkand Active RFIDby Prof. Holden Li, Temasek Laboratories at Nanyang Technological

UniversityDate / Time Wednesday, 30 November 2016 / 13.10 to 17.00 hrsVenue MR301, Level 3

DescriptionThis short course focuses on the technology and markets enabling the Internet of Things (IoT), especially relatedtechnologies such as Wireless Sensor Network and Active RFID. The class will discuss in detail generic IoT sensors,especially MEMS based one, that are commonly used and also upcoming ones; technologies progression over thepast ten years and looking beyond; reality versus the hype, etc.

It will also specifically address issues like the hardware advantages and disadvantages for each choice. Participantswill have a better understanding of what IoT is and which part does wireless sensing and RFID play. Other inter-esting topics include the architecture of IoT from the ground up; traditional Active RFID, RFID enabledcellphones, smart active labels/ battery assisted passive tags, and Wireless/Ubiquitous Sensor Networks (USN).Lastly, a brief introduction on the various energy harvesting mechanisms will also be discussed.

Outline

1. Introduction and background of IoT2. RFID System Basics3. Various RFID related technologies used in IoT4. RFID related application in Singapore5. Wireless Sensor Networks (WSN)6. WSN in Singapore context7. Enablers of IoT – Energy Harvesting8. Real Time Location Systems9. Tradeoff studies of various technologies

10. Related Opportunities in Singapore and South East Asia

Dr Holden Li graduated in NUS with a Bachelor of Engineering (Honors) in 1997. In2000 Holden enrolled in Stanford University for his graduate studies under ProfessorThomas Kenny. During his PhD studies, Dr Holden Li was actively involved in MEMSprocess development in finding suitable packaging solutions to MEMS and BioMEMSdevices. Besides, he worked closely with several industrial partners who benefited from theon-going research activities in Kenny’s group at that time. He was awarded his MSc and PhDin Mechanical Engineering in 2001 and 2005 respectively. Back in Singapore in September2005, he started to lead a research team in MEMS sensors research effort in the area of

MEMS R&D and reliability study. Beyond this, his passion for R & D in microelectronics,and his strong academic interest in the area of micro and nanotechnology propelled him to seek for funding oppor-tunity in this area. He is currently working closely with several senior faculties in the area of microelectronics,MEMS research and Internet of Things (IoT) applications both in NTU and Temasek Laboratories at NTU. He isserving on the National Committee of Semiconductor Devices and Technology formed by SPRING Singapore anddriving the standardization of the design, manufacture and testing of MEMS and NEMS devices.

I-28



PDC 6: [Parallel] 2.5D- and 3D-Stacked ICsby Prof. Paul Franzon, North Carolina State University, USADate / Time Wednesday, 30 November 2016 / 13.10 to 17.00 hrsVenue MR302, Level 3

DescriptionThree dimensional chips stacked using Through Silicon Via (TSV) technology has been under consideration andthe subject of intensive research for several years now. This tutorial covers the technology, applications, design andCAD for 3DIC. The technology will be introduced, including TSVs, face to face technologies, integration optionsand interposers. Applications will be discussed as driven by cost, performance and power efficiency needs. Exampleswill be given from the commercial world and the author’s own research. CAD and CAD-driven design will be cov-ered including verification, test, and thermal evaluation.

Outline

1. DIC Motivation• Power Efficiency• Memory Bandwidth• Bandwidth density• Heterogeneous Integration• Cost reduction

2. DIC Manufacturing• Bulk TSV formation• SOI TSV formation• Wafer and chip assembly flows• Interposers

3. DIC Design and Test• Power and power efficiency• Memories and memory interfaces• The potential for logic partitioning• CAD flows• Thermal design• Power delivery

4. Test• Test issues• Potential Test Flows• Test standards• Cost issues• Conclusions and Future perspectives

Paul D. Franzon is currently a Distinguished Professor of Electrical and ComputerEngineering at North Carolina State University. He earned his Ph.D. from the University ofAdelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTOAustralia, Australia Telecom and three companies he cofounded, Communica, LightSpinTechnologies and PBI Inc. His current interests center on the technology and design ofcomplex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electron-ics. He has lead several major efforts and published over 200 papers in these areas. In 1993he received an NSF Young Investigators Award, in 2001 was selected to join the NCSUAcademy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor,

and received the Alcoa Research Award in 2005. He served with the Australian Army Reservefor 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.

I-29



Advanced eWLB FOWLP SiP Technologyby Dr. Seung Wook Yoon, MBA, STATS ChipPAC Date / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR331

DescriptionThe number of WLCSP (Wafer Level Packages) used in semiconductor packaging has experienced significantgrowth since its introduction in 1998. The growth has been driven primarily by mobile consumer products becauseof the small form factor and high performance enabled in the package design as well as its cost advantage. And itis also attractive to WE (wearable electronics) and IoT(Internet of Things) products. The implications of thesemarket drivers on the packaging are; higher performance designs, lower power consumption, lower cost, smallerform factor, thinner profile and higher level of integration.

eWLB (Embedded Wafer Level BGA) is one of key advanced packages because of advantages of higher I/O den-sity, process easiness and integration flexibilities. It also facilitates integration of multiple dies in one packagewithout using substrates. eWLB provides smaller form-factor, excellent heat dissipations, thin package profile as ithas the potential to evolve in various configurations with proven manufacturing capacity and production yield.

This paper introduces eWLB (embedded Wafer Level Ball Grid Array) /FO-WLP (fanout –WLP) for its current mar-ket and future trend&requirement, advantages, improved and advanced features and performance as well as reliability.This paper also discusses the wide range of FOWLP/eWLB adoptions in industry past years and novel features avail-able for emerging market of IoT and WE. This advanced technology is well designed for 3D PoP, MEMS/sensors,3D SiP modules as well as ultra-thin, highly integrated packaging solutions. Innovative FOWLP/eWLB features arealso introduced with the merits and thermal/electrical characterization data as well as enhanced reliability.

Dr. YOON is currently in charge of Wafer Level Products & Technology Marketing inSTATS ChipPAC PTE LTD. His major interests are for wafer level products includingeWLB/Fanout WLP, WLCSP, IPD (integrated Passive Device), flipchip bumping, TSV(Through Silicon Via), SiP and integrated 3D IC packaging.

Prior to joining STATS CHIPPAC, He was deputy lab director of MMC (Microsystem,Module and Components) lab, IME (Institute of Microelectronics), A*STAR (Agency ofSingapore Technology and Research), Singapore. “YOON” received Ph.D degree in

Materials Science and Engineering from KAIST, Korea. He also holds MBA degree fromNanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers,and over 25 US patents on microelectronic materials and electronic packaging. Currently contributing as technicalcommittee member of prestigious international conferences, such as EPTC, ESTC, iMAPS, IWLPC and SEMI.

What’s happening in TSV based 3D/2.5D IC packaging: Latest market &Technology Trendsby Mr. Santosh Kumar, Yole DevelopmentDate / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR332

DescriptionThrough-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They arealso an enabling technology for heterogeneous integration of logic circuits with CMOS image sensors (CIS),

I-30

Invited Presentations


MEMS, sensors, and radio frequency (RF) filters. In the near future they will also enable photonics and LED func-tion integration. The market for 3D TSV and 2.5D interconnect is expected to reach more than two million wafersin 2020, expanding at >20% CAGR. The growth is driven by increased by increased adoption of 3D memorydevices in high-end graphics, high-performance computing, networking and data centers, and penetration into newareas, including fingerprint and ambient light sensors, RF filters, photonics and LEDs.

The presentation will explain the market’s dynamics and give an overview of all segments and key markets of theTSV based 3D/2.5D IC packaging.

Santosh Kumar is currently working as Senior Technology & Market Research Analyst atYole Développement. He is involved in the market, technology and strategic analysis of themicroelectronic assembly and packaging technologies. His main interest areas are advancedIC packaging technology including equipment & materials. He is the author of severalreports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

He received the bachelor and master degree in engineering from the Indian Institute ofTechnology (IIT), Roorkee and University of Seoul respectively. He has published more

than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented andgiven talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

Opportunities and Challenges for Advanced Packaging Equipmentby Mr. Bob Chylak, K&SDate / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR333

DescriptionThe slowdown of Moore’s Law chip scaling prompted a greater focus on packaging R&D over the last several years.These efforts have resulted in a proliferation of packaging solutions that are collectively referred to as AdvancedPackaging. The new technologies are currently at various stages of the research-development-production path andit is not entirely clear which of these will emerge as the high volume manufacturing methods of the future. Only afew years ago 2.5D and 3D were thought so see huge volumes by now, but this has largely not materialized exceptfor the case of advanced stacked memory and leading-edge graphics cards.

SiP and Fan-out Wafer Level Packaging (FOWLP) now appear as the highest projected growth rate packages in the elec-tronics packaging space and their future as the leading high volume manufacturing technologies appears more certain.Part of the increasing demand for FOWLP is driven by the potential for high levels of integration, creating FOWLP SiPoptions that enable the smallest form factor, lowest cost and highest performance for new multi-die designs. The rangeof potential FOWLP packages goes from the low cost single die, with or without passives, to complex multi-die 3Dpackaged assemblies. But within this new packaging technology, there is a lack of standards resulting in multiple optionsthat place very different requirements on the assembly equipment. These include face-up/face-down die placement,RDL last (die first)/RDL first (die last), local/global alignment. Depending on the particular methodology, the pickand place tools would need pulsed heated or constant heat bondheads, flip/unflip, high/low force, accuracy rangingfrom 3um to 10um and potentially the ability to place on organic substrates, wafers or panels. All of these options havethroughput and COO implications. The assembly needs can be addressed with equipment architectures ranging fromhigh-end TCB/flip chip bonders with high accuracy and lower UPH to high-end SMT tools with medium accuracyand very high UPH. There are also opportunities to integrate PC Board manufacturing and backend assembly.

Beyond fan-out, true thermocompression bonding such as for TSV memory stacks, high accuracy flip chip bond-ing to substrates or wafers and SMT-type placement of substrate-embedded die are all within the die placementequipment space.

I-31



The multitude of packaging processes creates both challenges and opportunities for equipment suppliers. Theopportunities are of course to sell equipment for these emerging markets. But there is also risk of developingmachines for markets that then don’t materialize in a good ROI. The end-users of the equipment are challengedwith trying to develop innovative packaging solutions that distinguish themselves from their competitors withoutrequiring equipment that is so customized that cost become prohibitive. The logical path for equipment suppliersis to develop highly versatile and re-configurable machines. This effort can be helped by the end users being care-ful to not over-spec the requirements, aiming for as much standardization as possible without limiting theircompetitive advantages and close collaboration between equipment suppliers and users.

Bob Chylak is Vice President, Packaging and Process Integration for Kulicke & Soffa. Heis responsible for the research and development of packaging solutions across all K&S prod-ucts. Bob has more than 25 years of experience in the semiconductor industry. He has aBS-EE degree from Penn State University and completed Executive Management Studies atStanford University. Bob has published more than 50 papers and holds numerous patents.He can be reached at [email protected].

Chip Integrated Single Phase Liquid Cooling Using Pin Fin EnhancedMicrogapsby Prof. Yogendra Joshi, Georgia TechDate / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR334

DescriptionHigh performance planar and three-dimensional (3D) stacked chip microsystems of the future have been projectedto result in background heat fluxes in excess of 1 kW/cm2, and localized hot spots of 5 kW/cm2 or more.Requirements for routing of electrical interconnects across the entire 3D chip stack, along with the need forenhancement of heat transfer surface area have made microgaps incorporating pin fin arrays an attractive designconfiguration. Liquid cooling using microgaps is also of interest in ultraportable applications, where increasing chipleakage power is becoming a serious limitation. In this talk, I will discuss the design evolution of a single phase liq-uid cooled chip integrated package to handle large background heat fluxes, along with localized hot spots. I willstart by addressing the flow delivery plenum design to insure structural reliability, along with uniform flow distri-bution. Experimental and computational studies of single phase forced convection in enhanced microgaps to handlehighly non-uniform power maps will be presented. The effectiveness of pin clustering to handle non-uniform heatfluxes within the microgap will be demonstrated. Finally, examples of single phase microfluidic cooling for chipcooling applications will be presented.

Yogendra Joshi is Professor and John M. McKenney and Warren D. Shiver Distinguished Chairat the G.W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology.At Georgia Tech he is the Principal Investigator of the Office of Naval Research Consortium forResource-Secure Outposts (CORSO), and Site Director for the National Science FoundationIndustry/University Cooperative Research Center on Energy Efficient Electronic Systems. Hisresearch interests are in multi-scale thermal management. He received a Ph.D. in MechanicalEngineering and Applied Mechanics, from the University of Pennsylvania in 1984. He is anelected Fellow of the ASME, the American Association for the Advancement of Science, andIEEE. He was a co-recipient of ASME Curriculum Innovation Award (1999), Inventor

I-32



Recognition Award from the Semiconductor Research Corporation (2001), the ASME Electronic and PhotonicPackaging Division Outstanding Contribution Award in Thermal Management (2006), ASME J. of ElectronicsPackaging Best Paper of the Year Award (2008), IBM Faculty Award (2008), IEEE SemiTherm Significant ContributorAward (2009), IIT Kanpur Distinguished Alumnus Award (2011), ASME InterPack Achievement Award (2011),ITherm Achievement Award (2012), and ASME Heat Transfer Memorial Award (2013).

A Novel NanoCopper-Based Advanced Packaging Materialby Dr. Alfred A. Zinn, Lockheed Martin Space Systems CompanyDate / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR335

DescriptionA novel nanocopper-based packaging material was developed for robust, void-free thermal interfaces between LEDsand heat sinks/spreaders and other high power components and devices allowing sub-10 micron thermal interfacesensuring high heat transfer rates. Other applications are in TSV & wafer level packaging, embedded chip packag-ing, direct print of Si and Glass interposers, wafer level bonding and die attachment as well as printed and flexibleelectronics.

This solder-free nanocopper material overcomes the fundamental limitation of traditional solders, where the pro-cessing temperature sets an upper bound to the maximum possible operating temperature. Since nanocopperreverts to bulk copper upon fusion, it is capable of operating at temperatures above its original processing temper-ature making it the ideal high temperature packaging technology. Being pure copper in its fused state, the materialcan form contacts with 5-10x the thermal and electrical conductivity of typical solder systems. The material’s rhe-ology can be tuned for drop-in replacement of solder paste on standard PCB assembly lines and other industrialdispensing and printing equipment. The resulting copper-based interconnects can exhibit improved creep resistanceand enhanced reliability and robustness in low- and high-temperature operating environments.

For LED bonding to thermal heat sinks/spreaders, a readily dispensable nanocopper die attach material was for-mulated for controlled and repeatable dispensing of less than 0.1 mg per die that led to interface layers as thin as2-3 micron.

Dr. Alfred Zinn has over 20 years of experience working on the development of nanostruc-tured functional materials (optical, thermal, nano/micro-magnetics), smart materials,high-temperature materials systems, device physics modeling, quantum/ superlattice struc-tures and devices, and high performance energy conversion devices (solar, high & low qualityheat conversion). His role includes identifying profitable adjacencies and licensing opportu-nities for such new technologies and help bring them to market. His responsibility spans allphases of a project environment from the proposal phase, hardware design, analysis and test-ing, to technology transition and integration as well as commercialization. He has been

leading multiple projects and teams to success at the ATC and is invaluable in the design,analysis, fabrication and test of materials systems. He has extensive experience in designing of complex materials sys-tems for a wide variety of applications ranging from electronics to high temperature structural applications as wellas manufacturing process design, implementation and scale-up.

Dr. Zinn currently holds 23 patents in materials, structures and processing technologies and THz technology, withover 10 additional patents pending (multiple international filings) as well as eight trade secrets and one trademark(CuantumFuseTM). He has authored or co-authored over 30 archival journal publications, including book chap-ters in “The Chemistry of Metal CVD” as well as the “Encyclopedia of Inorganic Chemistry.”

I-33



Innovations in Packaging will enable the IoT world of the Futureby Dr. W. R. Bottoms, 3MTSDate / Time Thursday, 1 December 2016 / 13:30 to 14:00 hrsVenue MR336

DescriptionMoore’s Law scaling can no longer maintain the pace of progress just when we need it most. Data, logic and appli-cations are migrating to the cloud, consumerization of data and the rise of the Internet of Things are placing newdemands and they are all occurring at the same time. Difficult challenges in power, performance, latency, band-width density and cost threaten our ability to maintain the progress that has enabled the growth of our industry.Meeting these challenges will require reduction in power and cost per function by a factor of 104 over the next 15years while improving performance and decreasing latency. It is clear that we will not have a replacement for theCMOS switch in the near term to return to a device scaling path to maintain the pace of progress. Only a revolu-tion in packaging, which has not kept up with the scaling of CMOS, can provide a solution. This will require newtools for design and simulation, new packaging architectures, production processes, materials, and equipment.These difficult challenges and potential solutions will be discussed.

Dr. Bottoms received a B.S. degree in Physics from Huntington College in Montgomery,Alabama in 1965, and a Ph.D in Solid State from Tulane University in New Orleans in 1969and is currently Chairman of Third Millennium Test Solutions. He has worked as a facultymember in the department of electrical engineering at Princeton University, manager ofResearch and Development at Varian Associates, founding President of the SemiconductorEquipment Group of Varian Associates and general Partner of Patricof & Co. Ventures. Hehas served as Chairman and CEO of Several Companies both public and private.

Dr. Bottoms has also served in a number of Government Advisory positions includingChairman of the Board on Assessment for NIST and a member of the Technical Advisory Committee on exportcontrols for the US Commerce Department.

Dr. Bottoms currently serves as:

• Emeritus Member of the Board of Tulane University• Co-Chair of the Heterogeneous Integration Roadmap• Chairman of the SEMI’s Awards Committee• Chairman of the Packaging and Package Substrates Technical Working Group for INEMI• Member of the Board of MIT’s Microphotonic Center• Chairman of APMT• Chairman of Third Millennium Test Solutions

I-34



In the IoT development frame : How to address mechanical and thermalissue?by Dr. Sebastien Gallois-garreignot, STMicroelectronicsDate / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR331

DescriptionPrevious years have seen tremendous surge of interest and publications in the Internet of Things (IoT). Generallyspeaking, IoT may be defined as a global infrastructure connecting virtual and physical generic objects, collecting& exploiting information provided by those objects, and its related network developments. Numerous visions co-exist in the industry for that domain. The very wide range of possible applications (Transportation, Healthcare,Home/Office/Plant environments…) clearly promotes this technology as a real business opportunity in the com-ing years. In that regard, STMicroelectronics has developed a unique portfolio covering all the necessary buildingblocks (Analog, Connectivity, Microcontrollers, Power, Sensors…) able to provide solutions to create smart things.

In our analysis, IoT technologies rely on a strong heterogeneous integration, connectivity standards, large band-widths and low power consumption… Moreover, the fields of application are as numerous as they are challenging.Indeed, the environments may be harsh and quite different from one to another: Automotive, Industry…Reliability may be also crucial like in e-Health domain. In that context, co-design is needed to propose reliable,optimized and efficient object. Focusing on the mechanical and thermal issues, these aspects have to be evaluatedand controlled as soon as possible during the product development.

To do so, a traditional approach, based on Finite Element method, is necessary. Such tool may be considered as agood compromise between standardization/availability on the market, user-friendly interface and accuracy.However, the scale of interest (from millimeter to microns, and even nanometer) is a huge challenge which requiresadditional approaches.

Experimental characterization (properties, imaging, strain/temperature map…) is complex in our industry due tostrong constraints: thin film effect, sample processing and micrometer scale are part of it. However, we have at ourdisposal very well-known electronic devices which can be rethought as sensors (among others, diode, transistor,resistance). Thus, it provides in-situ measurements during the process flow and/or the product life. Such data aremore than welcome for our community: for calibration (CAD tool) and qualification (product) purposes but also,as an important data bank which may be used for further optimization, knowledge of the stress state in variousapplications.

In that sense, the parallel with the IoT (interactions and communications with the environment thanks to sensorsembedded in everyday-life objects) is interesting and may be inspiring for developing new approach/methods forthe reliability.

Sebastien Gallois-Garreignot is in charge of mechanical and thermal simulations forSTMicroelectronics, more particularly concerning the Chip/Package interactions and therelated failures. Development of mechanical characterization methods, understanding of thefracture phenomena in complex architecture are ones of his additional fields of research andexpertise.

He received Phd degree from INSA-Lyon on the experimental and numerical investigationson the fracture phenomena in advanced architecture in microelectronics in 2010.

I-35



Laser Processing of Printed Copper Interconnects On Polymer Substratesby Dr. David HUTT, Loughborough Univ.Date / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR332

DescriptionWith the increasing demand for integration and embedding of electronics into a variety of devices there has beena consequent increase in the demand for novel materials and methods for the deposition of electrically conductivetracks on non-traditional substrate materials and/or complex 3D shapes. Current and future manufacturing meth-ods of such devices may include high volume reel-to-reel processing on temperature sensitive polymer substrates,e.g. for low cost RFID tags or IoT applications, or incorporation of circuits onto or within 3D printed plastic parts.Circuit deposition techniques must therefore be compatible with these applications and ideally be additive innature. Materials development has largely focused on silver inks and pastes due to their high conductivity and reli-ability; however, they are limited in their uptake by the relatively high material cost and, in many cases, therequirement for non-localised thermal processes to obtain the required electrical properties.

This presentation will describe recent research investigating methods for the deposition of micron scale copperpowder based materials and their selective laser processing to form interconnects on polymer substrates. Theapproach uses copper powder that is chemically treated to modify its surface condition and then patterned onto thesubstrate either as a dry powder, or combined with a binder to be printed as a paste. A low cost CO2 laser is thenused as a highly controllable heat source to deliver the required power selectively to the copper powder, leading totracks that show good electrical conductivity and with microstructures that are dependent on the process parame-ters. This controlled laser treatment method has enabled the formation of conductive tracks on low meltingtemperature polymer substrates, thereby enabling the capabilities of the technology to be explored in the creationof 3D printed circuits.

Dr David Hutt is a Senior Lecturer at Loughborough University, UK and a Senior Memberof the IEEE. He received his BSc in Chemistry and PhD in Surface Science from ImperialCollege, London and studied surface chemistry / physics as a Research Associate at a num-ber of UK universities. In 1997, he joined the Interconnection Group at LoughboroughUniversity, applying this background to the field of electronics manufacture and wasappointed to a lectureship in 1999. He has led numerous research projects in the area of elec-tronics packaging and published over fifty journal papers with particular emphasis onself-assembled monolayers for surface modification and preservation, metallisation using

electroless plating, flip-chip assembly, copper filled electrically conductive adhesives, polymerand glass substrate manufacture.

Package Miniaturization & Integration for Future Automotive Applicationsby Andreas Fischer, Robert Bosch GmbHDate / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR333

DescriptionAdvanced driver assistance systems, automated driving features, and comprehensive vehicle connectivity are key sell-ing features for current and future automobiles.

I-36



The race of car manufacturers towards smart mobility is both, a major challenge and an opportunity for the auto-motive electronics industry.

Smart mobility requires highly integrated solutions with technology and packaging features and performance knownfrom consumer electronics, but designed and approved for safety-relevant automotive applications under harsh con-ditions. Heterogeneously integrated packaging solutions will significantly increase technical complexity. At the sametime automotive quality standards and lifetime requirements for the entire system have to be fulfilled, knowing thattrends in automotive electronics will push the limits for certain applications to even higher levels than today.

Key capabilities to be successful are a profound knowledge of technology features, the related failure modes, andquantitative characterization of materials and interfaces. Those will be the basis for improved simulation-based engi-neering already in early design phases. Examples for that methodology are shown and an outlook towards possibleimprovements will be given.

Andreas Fischer has studied physics at the university of Ulm, Germany, focusing on solidstate and polymer physics.After his master thesis on nuclear magnetic resonance and polymerdynamics he joined Bosch in 1990, starting as a process development engineer for hybrid cir-cuits and sensors.Then he moved to assembly & packaging as a project manager forpackaging development for ASICs. Currently he is senior manager for ASIC packagingdevelopment.

Packaging and Testing of High Speed Rotor for MEMS Gas TurbineEnginesby Prof. Yan Xiaojun, Beihang UniversityDate / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR334

Xiaojun Yan joined Beihang University in 2002 and is now a professor at the School ofEnergy and Power Engineering and vice-dean of the school. He received his B.S. and Ph.D.degrees from Beihang University in 1995 and 2000, respectively. He was a visiting scholarat UC Berkeley during 2009-2010. He was awarded the National Excellent 100 DoctoralDissertation (2003) and the New Century Excellent Talents in Universities (2006) in China,the Second Prize for Progress in Science and Technology awarded by Chinese Ministry ofEducation ( 2013). He won the Beijing Youth May 4th Medal (2009), the Award for BeijingTalents in Education Innovation (2006). His current research interests include power andpropulsion for micro air vehicles, smart structure, high temperature structure mechanics etc.

Currently, he serves as a subject editor for Journal of Aerospace Power, and a member of Beihang UniversityAcademic Committee.

I-37



Technology and Market Trends in Packagingby Mr. Damo Srinivas, Lam ResearchDate / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR335

DescriptionThe presentation will focus on technology and business trends in packaging. Market segmentation for current andemerging markets will be presented. The drivers and technology roadmap will be covered for DRAM and CIS mar-ket segments. Also, presented will be market size for capital equipment in the packaging segment. Increasingnumber of WLP in smart phones and other applications will continue to drive the growth of advanced packagingin OSAT and IDMs. Internet of Things (IoT) will enable further growth in the advanced packaging segment.

Damo Srinivas rejoined Novellus Systems Inc. in April 2010 and is currently ManagingDirector of Business Development for the Lam Research equipment portfolio serving theadvanced wafer level packaging applications & FEOL Electroplating. Damo has held severalkey management positions including Vice President, General Manager for the Photoresistand CM business groups at Novellus and Vice President, Interconnect Technologies atATMI Inc.

Damo has also extensive international customer experience working in account managementroles for Novellus serving Intel in Hillsboro, OR for 6 years , IBM and alliance partners for

2 years based in Fishkill, NY and 2 years in Hsinchu, Taiwan R.O.C., serving TSMC, UMC, and the rest of theSemiconductor companies based in Taiwan, China and Singapore.

Damo also has extensive product management and business development experience and has led several new prod-uct development for high end value added Semiconductor applications. Damo received his M.S. Degree inMaterials Science fromArizona State University, Tempe, AZ USA and B.S. Degree in Metallurgical Engineeringfrom Indian Institute of Technology, Chennai, India.

Wafer Bonding as an Enabler for Microsystems Packaging and Integrationby Prof. Chuan Seng Tan, NTUDate / Time Friday, 2 December 2016 / 08:30 to 09:00 hrsVenue MR336

DescriptionWafer bonding has come a long way in semiconductor manufacturing. Broadly, it can be classified as direct or indi-rect bonding. With the emergence of 3D packaging, MEMS packaging, engineered substrate and monolithicintegration, wafer bonding has increasingly played a pivotal role. In the first half of this talk, solderless copper bond-ing is discussed with emphasis on surface passivation with self-assembled monolayer and surface activation withinert plasma. Recent work on copper nano-particles and micro-particles mixture for die attach application is alsodiscussed. A demonstration of TSV-less CMOS-MEMS stacking with metal bonding is showcased. In the secondhalf of this talk, discussion on molecular bonding of silicon and non-silicon materials is discussed. Applications inengineered substrate and monolithic integration using molecular bonding are also presented.

I-38



Chuan Seng Tan received his B.Eng. degree in electrical engineering from University ofMalaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advancedmaterials from the National University of Singapore under the Singapore-MIT Alliance(SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as aresearch engineer where he worked on process integration of strained-Si/relaxed-SiGe het-erostructure devices. In the fall of 2001, he began his doctoral work at the MassachusettsInstitute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electricalengineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for

2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joinedNTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inauguralNanyang Assistant Professorship. In February 2014, he was promoted to the rank of Associate Professor (withtenure). His research interests are semiconductor process technology and device physics. Currently he is workingon process technology of three-dimensional integrated circuits (3-D ICs) as well as engineered substrate for elec-tronics-photonics integration. He authored and edited four books. He is an associate editor for ElsevierMicroelectronics Journal (MEJ). He is a member of IEEE.

Enabling Design for Reliability in Advanced Interconnects for 3D IC andNext Generation Solar PV (Photovoltaics) Systemsby Prof. Arief Budiman, SUTDDate / Time Friday, 2 December 2016 / 13:50 - 14:20 hrsVenue MR331

DescriptionThe importance of mechanics and reliability in the design of advanced engineering systems and devices goes beyondtheir functionality. When materials under operational conditions fail, which occur for any advanced systems (elec-tronics, photonics, photovoltaics, mechanical or even biological), failures are almost always controlled by themechanics of the materials - more and more true in advanced or nanoscale materials. Device/system makers havemore and more thus realized that until they ship robust and reliable nanoscale systems/devices, they will not real-ize the true commercial values of their products. Thus the term was coined in the design community - Design forReliability. To enable design for reliability for advanced systems/devices like 3D IC systems and next generationphotovoltaics (PV) modules, it is important that we not only become great nanoresearchers and scientists, but alsogreat nanodesigners - able to offer complete and elegant engineering solutions from ideas to beautifully working,robust and reliable nanodevices. One key to enable the successful implementation of advanced interconnects in 3DIC using the Through-Silicon Via (TSV) as well as in next generation PV systems is the control of the mechanicalstresses. They could lead directly to integration issues as well as reliability concerns during the system’s lifetime.More importantly, they could also impact the device/system’s electrical performance through strain-induced elec-tron mobility change in the silicon (in the case of TSV) and the photovoltaics performance through cell cracks inthe silicon solar cells (in the case of solar PV). In an effort to shed light on these topics, stress characterization andmapping of the samples using ex situ and in situ synchrotron X-ray microdiffraction technique (in situ - ie. duringoperational and/or accelerated loading conditions of the device) are proposed. The synchrotron-sourced X-raymicrodiffraction technique has been recognized to allow some important advantages compared to other techniques,namely stress measurement of individual Cu TSV as well as the silicon substrate surrounding it simultaneously atthe submicron resolution, stress measurement in situ during annealing and while Cu TSV is still buried under thesilicon substrate (mimicking the conditions of real device). In the case of silicon solar PV, this technique has beenalso recently recognized to allow important measurement to be done directly on the silicon solar cells while theyare already encapsulated in the laminate or module packages. Using this approach, we aim to gain fundamentalunderstanding of the role of stresses and mechanics, and how they evolve through processes and integration as wellas during operation/service of the device leading to the eventual catastrophic events of failure. This elementaryunderstanding of the failure mechanisms would allow the robust construction of mechanistic-based accelerated

I-39



models. Some examples involving other advanced interconnects in Back-End-Of-the-Line (BEOL) integrationschemes as well as in next generation thin silicon solar PV technology will also be discussed highlighting how wecould enable design for reliability using the synchrotron X-ray microdiffraction technique in advanced microelec-tronics and next generation thin solar PV systems.

Arief Suriadi Budiman received his B.S. in mechanical engineering from Institute ofTechnology, Bandung (ITB), Indonesia, his M.EngSc in materials engineering from MonashUniv., Australia and his Ph.D. in Materials Science and Engineering from StanfordUniversity, CA in 2008. During his doctoral candidacy at Stanford’s Department ofMaterials Science & Engineering under the supervision of Professor William D. Nix (MRSVon Hippel Award 2007), Dr. Budiman received several research awards (MRS GraduateSilver Award 2006, MRS Best Paper 2006) and contributed to several high-impact journalpublications (Acta Materialia, Applied Physics Letters, Journal of Electronic Materials). He

gave two symposium invited talks as well in the MRS spring and fall meetings in 2006. Morerecently Dr. Budiman has been awarded the prestigious Los Alamos National Laboratory (LANL) Director’sResearch Fellowship to conduct top strategic research for the energy and national security missions of the LosAlamos National Laboratory’s. At the Center for Integrated Nanotechnologies (CINT) at Los Alamos, Dr.Budiman’s research program involves nanomaterials for extreme environments with potential applications inadvanced energy systems including for next generation nuclear power reactors. Currently, at Singapore Universityof Technology & Design (SUTD), Prof. Budiman is leading a dynamic, young group researching nanomaterialsand nanomechanics and their implications for extending the extreme limits of materials as well as their applicationsin the next generation energy technologies (solar PV, extreme environments, energy storage, etc.). His work hasalso recently received the famed Berkeley Lab Scientific Highlights twice in May 2010 and June 2013 (the latterwas for his novel, innovative characterization technique that enables thin silicon solar PV technology). His deepexpertise in the synchrotron X-ray microdiffraction technique was also recently utilized to enable the first ever insitu measurements of mechanical stresses in the 3-D through-silicon via (TSV) Cu interconnect schemes in theworld - the findings were reported in a publication in Microelectronics Reliability (2012) and now one of the mosthighly cited references in the field of TSV/3D Interconnect stress measurements. He has been invited to giveinvited lectures/seminars on 3D/TSV Interconnect in various international conferences (including IEEE IITC2012, AVS Thin Films Users Group 2012, TMS Symposium for Emerging Interconnects and PackagingTechnologies 2011 and SEMATECH Workshop on 3D Interconnect Metrology at SEMICON 2011). Dr.Budiman has authored/co-authored several high-impact journal publications (Acta Materialia, Solar EnergyMaterials & Solar Cells, Materials Science Engineering A), and contributed a book chapter on “Electromigrationin Thin Films and Electronic Devices: Materials and Reliability,” Woodhead Publishing, Cambridge, 2011. He hasalso recently published a book “Probing Crystal Plasticity at the Nanoscales - Synchrotron X-ray Microdiffraction”(Springer 2015). He has two U. S. Patents and one pending.

Multi-die integration using advanced fan-out packaging technologyby Mr. WonChul Do, AmkorDate / Time Friday, 2 December 2016 / 13:50 to 14:20 hrsVenue MR332

DescriptionThe ability to integrate multiple die, passives components, and even packages is one of the key enablers for the wide-spread adoption of Fan-Out Wafer Level Package (FO-WLP). The other restrictions or challenges of traditionalFO-WLP are limited line and space capabilities, creation of 3D structures, and good die scrapping concerns asso-ciated with chip first flow. Chip last and RDL first fan-out approach can overcome many of the issues associatedwith conventional fan-out technology and provide increased I/O and circuit density within a reduced footprint and

I-40



profile. This presentation describes the process flow of a new chip last high density fan-out technology and com-pares its package capabilities with flip chip based 3D PoP at 15 mm package size. The results show the new chiplast FO-WLP has better electrical and thermal performance with very robust component and board level reliability.More complicated SiP and its further miniaturization can be realized because RDL formation is done without anymold compound before chip attach is performed and the creation of advanced 3D structures and integration of pas-sives with various surface finishes are possible. For the most aggressive designs such as interconnect for split diearchitecture or for High Bandwidth Memory (HBM), 2.5D interposer with fine line damascene Cu BEOL mustbe incorporated. For high performance and multi-die mobile products, FO-WLP with TSV-less interposer and chiplast process flow can provide the 2.5D sub-micron routing capability, lowers cost, and improves electrical perform-ances. The routing capability, process flow, and reliability results of a TSV-less package TV with 15 mm body willbe presented.

WonChul Do is Sr. director of R&D Division Group and currently leading the developmentof next generation fan-out packaging technology at Amkor Technology Korea, Inc. He waspackage development project manager for 2.5D/TSV products until he took on the currentrole in 2014. He has more than 15 year experience in the semiconductor packaging field andhas been involved in the development of flip chip package, wafer bumping and wafer levelpackaging and 2.5D/3D IC packaging. He received a Master of Science degree in ElectronicEngineering from Sogang University in Seoul, Korea.

Materials and Processes of Fan-out Wafer/Panel Level Packagingby Dr. Li Ming, ASMDate / Time Friday, 2 December 2016 / 13:50 to 14:20 hrsVenue MR333

DescriptionThe presentation will focus on the design, materials, process, and equipment of fan-out wafer/panel-level packag-ing (FOWLP or FOPLP). Various FOWLP formation methods such as chip-first with die-up, chip-first withdie-down, and chip-last (RDL-first) will be introduced. Several key process technologies, such as die pick & place,molding, redistribution layer (RDL) and solder ball mount will be discussed. Since warpage control is a critical issuefor the process, effects of various factors, such as molding material property, chip size, EMC thickness and packagefan-out ratio, on the wafer/panel warpage will be studied. Based on the applications, different RDL process (Cudamascene, polymer thin film, or printed circuit board (PCB) approach), RDL line/width, dielectric thickness, andequipment involved will be recommended and summarized.

Li Ming was awarded BSc and MSc in Materials Science and Engineering by Shanghai JiaoTong University, China, and earned her PhD in Materials Science from the University ofLondon, UK. Before joining ASM in June 2004, Dr. Li Ming worked in the University ofLondon (UK), the Institute of Materials Research and Engineering (Singapore), andChinese University of Hong Kong (Hong Kong). Currently, working in ASM as a R&DDirector for Enabling Technology, Dr. Li is heading the Process and PackagingTechnology Development Team to improve current processes and explore advanced pack-aging technologies. Dr. Li has published more than 70 papers in leading journals &

technical conferences.

I-41



3D-Printing and Electronic Packaging: Current Status and FutureChallengesby Prof. Christopher Bailey, University of GreenwichDate / Time Friday, 2 December 2016 / 13:50 to 14:20 hrsVenue MR334

DescriptionAchieving required performance, quality and reliability are key factors for the success and adoption of 3D printingtechnology in electronics manufacturing applications. This presentation details the current status of 3D-Printingwith regards different processes and technologies and their potential use for electronics manufacturing and packag-ing. In addition to this, design, modelling methodologies, and toolsets for 3D-printing will be presented. Thesetechnologies provide significant benefits to packaging engineers in term sof optimizing the performance of the 3D-prining process and the quality and reliability of the fabricated packages. The presentation will then provide asummary of the key challenges that need to be overcome before 3D-printing can become a mainstream technologyin the electronics industry.

Professor Chris Bailey received his PhD in Computational Modelling in 1988 fromUniversity of Greenwich, and an MBA in Technology Management from the OpenUniversity in 1996. Before re-joining Greenwich in 1991, he worked for three years atCarnegie Mellon University and US Steel Corporation in Pittsburgh PA. He has been activein electronic packaging and its reliability for over 20 years. He currently leads theComputational Mechanics and Reliability Group at Greenwich and a research team of 15staff whose work is primarily funded from UK, EU and US Government Organisations andIndustry. His research has resulted in over 250 publications. He is an Associate Editor for

the IEEE-CPMT Transactions; a Senior Member of IEEE, Member of IET and is currentlyVice-President for conferences for IEEE-CPMT society.

Patent Monetizationby Mr. Dexter Chin, Horizon IP Pte LtdDate / Time Friday, 2 December 2016 / 13:50 to 14:20 hrsVenue MR335

Description

“Patent monetization”, a term that has become “en vogue” in recent years. However, patent monetization hasbeen around for many years. Approaches for patent monetization include licensing, legal enforcement, sale as wellas others. The approach taken may depend on various factions, such as the objective of patent owner, the value ofthe asset, and the situation involved. We will discuss various examples of patent monetization and their impact.

I-42



With over 25 years of legal experience, Dexter offers extensive business and legal expertiseon all facets of IP portfolio creation and monetization, including IP procurement and acqui-sition, competitive analysis, strategic planning, global portfolio management, technologyevaluation and licensing negotiations.

As the founder of Horizon IP Pte. Ltd. (Singapore), and a former senior patent counsel atSiemens Corporation in Iselin (New Jersey), Dexter has developed strong expertise in manydiverse technologies and business processes, including advanced memory products, fiber

optics, imaging, semiconductor materials and processing, telecommunication services, speechrecognition signal processing, and network systems. Dexter has also counseled clients in matters related to tech-nical standards (JEDEC, SLDRAM and ATM consortia). Other professional experiences include serving as anattorney in AT&T Bell Laboratories in Murray Hill (New Jersey) and Kilpatrick Townsend & Stockton in the PaloAlto office, preparing and prosecuting domestic and foreign patent applications and conducting patent validity andinfringement analyses.

Dexter works closely with various Singapore government bodies to implement IP educational strategies and toincrease public IP awareness. He also serves on the patent agents qualifying examination committee of theIntellectual Property Office of Singapore.

Requirement for Advanced Packaging Technology of Power SemiconductorModule in High Power Density Converter for More ElectricTransportationby Dr. Rejeki Simanjorang, Rolls RoyceDate / Time Friday, 2 December 2016 / 13:50 to 14:20 hrsVenue MR336

DescriptionA recent trend in more electric technology for transportation system, such as in automotive, traction, and even inaircraft has made power electronics technology become indispensable. In aircraft industry, more electric technol-ogy will replace mechanical, hydraulic, and pneumatic system with electrical system that is more efficient, reliable,and environmentally friendly. This is commonly known as More Electric Aircraft (MEA) technology. As a result,there is increasing electric power demand in the aircraft. To satisfy such demand, power electronics converter thatconverts and control electrical power is the key enabling technology. For this weight concerned application, themain performance index of the power converters is their power density which determines how heavy and compactthe converters are.

To realize a high power density converter, the most straight-forward way will be by increasing the switching fre-quency of the converter. By doing so, the size of passive components (capacitor and inductor) will reduce. Alongwith that, thermal management of the converter should be taken care of to ensure the device operates within per-missible temperature range. High switching frequency of converter means driving the power semiconductormodule (consists of power semiconductor devices in a package) at high frequency. This can only be achieved byhigh speed switching techniques to minimize the switching losses in the power module. To enable high speedswitching there are two important factors, i.e. the power devices and the packaging around it.

In recent years, wide band gap power devices such as Silicon Carbide and Gallium Nitride have entered the com-mercial market. These power devices have the capability for high speed switching. Unfortunately, the currentlyapplied packaging technology does not allow full utilization of these wide band gap devices’ capability.

I-43



This presentation will elaborate the electrical performances of power module required for high speed switching inhigh power density converter. Parasitic impedance in power module that originates from devices and packaging lay-out will be discussed. Their effects to the power converters such as overshoot voltage, EMI issues, and switchingloss will be elaborated. Finally, advanced packaging technique to minimize these parasitic impedances will bepresented.

Rejeki Simanjorang was born in Tanah Karo, Indonesia. He received his B.Sc., M.Eng. andDr.Eng. degrees in Electrical Engineering from University of Sumatera Utara (Indonesia,1998), Bandung Institute of Technology (Indonesia, 2002) and Osaka University (Japan,2008) respectively. He was a researcher in National Institute of Advanced Industrial Scienceand Technology (AIST) and R&D partnership for Future Power Electronic Technology(FUPET), Japan from 2008 to 2013. Currently, he is a technologist in Rolls-RoyceSingapore and leading some collaboration research projects between Rolls-Royce Singaporeand external partners. His main research focuses are application of power electronic con-

verter in electrical system, design of high power density converter, and Electrical HealthMonitoring (EHM) system for power electronics.

I-44






I-48

OVERVIEW

As a leading supplier of wafer fabrication equipment and services to the global semiconductor industry, Lam Research develops innovative solutions that help our customers build smaller, faster, and more power-efficient electronic devices—the kind that are driving the proliferation of technology into our everyday lives.

To produce the tiny, complex chips used in products such as cell phones, computing devices, and entertainment gadgets, semiconductor manufacturers require highly sophisticated processes and equipment. Lam’s products play a key role in this, allowing chipmakers to build device features that are more than 1,000 times smaller than a grain of sand. In fact, nearly every leading-edge integrated circuit made today has been processed with Lam’s equipment.

Lam Research offers a broad portfolio of market-leading thin film deposition, plasma etch, photoresist strip, and wafer cleaning solutions for front-end wafer processing and advanced packaging applications. Comprehensive customer support offerings deliver value throughout the equipment lifecycle, from system installation, production ramp, and new technology upgrades through end-of-life asset management. Through collaboration, continuous innovation, and delivering on commitments, Lam is transforming atomic-scale engineering and enabling its customers to shape the future of technology.

PRODUCT OFFERINGS

Deposition Dielectric & hardmask films: VECTOR® PECVD/ALD family, SPEED® gapfill HDP-CVD family Metal films: SABRE® ECD family, ALTUS® tungsten ALD/CVD family Film treatment: SOLA® UV thermal processing family

Etch Conductor etch: Kiyo® family, Versys® Metal family Dielectric etch: Flex™ family Through-silicon via etch: Syndion® family MEMS & deep silicon etch: TCP® 9400DSiE™ family Strip Standalone strip: GAMMA® family Integrated strip: Strip45™, Microwave Stripper Clean Spin wet clean: EOS®, DV-Prime®, Da Vinci®, SP Series Plasma bevel clean: Coronus® family Support Service, spares, upgrades, technical training Reliant™ Systems – refurbished and newly built legacy products

The Lam Research logo, Lam Research, and all product names listed herein are either registered trademarks or trademarks of Lam Research Corporation or its subsidiaries. © 2016 Lam Research Corporation. All rights reserved. 201602-012EA

Key Facts Founded: 1980Revenue: ~$5.9 Billion (CY 2015)Employees: ~7,300Locations: 16 Countries WorldwideNasdaq Symbol: LRCX

HeadquartersLam Research Corporation 4650 Cushing Parkway Fremont, CA 94538 (510) 572-0200 (800) 526-7678

Contact [email protected]

[email protected]

[email protected]

[email protected]

Sponsors


I-49

Sponsors

APPLIED MATERIALS (SEA)

Address: 8 Upper Changi Road NorthContact Person: Ai Long WUTitle / Designation: Global Product Manager Tel: +65.6311.7000Email: [email protected]: www.appliedmaterials.com

Applied Materials, Inc. (Nasdaq: AMAT) is the leader in materials engineering solutions used to produce virtuallyevery new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on anindustrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations makepossible the technology shaping the future. Learn more at www.appliedmaterials.com.

ASM PACIFIC TECHNOLOGY LTD

Company Address: 4/F Watson Centre, 16-22 Kung Yip Street, Kwai Chung, Hong KongTel: 852-26192000Fax: 852-26192118Email: [email protected]: www.asmpacific.com

Email Address of the contact person: [email protected] Contact person: Tse Wing Ho, RingoContact number of the contact person: (852) 2619-2250

ASM Pacific Technology Limited (“ASMPT”), as a global technology and market leader, develops and providesleading edge solutions and materials for semiconductor assembly and packaging industries, as well as surface mounttechnology solutions in a wide range of end-user markets including electronics, mobile communications, automo-tive, industrial, LED and solar energy. ASMPT consistently invests in R&D to provide customers with innovativeand cost-efficient solutions and systems that help them to achieve higher productivity, greater reliability andenhanced quality. To learn more about ASMPT, please visit www.asmpacific.com.

INDIUM CORPORATION

Address: Indium Corporation, Asia-Pacific Operations, 29 Kian Teck Avenue, Singapore 628908Contact Person : Irene LeowTitle / Designation : Regional Sales Manager, Southeast AsiaTel : +65 6268 8678Email : [email protected] www.indium.com

Indium Corporation is a premier materials manufacturer and supplier to the global electronics, semiconductor,solar, thin-film, and thermal management markets. Products include solders and fluxes; brazes; thermal interfacematerials; sputtering targets; indium, gallium, germanium, and tin metals and inorganic compounds; andNanoFoil®. Founded in 1934, Indium has global technical support and factories located in China, Singapore,South Korea, the United Kingdom, and the USA.


PACTECH ASIA SDN. BHD.

Address: No.14, Medan Bayan Lepas, Technoplex, Phase 4, Bayan Lepas Industrial Zone, 11900 Bayan Lepas,Penang, MalaysiaContact Person: Sim SyJiunTitle / Designation: Sales & Marketing ManagerTel: +604- 644 0986 ext: 211 Email: [email protected]: http://www.pactech.com

PacTechis a worldwide leaderwith over 20 years of experience in its specialization of both wafer level packagingservices and equipment development and manufacturing. PacTech has a global coverage with facilities in Europe,USA and Asia.

PacTech offers a broad selection of wafer level packaging services including its core expertise of electrolessNiAu,NiPd and NiPdAu plating and solder bumping, as well as other extended wafer level packaging technologies suchas RDL, wafer thinning, backmellization and sawing, from low to high volume, with possibility of quick turn pro-totyping build to high volume production with competitive pricing and lead time.

Working hand-in-hand with its very own Advance Packaging Equipment business unit, PacTech provides a uniqueturnkey solution for its core technologies of electroless plating and solder bumping with possibility of both out-sourcing and in-house installation options to its customers. Other star products of PacTech’s Equipment businessunit include contactless,fluxless SB2 series for flexible soldering, and high precision assembly solution with Laplaceseries for components attach, cantilever placement and vertical chip bonding.

SILICONWARE PRECISION INDUSTRIES CO., LTD. (SPIL)

Address: No. 123, Sec. 3, Da Fong Rd., Tantzu, Taichung, Taiwan 427, R. O. C.Contact Person: Max LuTitle / Designation: Deputy DirectorTel: 886-4-2534-1525 # 7898Email: [email protected]: http://www.spil.com.tw/

Established in May 1984, Siliconware Precision Industries Co., Ltd. has become one of the leading providers ofcomprehensive semiconductor assembly and test services. SPIL posted annual sales of US$2.61 billion in 2015 andcurrently employs around 24,000 people worldwide. The company is listed on the Taiwan Stock Exchange (TSE :2325) and NASDAQ National Market under the trading symbol of SPIL.

SPIL is dedicated to meeting all customer’s integrated circuit packaging and testing requirements. Our turnkeysolutions range from bumping, wafer sort, assembly, final test, to shipment. Products include advanced leadframeand substrate based packages, which are widely used in, but not limited to, computers, tablets, cellular phones, set-top boxes, LCD monitors, wearable devices, smart appliances, digital cameras and video game consoles.

Our dedication to enhancing quality and developing technical innovations to satisfy customers’ needs has madeSPIL one of the top leaders in creating high value-added solutions, to the point where we are now the world’s thirdlargest IC packaging and testing services provider.

SPIL provides services and support to fabless design houses, integrated device manufacturers and wafer foundriesglobally. We constantly upgrade our processes to meet the demand for the most advanced manufacturing technol-ogy and also build a strong reputation for high quality products and services. This has made us a partner our

I-50

Sponsors


I-51

Sponsors

customers know they can trust. Our passion for quality has also enabled us to maintain consistent growth and max-imize returns for our shareholders.

SPIL’s headquarters is located in Taichung, Taiwan. Our offices in China, Japan, Singapore, and throughout theUnited States offer convenient support to customers’ headquarters. SPIL operates eight factories. Four of them arelocated in the central regions of Taiwan (DaFong Factory, ChungShan Factory, ZhongKe Factory, and ChangHuaFactory.) DaFong Factory, ZhongKe Factory, and ChungShan Factory are located in Taichung, ChangHua Factorylocated in ChangHua. Three other factories are located in the Hsinchu Science Park (HsinChu branch company)with one more in SuZhou, China (SPIL’s subsidiary, Siliconware Technology (SuZhou) Limited).

SPIL safeguards the interests of investors by not only conforming to all relevant stock exchange rules, but also plac-ing a high priority on corporate governance. In 2005, we began implementing Section 404 of the Sarbanes-OxleyAct of 2002 on management assessment of internal controls, which strengthened our financial reporting proceduresand disclosure qualities to protect our shareholders’ interest.

KULICKE & SOFFA

Address: 23A Serangoon North Avenue 5, #01-01, K&S Corporate Headquarters, Singapore 554369Contact Person: Marilyn SimTitle / Designation: Manager, Marketing CommunicationsTel: +65 6880-9309Email: [email protected]: www.kns.com

Kulicke & Soffa (NASDAQ: KLIC) is a leading provider of semiconductor packaging and electronic assembly solu-tions supporting the global automotive, consumer, communications, computing and industrial segments. As apioneer in the semiconductor space, K&S has provided customers with market leading packaging solutions fordecades. In recent years, K&S has expanded its product offerings through strategic acquisitions and organic devel-opment, adding advanced packaging, electronics assembly, wedge bonding and a broader range of expendable toolsto its core offerings. Combined with its extensive expertise in process technology and focus on development, K&Sis well positioned to help customers meet the challenges of packaging and assembling the next-generation of elec-tronic devices.

NIHON SUPERIOR CO. LTD.

Address : No. 5 Harper Road #04-03 Singapore 369673Contact Person : Wayne NGTitle / Designation : Regional Technical ManagerTel : +65 6741 4633Email : [email protected] : http://nihonsuperior.co.jp/english/

Nihon Superior is recognised as one of the world’s most technically innovative solder makers supplying electronicsmanufacturers in all categories through its network of offices in Asia, through licensees in Europe and the Americasand distributors in most other areas. While supplying a full range of soldering materials Nihon Superior has earnedparticular recognition for its Ag-free, Pb-free solder that has set the standard in that category. Nihon Superior’sfocus is now on developing Ag-free Pb-free solders to meet the increasing demands for cost effective reliability andapplying their unique nano-Ag technology to provide solutions for Pb-free high temperature die attach. NihonSuperior is keen to enter into technical partnerships with companies looking for soldering solutions. For moreinformation visit the Nihon Superior website http://nihonsuperior.co.jp/english/


SPTS TECHNOLOGIES LTD

Address: Ringland Way, Newport, UK, NP18 2TAContact Person: Wendy DavisTitle: Marketing Communications ManagerTel: +44 (0)1633 41400Email: [email protected]: www.spts.com

SPTS Technologies, an Orbotech company, designs, manufactures, sells, and supports advanced etch, PVD, andCVD wafer processing equipment and solutions for the global semiconductor and micro-device industries, withfocus on the Advanced Packaging, MEMS, high speed RF device, power management and LED markets.With the addition of SPTS, Orbotech is able to offer a broader range of process solutions for Advanced Packaging,which includes Orbotech’s Inkjet solutions for die level printing of package marking, underfill dams and isolationlayers.SPTS has manufacturing facilities in Newport, Wales and Allentown, Pennsylvania, and operates across 19 coun-tries in Europe, North America and Asia-Pacific. For more information please visitwww.spts.com andwww.orbotech.com.

ACCURUS SCIENTIFIC CO. LTD.

Address : No.508-51, Section 1, Wen-Sien Road, Rende District, Tainan City 717, Taiwan (R.O.C.) Contact Person : Kok-lin Heng Title / Designation : Vice President Tel : +6596684609Email : [email protected]

Accurus is among the leading providers of solder ball. As a global leader geared towards meeting the industry’s evergrowing needs for faster, smaller and higher performance chips, Accurus develops and offers a wide portfolio oftechnology and solutions. For more information about Accurus, please visit http://www.accurus.com.tw/

I-52

Sponsors


Media Partners

MEMS JOURNAL

MEMS Journal is the largest MEMS publication worldwide. We cover the most notable MEMS news and develop-ments to ensure that our subscribers explore and take advantage of the latest business development,commercialization and partnership opportunities. We provide the following services:

• strategy consulting• market research and intelligence • marketing and advertising• business development• executive and engineering recruiting• intellectual property brokerage• MEMS and semiconductor equipment brokerage

We were founded in 2003, currently have 28,700+ subscribers worldwide and attract top-level executives, engineersand researchers who are active participants in the MEMS community. For inquiries, please email us at [email protected].

CONTACTMike Pinelis, Ph.D.President and CEO248.792.9618 (office)734.277.3599 (cell)734.239.7409 (fax)Email: [email protected] Website: www.memsjournal.com

SOLID STATE TECHNOLOGY

Solid State Technology reaches the largest, most qualified community of decision makers for semiconductor andelectronics manufacturing through the magazine, email newsletters, website, webcasts and The ConFab Conference& Networking event. Topics include Advanced Packaging, MEMS, LEDs and Displays as well as current trends inthe industry.

CONTACTKerry HoffmanSales Director415.255.0390 (office)Email: [email protected]: www.solid-state.com

I-53

Partnerships


YOLE DÉVELOPPEMENT

Founded in 1998, Yole Développement has grown to become a group of companies providing marketing, technologyand strategy consulting, media and corporate finance services. With a strong focus on emerging applications using sili-con and/or micro manufacturing, the Yole Développement group has expanded to include more than 50 collaboratorsworldwide covering MEMS, Compound Semiconductors, LED, Image Sensors, Optoelectronics, Microfluidics &Medical, Advanced Packaging, Manufacturing, Nanomaterials, Power Electronics and Batteries & Energy Management.

The “More than Moore” company Yole and its partners System Plus Consulting, Blumorpho and KnowMade sup-port industrial companies, investors and R&D organizations worldwide to help them understand markets andfollow technology trends to develop their business.

CONTACTConsulting & Financial Services: Jean-Christophe Eloy( [email protected])Reports business: David Jourdan ([email protected])Marketing & Communication: Camille Veyrier ([email protected])Website: www.yole.fr / www.i-Micronews.com

Partnering Associations

THE ASSOCIATION OF ELECTRONIC INDUSTRIES IN SINGAPORE (AEIS)

The Association of Electronic Industries in Singapore (AEIS) is the only industry association representing the elec-tronics business in Singapore.

AEIS represents all facets of the electronics and supporting services industries. It covers manufacturers of industrialelectronics, electronic components and consumer electronics products as well as industrial electronics companiesassociated with the electronics industry.

Since its inception on 7 November 1973, AEIS has played a vital role in promoting the industries not only withinSingapore, but also within the international business community. This is achieved through its ongoing trade devel-opment efforts to help Singapore companies better penetrate and favorably positioned itself in the overseas markets.

CONTACTRonnie WongChief Operating Officer67761880 (office)Email: [email protected]: www.aeis.org.sg

I-54

Partnerships


SINGAPORE SURFACE ENGINEERING ASSOCIATION (SSEA)

The Singapore Metal Finishing Society (SMFS) was founded in November 1981 with the mission to promote thedevelopment of the local electroplating industry. It was renamed the Singapore Surface Finishing Society (SSFS) in1992. In 1994, we included PCB manufacturing as an integral part of our activity and admitted PCB manufactur-ers as members. In order reached out to more industries specializing in the surface engineering technology, theSociety changed its name to the Singapore Surface Engineering Association (SSEA) in 2009. With this change, theAssociation had broaden its role to include members from the powder coating, vacuum coating, corrosion protec-tion, recovery of metals and other similar coating sectors.

As an Association over the last 30 odd years, it has established a wide network of contacts dealing in the surfaceengineering field around the world. With this wealth of experience, it is actively reaching out to fellow industryplayers in the ASEAN region that are involved in the surface engineering field. Those who are interested to be inthe fraternity of the surface engineering circle should look up our web site for membership details

For more information:Email: [email protected] Website: http://www.aseansurfin.org/

SINGAPORE SEMICONDUCTOR INDUSTRY ASSOCIATION (SSIA)

Singapore Semiconductor Industry Association (SSIA) is the voice of Singapore’s semiconductor industry and iscommitted to support this important sector in Singapore in order to facilitate substantial growth of the whole semi-conductor economy of the country. SSIA is a non-profit organization, which brings together industry players,academia, and government agencies. Major activities focus on industry and talent outreach and continuing educa-tion, as well as to collectively address industry needs.

SSIA is a platform for members to reach out to new business opportunities, industry alliances, and partners. It pro-vides networking and relationship opportunities beyond the boundaries of Singapore. SSIA members today includecompanies and organizations throughout all parts of the complex and comprehensive value chain - Chip designcompanies, Manufacturers, Fabless companies, Equipment suppliers, Photovoltaic and LED companies, EDA andmaterial suppliers, Training and service providers, IP companies, Research institutes and Academia, as well as indi-vidual members.

CONTACTEmail: [email protected] Website: www.ssia.org.sg

I-55

Partnerships


Publishers

SPRINGER

The world is full of publishers. Some move forward, some go backward, and some even seem to go nowhere at all.But at Springer we move in our own unique way.With more than 200 Nobel Prize winners among the authors of our books and journal articles, it is safe to say thatSpringer has earned its place among the world’s foremost STM publishers. As an e-first company our editors dis-cover the best authors and help to disseminate their research, while our developers deliver the next big thing inscholarly communications. Our dedicated teams crisscross the globe to get journal articles, books, protocols andother products into the hands of the researchers, librarians and practitioners who need them most.

CONTACTLoyola D’SilvaEmail: [email protected]: www.springer.com

WORLD SCIENTIFIC

As the largest privately-held Singapore publisher and a leading independent publisher of books and journals for thescholarly, research and professional communities, World Scientific collaborates with prestigious organizations likethe Nobel Foundation and US National Academies Press to bring high quality academic and professional contentto researchers and academics worldwide. The company publishes about 600 books annually and 130 journals invarious fields. To find out more about World Scientific, please visit www.worldscientific.com.

For more information on World Scientific’s products and services, please contact World Scientific at Telephone:64665775 Email: [email protected]

I-56

Partnerships


I-57

Exhibitors – Foyer 5

9

10

7

8

13

15

12

4

5

614

1

1112

3

2


I-58

Exhibitors

Booth No Company

1 Lam Research

2 Sinyang – Accurus

3 Indium Corporation

4 ULVAC

5 PacTech

6 Digit-Concept

7 Crest Innovations

8 CAD-IT Consultants

9 Workforce Singapore

10 IEEE – CPMT Society

11 NordsonDage

12 AGC Asia Pacific

13 ASM Pacific Technology

14 Advisian

15 CST

IEEE Components, Packaging and Manufacturing Technology Society

Lam Research Singapore Pte LtdCompany Address: No 2 Serangoon North Avenue 5 #05-03 Singapore 554911Key Contact person: Hui-Yun CHENEmail Address: [email protected] number: 63476819

Siliconware Precision Industries Co., Ltd.Company Address: No. 123, Sec. 3, Da Fong Rd., Tantzu, Taichung, Taiwan 427, R. O. C.Key Contact person: Max LuEmail Address: [email protected]


Contact number: 886-4-2534-1525 # 7898

PacTech Asia Sdn BhdCompany Address: No 14, Medan Bayan Lepas, Technoplex, Phase 4, Bayan Lepas Industrial Zone, 11900 BayanLepas, Penang. MalaysiaKey Contact person: Nasrina Nasir (Rina)Email Address: [email protected] number: 604- 644 0986 ext: 206Indium CorporationCompany Address: 29 Kian Teck Avenue Singapore 628908Key Contact person: Sze Pei LIMEmail Address: [email protected] Contact number: 6012-2896560

Applied Materials, IncCompany Address: 8 upper changi road north Singapore 506906Key Contact person: Ai long WUEmail Address: [email protected] number: 63117000

ASM Pacific Technology LtdCompany Address: 4/F Watson Centre, 16-22 Kung Yip Street, Kwai Chung, Hong KongKey Contact person: Tse Wing Ho, RingoEmail Address: [email protected] Contact number: (852) 2619-2250

AdvisianCompany Address: 111 Somerset Road, #12-05 TripleOne Somerset, Singapore 238164Key Contact person: TAN Chee WeiEmail Address: [email protected] number: (65) 6735 8444

CSTCompany Address: 66A Neil Road, Singapore 088835Key Contact person: Klaus KrohneEmail Address: [email protected] Contact number: +65 9182 4336

ULVAC Singapore Pte LtdCompany Address: 11 Tampines Street 92, Tampines Biz-Hub, #02-08, Singapore 528872Key Contact person: Low Jian ChienEmail Address: [email protected] Contact number: 65422700/97399768

Nordson Advanced TechnologyCompany Address: 2 Corporation Road #03-10/11/12 Corporation Place Singapore 618494Key Contact person: Mr Louis Leyu, Mr Steve HurseyEmail Address: [email protected], [email protected] number: +65 98437106, +60124165253

Sinyang Accurus Pte LtdCompany Address: 11 Woodlands Close #10-08 Woodlands 11 Singapore 737853Key Contact person: Ching Soon Koh , KL Heng

I-59

Exhibitors


Email Address: [email protected] , [email protected] Contact number: +65 96394852 , +65 96684609

Crest Innovation (S) Pte LtdCompany Address: 10 Ubi Crescent, #02-25, Ubi Teckpark Lobby B, Singapore 408564Key Contact person: Thomas KohEmail Address: [email protected] Contact number: +65 9856-9731

CAD-IT Consultants (Asia) Pte LtdCompany Address: 159 Sin Ming Road #03-05 AmTech Building S575625Key Contact person: David ShakEmail Address: [email protected] number: 65084293

AGC Asia Pacific Pte LtdCompany Address: 460 Alexandra road #32-01 PSA Building S119963Key Contact person: Jasmine Cheh Email Address: [email protected] Contact number: 65084293

DIGIT CONCEPT SASCompany Address: 2, Chemin Saint Sulpice F-14740 SECQUEVILLE EN BESSINKey Contact person: Michael OBEINEmail Address: [email protected] Contact number: +33 (0) 231 354 354

Workforce Singapore

I-60

Exhibitors


I-61

General Floor Plan – LEVEL 3

1

28 9

345

7

8 9

10 1456

111213

11

No. Room Description1 MR331 Keynote / Technical Track 11 MR331 Keynote / Technical Track 12 MR332 Keynote / Technical Track 23 MR333 Technical Track 34 MR334 Technical Track 45 MR335 T h i l T k 55 MR335 Technical Track 56 MR336 Technical Track 67 Foyer 5 Exhibition & Registration8 MR330 Conference Secretariat9 MR329 PDC lunch

10 Summit 2 Conference Luncheon11 MR300 PDC1 & PDC412 MR301 PDC2 & PDC513 MR302 PDC3 & PDC614 MR303 304 Panel session


Suntec Singapore Convention & Exhibition Centre

Suntec Singapore Convention & Exhibition Centre1 Raffles Boulevard, Suntec City,Singapore 039593

Connected seamlessly to Suntec Singapore Convention & Exhibition Centre, Suntec City Mall is one of the largestshopping malls in Singapore.Boasting more than 380 retail outlets and over 100 dining options, Suntec City Mallis also home to The Fountain of Wealth, listed by the Guinness Book of Records as the World’s Largest Fountain.Suntec Singapore is centrally located in the Marina Bay area with ample parking spaces and easy access to publictransportation, restaurants, shopping and entertainment.

Read more on www.suntecsingapore.com: Meetings – Suntec Singapore Convention & Exhibition Centre Follow us: @SuntecSingapor on Twitter | suntecsingapore on Facebook

Read more on www.suntecsingapore.com: Suntec City Mall – Suntec Singapore Convention & Exhibition Centre Follow us: @SuntecSingapor on Twitter | suntecsingapore on Facebook

I-62

Conference Venue


I-63

Marina Mandarin Singapore6 Raffles BoulevardMarina SquareSingapore 039594

Marina Mandarin Singapore is a world-class, five-star luxury hotel that offers breathtaking views of Marina Bay andthe financial district.

Enjoying an excellent location in the heart of the city, the hotel has direct access to the Marina Square ShoppingMall, and is opposite the Suntec Convention & Exhibition Centre and The Esplanade-Singapore’s premier per-forming artscentre. Complemented by a host of comprehensive amenities, the hotel’s 575 well-appointed guestrooms and suites are specially tailored to meet the needs of discerning business and leisure travellers.

With a distinctively majestic atrium soaring through 21 levels of the hotel, Marina Mandarin Singapore is imbuedwith a philosophy of providing Asian grace, warmth and care in an atmosphere of relaxed elegance.

Conference Hotel


I-64

Conference Location

Prive Chijmes Marina Mandarin SingaporeSuntec Singapore Convention &#01 33, 30 Victoria Street,Singapore 187996

6 Raffles BoulevardMarina SquareSingapore 039594

Exhibition Centre1 Raffles Boulevard,Suntec City,Singapore 039593


I-65

SUTD Visit

The Singapore University of Technology and Design isThe Singapore University of Technology and Design isestablished in collaboration with MIT to advanceknowledge and nurture technically grounded leaders andinnovators to serve societal needs with a focus on Designinnovators to serve societal needs, with a focus on Design,through an integrated multi disciplinary curriculum andmulti disciplinary research.

Singapore University of Technology and Design (SUTD) VISIT on 3rd Dec 2016:Registered conference delegates will be visiting 3D fabrication lab and SUTD-MIT International design centre on3rd Dec 2016. This visit covers the SUTD introduction and Campus tour to experience Cohort classroom, ARMSlab, Fab Lab, IDC, DManD centre and historical ancient Chinese Structures at Campus.

The 2,700 sqm Fabrication Laboratory aims to allow students to design and build virtually “almost anything”.Faculty, researchers and students are able to access valuable expertise and resources to transform their creative ideasinto tangible products, and eventually, into meaningful outcomes and innovations to serve societal needs.

The IDC is a multi-million dollar centre based in Singapore at SUTD, and Cambridge, MA, USA at MIT, withacademic and industrial partners from around the world. The IDC seeks to leverage their environment and part-nerships to create the next generation of technically-based leaders, world-class scholarship, and entrepreneurship aspart of an innovation ecosystem.

DManD (Digital Manufacturing and Design Centre) has an ambitious long-term vision to create the frontiers ofdigital design and manufacturing by bringing together new ideas and multidisciplinary fields to develop new tech-nologies, catalyze new products, create entire industries centered in Singapore based on digital design andmanufacturing, and provide the human capital that will help establish Singapore as a world leader in high-value-added digital manufacturing.

Conference delegates will also have a chance to check out the historical ancient Chinese building structures, whichare gifted by Hong Kong action star Jackie Chan to the SUTD Campus. These heritage buildings, which includesa Chinese Opera stage and A pavilion. The buildings from China’s south Anhui province are said to date back tothe Qing and Ming Dynasties, around 370 years ago.


I-66

SUTD Visit

Cohort Classroom

IDC


I-67

SUTD Visit

Pavilion donated by Hong Kong action movie star Jackie Chan


I-68

General Information

LanguageThe official language of the Conference is English.

Conference Official Hotel - Marina Mandarin Singapore.6 Raffles Boulevard, Marina Square, Singapore 039594.

Conference Official Venue - Suntec Singapore Convention & Exhibition Centre.1 Raffles Boulevard, Suntec City, Singapore 039593

Dress CodeFormal office attire. The conference lanyard badge should be worn at all times at all conference functions for iden-tification.

Conference Banquet - Prive Chijmes#01-33, 30 Victoria Street, Singapore 187996

Dress code: Smart Casual.

Free Wi-FiHigh-density, high-speed, free Wi-Fi to all delegates allows up to 6,000 devices to be connected simultaneouslythroughout the entire facility. There is no password required for this Wi-Fi.

Wednesday, 30 November 2016Professional Development Courses MR 300, MR 301 & MR 302Tea Breaks Foyer 1Lunch MR 329Panel Session MR 303 & MR 304

Thursday 1 & 2 December 2016Welcome, Opening & Keynote Talks MR331 & MR332Technical (Parallel) Sessions MR331, MR332, MR333, MR334, MR335 & MR336Table Top Exhibition & Interactive Session Foyer 5 Exhibitor presentation Session Summit 2Tea Breaks & Luncheon Foyer 5 & Summit 2

Registration Fee EntitlementsStandard Registration fee is inclusive of conference kit, daily refreshments, luncheon and the conference banquet.It does not include accommodation and travel.

Conference SecretariatFor enquiries/assistance, please contact:

IEEE EPTC 2016 SecretariatC/o. C&M Consultants, #02-11, Lorong Bakar Batu, Singapore 348745Phone: +65-64921137; Fax: +65-67482556. Email: [email protected]: https://eptc-ieee.net/

On-site Secretariat(From 30 November 2016 to 2 December 2016)

Suntec Singapore Convention & Exhibition Centre1 Raffles Boulevard, Suntec City,Singapore 039593Conference Secretariat Room: MR 330


In the 13th-century Malay Annals, Sang Nila Utama, a prince from Palembang was shipwrecked and washedashore to an island. There he saw a creature which he believed was a lion. Taking it to be a good sign, he foundeda city, naming it “The Lion City” or Singapura, from the Sanskrit words “simha” (lion) and “pura” (city).

Unique is the word that best captures Singapore, a dynamic city rich in contrast and color where you’ll find a har-monious blend of culture, cuisine, arts and architecture. Singapore has grown into a thriving centre of commerceand industry. Located in the heart of fascinating Southeast Asia, Singapore is the busiest port in the world with over600 shipping lines. Brimming with unbridled energy and bursting with exciting events, the city offers countlessunique, memorable experiences waiting to be discovered.

For more information please click to visit Your Singapore - Singapore Tourism Board’s official tourism website.

Key Information at a Glance

Climate. Singapore is known for its hot and humid weather, with little variation throughout the year. The averagedaytime temperature is 31°C (88°F), dropping to around 24°C (75°F) in the evenings.

People. There are about 5.3 million people on the island. Today, the ethnic Chinese form 74.2% of the Singa-porean population, with the country’s original inhabitants, the Malays, comprising 13.3%. The Indians make up9.2%, and Eurasians and Asians of different origins making up a combined 3.3%. Singapore is also home to manyexpatriates coming from countries as diverse as North America, Australia, Europe, China, Japan and India.

Language. English is the main working language in Singapore. Other official languages used are Mandarin, Malayand Tamil.

Transportation. Getting Around - Getting around Singapore is fairly easy: the public transportation system (MRT,LRT and buses) is relatively easy to use and taxis are reasonably priced when you can get one. Getting intoSingapore - Most people arrive in Singapore by air. Its status as a major airline hub in Asia makes Singapore a nat-ural starting or ending point for a multi-country tour of Southeast Asia. Most large international airlines have routesto Singapore, in addition to the island’s own highly regarded airline, Singapore Airlines.

Currency. The currency used in Singapore is the Singapore dollar (S$). Money changing services can be found notonly at the Singapore Changi Airport but also most shopping centres and hotels around the island. You can alsoaccess the automated teller machines (ATMs) located everywhere in Singapore, that accept most of the main creditcards such as Visa, Master Card and American Express.

Visa. Most foreigners coming into Singapore do not require visas for entry and may be given social visit passes forup to 30 days upon their arrival in Singapore. However, it is best to consult your local consular office for the lat-est information with regards to coming into Singapore. If you would like to stay in Singapore for a longer period,you may apply to the Immigration & Checkpoints Authority (ICA) upon your arrival. You should have a valid pass-port with at least 6 months validity, onward or return tickets, onward facilities (such as visas or entry permits) toyour next destination, and of course, sufficient funds for your stay in Singapore.

Electricity. Singapore uses the “Type G” (British 3-pin rectangular blade) electrical plug. Voltage is 230 V, 50Hz.

Cuisine. Singapore is consequently a cosmopolitan place where people from all over the world sit down to enjoyeach other ‘s cooking. Each culture has brought with it unique cooking styles including Malay, Chinese,Indonesian, Peranakan, Indian, Thai, Japanese and Korean. There is a vast array of hawker stalls and restaurants,ranging from global franchises to gourmet delis to fancy six-star settings.

Shopping. Orchard Road would be the most popular and most commonly heard names if anyone should mentionabout shopping. This place is the central hub, also known as the “city” of Singapore, and it is well known amongtourists. Orchard Road offers major departmental stores, supermarkets, movie theatres, restaurants, famous hotelsand other entertainment outlets.

I-69

About Singapore


Cell Phone Usage. Singapore’s international dialing code is +(65). While in Singapore and if you have interna- tionalroaming service on your cell phone, you don’t have to press +(65) as it will automatically connect you to the localnumbers here.

Useful Telephone Numbers

Conference Secretariat (65) 6492 1137 Online Web & Conference Mgnt. System (65) 6492 1137 Emer-gency/Medical Police 999 (toll-free)Ambulance 995 (toll-free) 1777 (non-emergency) Flight Information 1800 542 4422Singapore Immigration Department (65) 6391 6100Singapore Tourism Board 24hrs Touristline 1800 736 2000Global Refund Singapore (GST Refund) (65) 6225 6238

Taxi Service

Dial-A-Cab (65) 6342 5222CityCab (65) 6552 1111Comfort Taxi (65) 6552 1111SMRT Taxis (65) 6555 8888SMART Cabs (65) 6485 7777TransCab (65) 6555 3333Premier Taxis (65) 6363 6888Prime Taxi (65) 6778 0808Yellow-Top Taxi (65) 6293 5545

Credit Cards

American Express 1800-296-0220Visa Global Customer Assistance 800-4481-250MasterCard Global Service 800-1100-113Diners Club (65) 6292 7566For addresses and telephone numbers of airlines, banks, hotels and other essential services, the Yellow Pages is rec-ommended. Or try City Search at 1900-777-7777 (Each call is charged at $0.50).

Norwegian Trade Council (65) 6222 1316Australia (65) 6836 4100Japan (65) 6235 8855Korea (65) 6256 1188New Zealand (65) 6235 9966USA (65) 6476 9100

The majority of foreign missions observe normal working hours of 9am to 5pm, though it is not out of the ordi-nary to find some embassies working only in the morning or having shorter opening hours, especially with regardsto visa applications. Almost all the embassies are closed on Saturdays. It is therefore recommended that you tele-phone ahead to check the office hours before visiting.

I-70

About Singapore


I-71

Prive Chijmes

“Located in the midst of CHIJMES’ lush garden setting, Privé is an oasis of relaxation for urbanites who are look-ing for a little respite from the hustle and bustle of the city.

Take in the lush greenery from the surrounding courtyard and immerse yourself in the old-world charm as yousavour a meal under the cool shade of the many trees or nurse a refreshing cocktail under a blanket of stars. Here,you’ll always find a space to call your own.

Address: #01-33, 30 Victoria Street, S(187996)

Conference Banquet


Technical Sessions


1

Wednesday, 30th November 2016

07:30 - 08:30 Registration @ Level 3 (Secretariat Room)

08:30 - 12:20

MR300, Level 3

PDC 1 : Nanotechnologies for Microelectronics Packaging Applications Prof. James E. Morris, Portland State University, USA

MR301, Level 3

PDC 2 : 3D Integrated Circuit Failure Analysis Prof. Ingrid De Wolf, IMEC, Belgium & KULeuven, Belgium

MR302, Level 3

PDC 3 : Fan-In and Fan-Out in Wafer Level Packaging Mr. Albert Lan, SPIL, Taiwan

12:20 - 13:10 Lunch @ MR329

13:10 - 17:00

MR300, Level 3

PDC 4 : Energy Efficient Thermal Management of Data Centers Prof. Yogendra Josh, Georgia Tech, USA

MR301, Level 3 PDC 5 : Internet of Things (IoT) focusing on Wireless Sensors Network and

Active RFID Dr. Holden Li, Tamasek Laboratories at Nanyang Technological University,

Singapore MR302, Level 3

PDC 6 : 2.5D and 3D-Stacked Integrated Circuits Prof. Paul D. Franzon, North Carolina State University, USA

17:30 - 19:00 Panel Speaker Presentation (Topic : Rise of China Semiconductor) @ MR 303-304, Level 3

19:00 - 19:30 Panel Q & A

�

� �

Technical Sessions

eptc2016-pbk.qxd 28/11/2016 2:44 PM Page 1

2

Thursday, 1st December 2016�

07:30 - 08:30 Registration @ Level 3(Secretariat Room)

Venue/Time MR331-332, Level 3

08:30 - 08:40 Welcome Speech (EPTC 2016 General Chair) by Mr. Ranjan Rajoo

08:40 - 09:00 Opening Address by Ms. Jean M. TREWHELLA, IEEE CPMT President

09:00 - 09:30 Keynote Address 1: Packaging Matters Mr. Tom Dolbear, AMD

09:30 - 10:00 Keynote Address 2: How to Feed Enough to Greedy IOT Monster Prof. Kanji Otsuka, Meisei University

10:00 - 10:30 Coffee/Tea break & Interactive Session I at Foyer 5

Interactive Session I at Foyer 5

[31] High Temperature Endurable Hermetic Sealing Material Selection and Reliability Comparison for IR Gas Sensor Module Packaging K. Y. Au, Ding Mian Zhi, Vivek Chidambaram, Bu Lin, Kropelnicki, Piotr, Chuan and Kai Liang

Presenter: K. Y. Au, Institute of Microelectronics, Singapore

[32] Defects in Nickel Plating Layers on Copper-Metallized Substrates Induced by Thermal Cycles Shinji Fukuda, Kazuhiko Shimada, Noriya Izu, Hiroyuki Miyazaki, Shoji Iwakiri and Kiyoshi Hirao

Presenter: Shinji Fukuda, National Institute of Advanced Industrial Science and Technology (AIST), Japan

[34] Comparison of Au/Al, Cu/Al and Ag/Al in Wirebonding Assembly and IMC Growth Behavior Norhanani Binte Jaafar and Eva Wai Leong Ching

Presenter: Norhanani Jaafar, Institute of Microelectronics, Singapore

[40] Molding Process Development for High Density I/Os Fan-Out Wafer Level Package (FOWLP) with Fine Pitch RDL Mian Zhi Ding, Ser Choong Chong, David Soon Wee Ho and Sharon Pei Siang Lim

Presenter: Mian Zhi Ding, Institute of Microelectronics, Singapore

[42] Ga-a Masking Contamination Source to prevent FIB Cross-section on Al Film Leijun Tang, Jasmine Woo and Laiyin Wong

Presenter: Leijun Tang, Institute of Microelectronics, Singapore

� �

Technical Sessions


3

[62] Study of Dielectric Materials Coating Conformality and Adhesiveness on Epoxy Mold Compound Surface B. L., Lau, David., Ho, H.Y., Hsiao and K. Yamamoto

Presenter: B. L., Lau, Institute of Microelectronics, Singapore

[67] Thermal Management of High Performance Test Socket for Wafer Level Package Yong Han, Seow Meng Low and Jason Goh

Presenter: Yong Han, Institute of Microelectronics, Singapore

[68] Package with High Thermal Conductivity of Graphite Attached onto Die Surface to Solve Hot Spot Issue Freedman Yen, Leo Hung, Nicholas Kao and Don Son Jiang

Presenter: Freedman Yen, Siliconware Precision Industries Co. Ltd., Taiwan

[79] Chip to Wafer Hermetic Bonding with Flux-less Reflow Oven Leong Ching Wai, Vivek Chidambaram Nachiappan, Sunil Wickramanayaka and Christoph Oetzel

Presenter: Leong Ching Wai, Institute of Microelectronics, Singapore

[83] Laser De-bonding Process Development of Glass Substrate for Fan-Out Wafer Level Packaging Hsiang-Yao Hsiao, Soon Wee Ho and Boon Long Lau

Presenter: Hsiang-Yao Hsiao, Institute of Microelectronics, Singapore

[139] Double-side Direct Contact Calibration Thru Kit With Non-exchanging Structure Wen Chou, Bo-You Chen, Sung-Mao Wu, Cheng-Chang Chen and Ming-Shan Lin

Presenter: Chou Wen, National University of Kaohsiung, Taiwan

[94] Through Mold Interconnects for Fan-out Wafer Level Package Soon Wee Ho, Leong Ching Wai, Soon Ann Sek, Daniel Ismael Cereno, Boon Long Lau, Hsiang-Yao Hsiao, Tai Chong Chai and Vempati Srinivasa Rao

Presenter: Soon Wee Ho, Institute Of Microelectronics, A*STAR, Singapore

[98] Development of Bottom-up Cu Electroplating Process and Overburden Reduction for Through Silicon Via (TSV) Application Gilho Hwang, Ravanethran Kalaiselvan and Hilmi B Mohamed Yusoff

Presenter: Gilho Hwang, Institute of Microelectronics, Singapore

[150] Cu Wire Bond Process Optimization for Al Remnant Surface Xiangyang Li, Haiyan Liu, Jun Li, Sean Xu� and Siong Chin Teck

Presenter: Xiangyang Li, NXP Semiconductor, China

� �

Technical Sessions


4

[118] Modeling of Differential Vertical Transition with Through Silicon Vias (TSVs) in 3D Die Stack Ka Fai Chang

Presenter: Ka Fai Chang, Institute of Microelectronics, Singapore

[123] A New Failure Mechanism of Inter Layer Dielectric Crack Haiyan Liu, Xiangyang Li, Sean Xu, Jun Li, Gary Ge

Presenter: Haiyan Liu, NXP Semiconductors, China

[115] Qualification of 3D Integrated Silicon Photonics Massimo Fere, Livio Gobbato, Matteo Tremolada, Mark Shaw, Olivier Kermarrec, Carine Besset, Roberto Curti, Fabio Pietro Fiabane and Xueren Zhang

Presenter: Massimo Fere, ST microelectronics, Italy

[162] Fan-out Wafer Level Package Electrical Performances Teck Guan Lim

Presenter: Teck Guan Lim, Institute of Microelectronics, Singapore

10:30 - 11:00 Keynote Address 3: Advances of 3D Integration in China Prof. Wenhui Zhu, Central South University

11:00 - 11:30 Keynote Address 4: Innovation in SiP & Heterogeneous Integration Dr. Bill Chen, ASE

11:30 - 12:00 Keynote Address 5: Achieving Automotive Quality Excellence : Zero Defect Performance - A foundry's perspective Mr. Jagadish CV, SSMC

12:00 - 13:30

Lunch @ Summit 2

Luncheon Talk by Ms. Jean Trewhella : Acceleration of Electronic Packaging Innovation through Collaboration

Presentation of EPTC 2015 Best Paper Awards

Presentation of IEEE CPMT Certification of Appreciation to EPTC 2016 Organizing Committee

� �

Technical Sessions


5

Invited Presenters

13:30 - 14:00

MR331

Advanced eWLB FOWLP SiP Technology Dr. Seung Wook Yoon, MBA, STATS ChipPAC

MR332

What’s happening in TSV based 3D/2.5D IC packaging: Latest market & Technology Trends Mr. Santosh Kumar, Yole Development

MR333

Opportunities and Challenges for Advanced Packaging Equipment Mr. Bob Chylak, K&S

MR334

Chip Integrated Single Phase Liquid Cooling Using Pin Fin Enhanced Microgaps Prof. Yogendra Joshi, Georgia Tech

MR335

A Novel NanoCopper-Based Advanced Packaging Material Dr. Alfred Zinn, Lockheed Martin Space Systems Company

MR336

Innovations in Packaging will enable the IoT world of the Future Dr. W. R. Bottoms, 3MTS

� �

Technical Sessions


6

Session A1 Advanced Packaging

Date/Time Thursday, 1st December 2016 / 14:00 - 15:20

Venue MR331

Chair YC MUI, Advanced Micro Devices, Singapore

[26] A Design-of-Experiment (DOE) to Optimize a SiP Design for Connectivity Applications Quan Qi and Carlton Hanna

Presenter: Quan Qi, Intel, United States

[08] Extremely Low Warpage Coreless Substrate for SiP Module Tang-Yuan Chen and Meng-Kai Shih

Presenter: Tang-Yuan Chen, ASE, Singapore

[25] Wire Bond Scalable Design Methodology Fee Wah Chong and Yee Huan Yew

Presenter: Fee Wah Chong, Package Engineering, Malaysia

[07] A New Structure & Fabrication of a High Dissipation 3D Package with Flexible Substrate Garry Ge, Gideon Lye and Sonder Wang

Presenter: Garry Ge, Tianjin China/ Kuala Lumpur, Malaysia

Technical Sessions


7

Session A2 TSV/Wafer Level Packaging


Venue MR332

Chair Navas Khan, NXP, Singapore

[36] Ultra-Fine Pitch Cu-Cu Bonding of 6µm Bump Pitch for 2.5D Application Ser Choong Chong, Ling Xie, Sunil Wickramanayaka, Vasarla Nagendra Sekhar and Daniel Ismael Cereno

Presenter: Ser Choong Chong, Institute of Microelectronics, Singapore

[52] Development of an all-in One Wet Single Wafer Process for 3D-SIC Bump Integration and its Monitoring S. Suhard, A. Iwasaki, M. Liebens, K. Stiers, J. Slabbekoorn and F. Holsteyns

Presenter: S. Suhard, Screen Semiconductor Solutions Co., Ltd., Japan

[89] 3D-SoC Integration Utilizing High Accuracy Wafer Level Bonding Lan Peng, Soon-Wook Kim, Nancy Heylen, Maik Reichardt, Florian Kurz, Thomas Wagenleitner, Erik Sleeckx, Herbert Struyf, Kenneth June Rebibis, Andy Miller, Gerald Beyer and Eric Beyne

Presenter: Lan Peng, IMEC, Belgium

[88] Thermal Stress Reliability of Copper Through Silicon Via Interconnects for 3D Logic Devices Hideki Kitada, Hiroko Tashiro, Shoichi Miyahara, Aki Dote, Shinji Tadaki and Seiki Sakuyama

Presenter: Hideki Kitada, Fujitsu Limited, Japan

Technical Sessions


8

Session A3 Interconnection Technologies


Venue MR333

Chair Poi Siong TEO, Infineon Technology, Singapore

[15] The Influence of Bond-pad Smear Crevices on IMC Corrosion in Cu-Al Bonds Mark Luke Farrugia

Presenter: Mark Luke Farrugia, NXP Semiconductors, Netherlands

[170] Copper Clip Package for high performance MOSFETs Ko Lwin Kyaw

Presenter: Ko Lwin Kyaw, N.A,Singapore

[41] Copper Wire Bonding - Elimination of Pad Peel C. E. Tan, Y. J. Pan and T. K. Cheok

Presenter: Y. J. Pan, ON Semiconductor, Malaysia

[47] A Study on Optimization of Process Parameters, Microstructure Evolution and Fracture Behavior for Full Cu3Sn Solder Joints in Electronic Packaging Peng Yao, Xiaoyan Li, Xiaobo Liang and Bo Yu

Presenter: Peng Yao, Beijing University of Technology, China

Technical Sessions


9

Session A4 Quality & Reliability


Venue MR334

Chair Kripesh VAIDYANATHAN, ITE , Singapore

[06] Study of Discrete Voids Formation in Flip-Chip Solder Joints due to Electromigration Using In-Situ 3D Laminography and Finite-Element Modeling Yuan-wei Chang, Yin Cheng, Feng Xu, Lukas Helfen, Tian Tian, Marco Di Michiel, Chih Chen, King-Ning Tu and Tilo Baumbach

Presenter: Yuan-wei Chang, Karlsruhe Institute of Technology (KIT), Germany, Taiwan

[11] Creep Corrosion on uppf Lead Frame Package Caused by Packing Materials Huan Xu, Harvinderpal Kaur, Wee Kiat Crosby Lim, Dandong Ge, Kurnia Kumara and Ming Xue

Presenter: Huan Xu, Infineon Technologies Asia Pacific, Singapore

[12] Effect of Free-Air-Ball Palladium Distribution on Palladium-Coated Copper Wire Corrosion Resistance Liao Jinzhi, Zhang Xi, Vinobaji Sureshkumar, Bayaras Abito Danila, Chong Kim Hui, Lim Yee Weon, Lo Miew Wan, Loke Chee Keong and Zaiton Bte Bakar

Presenter: Liao Jinzhi, Heraeus Materials Singapore Pte Ltd, Singapore

[17] Reliability Study of No Clean Chemistries for Lead Free Solder Paste in Vapour Phase Reflow Emmanuelle Guene and Aurelie Ducoulombier

Presenter: Aurelie Ducoulombier, Inventec Performance Chemicals, United States

Technical Sessions


10

Session A5 Materials & Substrates/Leadframe


Venue MR335

Chair Ashok, Singapore Technology, Singapore

[58] Macro and Micro-Texture Study for Understanding Whisker Growth in Sn Coatings Piyush Jagtap and Praveen Kumar

Presenter: Piyush Jagtap, Indian Institute of Science, Bangalore, India

[59] Leadframe Alloys Cu-Fe-P And Cu-Cr As An Alternative To Cu-Zr For Wheel-Speed Magnetic Sensor Package Matthew M. Fernandez, Richard Jan C. Malifer and Emily A. Gonzales

Presenter: Matthew M. Fernandez, NXP Semiconductors Cabuyao Inc, Philippines

[127] Low Stress Dielectric Layers for Wafer Level Packages to Reduce Wafer Warpage and Improve Board-Level Temperature-Cycle Reliability James T. Huneke and Swee Teck Tay

Presenter: Swee Teck Tay,Designer Molecules Inc, United States

[80] Improvement of Mechanical Properties of In-48mass%Sn Solder by Ag and Cu Addition Taiki Uemura, Taiji Sakai and Seiki Sakuyama

Presenter: Taiki Uemura, Fujitsu Laboratories Ltd., Japan

Technical Sessions


11

Session A6 Electrical Modeling & Simulations


Venue MR336

Chair Dr. Gao Siping, IHPC, A*STAR, Singapore

[19] Void Risk Prediction for Semiconductor Packages Considering the Air Venting Analysis with Fluid/Structure Interaction Method Chih-Chung Hsu, Chao-Tsai Huang and Rong-Yeu Chang

Presenter: Chih-Chung Hsu, National Tsing Hua University, Taiwan

[21] Signal Integrity Analysis of SERDES based Communication in 2.5D Integrated Systems using low Cost Silicon Interposer Andy Heinig and Muhammad Waqas Chaudhary

Presenter: Andy Heinig, Fraunhoer IIS/EAS, Germany

[28] Placement of Decoupling Capacitor on Packages Based on Effective Decoupling Radius Jun Wang, Jianmin Lu and Yushan Li

Presenter: Jun Wang, Xidian University, China

[45] Development of UHF to 2. 4GHz and 5. 2GHz Dual Band Up-conversion CMOS Mixer Ryoya Miyamoto, A. I. A. Galal and Haruichi Kanaya

Presenter: Ryoya Miyamoto, Kyushu University, Japan

Technical Sessions


12

15:20 - 16:40

Coffee/Tea Break/ Exhibitor Presentation @ Summit 2

Lam Research : Partnering for Growth in Advanced Packaging, Mr. Lee Chee Ping

SPIL : SPIL Innovative Package Solutions, Mr. Albert Lan

PacTech Asia Sdn. Bhd : PacTech Technology Introduction (commercial video)

Indium Corporation : Materials for Advance Packaging, Ms. Sze Pei LIM

AMAT : Process and Equipment Technology for Advanced Packaging, Dr. Arvind SUNDARRAJAN

ASM : Solutions For Large Format Packaging, Mr. Eugene Wee

Technical Sessions


13

Session B1 Mechanical Modeling & Simulation


Venue MR331

Chair Prof. Tay Andrew, Singapore University of Technology and Design, Singapore

[16] Modeling of the Effect of Heat Flux on Replication Accuracy using Roll-to-roll Micro Hot Embossing S. H. Chen, X. C. Shan, H. H. S. Ng, Z. W. Zhong and Mohaime B. M.

Presenter: S. H. Chen, Singapore Institute of Manufacturing Technology, Singapore

[38] Study on Board Level Solder Joint Reliability for Extreme Large Fan-Out WLP under Temperature Cycling F.X. Che

Presenter: F.X. Che, Institute of Microelectronics, Singapore

[43] Evaluation of Thermal Mechanical Reliability of Three Dimensional Packaging System with Redundant TSVs Qinghua Zeng, Jing Chen and Yufeng Jin

Presenter: Qinghua Zeng, Peking University, Beijing, China

[65] Novel Way of Characterizing Fracture Toughness of Ultra-Low Temperature SiN Films by Nanoindentation H. Zhang, G. T. W. Goh and Y. Huang

Presenter: H. Zhang, Applied Materials, Singapore

Technical Sessions


14

Session B2 Interconnection Technologies


Venue MR332

Chair Dr. Tee Tong Yan, Singapore

[48] Evolution of Structured Adhesive Wafer to Wafer Bonding enabled by Laser Direct Patterning of Polymer Resins Kai Zoschke and Klaus-Dieter Lang

Presenter: Kai Zoschke, Fraunhofer IZM, Germany

[50] Optimizing the IC Wire Short Quality via Six Sigma Approach Tee Swee Xian, Mok Fock Lin and Appukkutty Vinoth Kumar

Presenter: Tee Swee Xian, Infineon Technologies (Advanced Logic) Sdn. Bhd., Malaysia

[86] Basics of Thermosonic Bonding of Fine Alloyed Ag Wires Sarangapani Murali, B. Senthilkumar, Loke Chee Keong, Ei Phyu Phyu Theint and IT Kang

Presenter: Murali Sarangapani, Senior Principal Research Engineer, Singapore

[93] High Bandwidth Interconnect Design Opportunities in 2. 5D Through-Silicon Interposer (TSI) Roshan Weerasekera, Ka Fai Chang, Songbai Zhang, Guruprasad Katti, Hong Yu Li, Rahul Dutta and Joseph Romen Cubillo

Presenter: Ka Fai Chang, Institute of Microelectronics, Singapore

Technical Sessions


15

Session B3 Emerging Technologies


Venue MR333

Chair James How

[09] Packaging of 50 x 50 MEMS-Actuated Silicon Photonics Switching Device How Yuan Hwang, Jun Su Lee, Tae Joon Seok, Lee Carroll, Ming C. Wu and Peter O'Brien

Presenter: How Yuan Hwang, Tyndall National Institute, Ireland

[74] Large Area Roll-to-Roll Screen Printing of Electrically Conductive Circuitries B. Salam, X. C. Shan and Wei Jun

Presenter: B. Salam, Singapore Institute of Manufacturing Technology, A-Star, Singapore

[161] Systematic Approach in Testing the Viability of Mechanical Partial-cut Singulation Process towards Tin-Plateable Sidewalls for Wettable Flank on Automotive QFN Technology Patricio Cabading Jr., Sotero Malabanan, Francis Ann Llana, Lester Garcia and Ian Harvey Arellano

Presenter: Ian Harvey Arellano, ST Micro Electronics, Inc., Philippines

[134] Investigation on the Influence of Phosphor Particle Size Gradient on the Optical Performance of White Light-Emitting Diodes Jiaqi Wang, S. W. Ricky Lee and Huayong Zou

Presenter: Shi-Wei Ricky Lee, Hong Kong University of Science and Technology, Hong Kong

Technical Sessions


16

Session B4 Quality & Reliability


Venue MR334

Chair Dr. David Hutt, Loughborough University, UK

[18] Rapid Thermal Annealing to Significantly Reduce Delamination of Silver Thin Film Sputtered on Silicon Dioxide Surface Sivanantham Neelakandan, Peng Koon Chua, Kok Siong Yeo, Bo Zhao and Veera Sae Tae

Presenter: Sivanantham Neelakandan, Lumileds Singapore Pte Ltd, Singapore

[24] Leakage Detection In Wire-Bonding Gas Supply System Yue Zhang and Haoming Chang

Presenter: Yue Zhang, ASM Technology Singapore, Singapore

[46] Effect of Mechanical Properties of the Ceramic Substrate on the Thermal Fatigue of Cu Metallized Ceramic Substrates Hiroyuki Miyazaki, Shoji Iwakiri, Hideki Hirotsuru, Shinji Fukuda, Kiyoshi Hirao and Hideki Hyuga

Presenter: Hiroyuki Miyazaki, National Institute of Advanced Industrial Science and Technology (AIST), Japan

[113] Analysis of Crack and Dislocation of Direct Wafer Bonded Silicon Diaphragm Ling Eng Khoong and Tai Kwee Gan

Presenter: Ling Eng Khoong, Delphi Automotive Systems Singapore Pte Ltd, Singapore

Technical Sessions


17

Session B5 Processes and Automation/Equipment


Venue MR335

Chair Adeline Lim, KnS

[63] Alternative Dicing Solution of Multi-Project Wafer (MPW) by Stealth Dicing Jen-Hsien Chang, Pei-Ling Chen, Chien-Chih Huang, Guo-Hao Cao and Ji-Ye Wang

Presenter: Pei-Ling Chen, SPIL, Taichung, Taiwan

[75] Friction Wear Test Evaluation for Assembly Tool Ong Chen Ho, Alfred Yeo, Tan Han Guan, Ng Lay Peng, Chan Kuok Wai and Lum Chee Choong

Presenter: Ong Chen Ho, Infineon Technologies Asia Pacific Pte. Ltd., Malaysia

[107] Reduction of Cu-Ni-Pd Pad Discoloration Caused by Cu Re-deposition Laura May Antoinette Clemente, Kejun Zeng and Amit Nangia

Presenter: Laura May Antoinette Clemente, Texas Instruments Incorporated, Philippines

[106] Highly Efficient and Accurate Package Electrical Modeling Automation Po-Wei Chiu, Chun-Hung Lin and Hong Shi

Presenter: Po-Wei Chiu, Xilinx Inc., Taiwan

Technical Sessions


18

Session B6 Advanced Packaging


Venue MR336

Chair Alvin LEE, Brewer Science

[44] Systematic Development Approach New QFN LTI Package in Logic Segment Andrew Saw Khay Chwan

Presenter: Andrew Saw Khay Chwan, Infineon Technologies (Advance Logic) Sdn. Bhd, Malaysia

[95] A Comparison of Polymers and Solder Alloys by Reliability Tests on Multi-layer Redistribution Lines in Fan out Wafer Level Package Hong-Da Chang, Jay Hsiao, Kenny Liu, H.S Hsu, Andrew You, Carter Ding, Soriente Joshua Pagala, Tammy Zhu, Ivan Chang, James Jiang, Cheng-An Chang, Tommy Sun, George Pan, Nicholas Kao and Jase Jiang

Presenter: Hong-Da Chang, Siliconware Precision Industries Co., Ltd, Taiwan

[103] On-Demand Laser-Sintering of Copper Micro-Particles on Ferrite/Epoxy Resin Substrates for Power Electronics Devices Hisaya Sonoda, Ryosuke Atsumi, Mamoru Mita, Kazuhiko Yamasaki and Katsuhiro Maekawa

Presenter: Hisaya Sonoda, Ibaraki University, Japan

[112] Resist Defined bump with Fluxless Flip Chip bonding for Productivity and Reliability Lee Teck Kheng, Ser Bok Leng, Yan Guo Qiang and Tioh Beng Chuan

Presenter: Teck Kheng Lee, Institute of Technical Education, Singapore

18:30 - 22:30 Conference Banquet ( Venue : Prive @ CHIJMES )

Technical Sessions


19

Friday, 2nd December 2016

Invited Presenters

08:30 - 09:00

MR331

In the IoT development frame : How to address mechanical and thermal issue? Dr. Sebastien Gallois-garreignot, STMicroelectronics

MR332

Laser Processing of Printed Copper Interconnects On Polymer Substrates Dr. David HUTT, Loughborough Univ.

MR333

Package Miniaturization & Integration for Future Automotive Applications Mr. Andreas Fischer, Robert Bosch

MR334

Packaging and Testing of High Speed Rotor for MEMS Gas Turbine Engines Prof. Yan Xiaojun, Beihang Univ.

MR335

Technology and Market Trends in Packaging Mr. Damo Srinivas, Lam Research

MR336

Wafer Bonding as an Enabler for Microsystems Packaging and Integration Prof. Chuan Seng Tan, NTU

� �

Technical Sessions


20

Session C1 Mechanical Modeling & Simulation

Date/Time Friday, 2nd December 2016 / 09:00 - 10:00

Venue MR331

Chair Cheryl Selvanayagam, Advanced Micro Devices, Singapore

[70] Different Conservation Laws Utilized for Warpage Prediction of MUF FCCSP with 4L ETS Chih-Sung Chen, Nicholas Kao and Don Son Jiang

Presenter: Chih-Sung Chen, Siliconware Precision Industries Co. Ltd., Taiwan

[102] Analysis of Moisture Transport Between Connected Enclosures Under a Forced Thermal Gradient �. Staliulionis, S. Joshy, R. Ambat, M. Jabbari, S. Mohanty and J. H. Hattel

Presenter: ��. Staliulionis, Technical University of Denmark, Denmark

[142] Investigation of Residual Stress Effect during the Anodic Bonding Process with Different Bondable Materials for Wafer Level Packaging Design Xiaodong Hu, Maozhou Meng, Manuel Baeuscher, Ulli Hansen, Simon Maus, Oliver Gyenge, Piotr Mackowiak, Biswajit Mukhopadhyay, N. Vokmer, Oswin Ehrmann, Klaus Dieter Lang and Ha-Duong Ngo

Presenter: Ha-Duong Ngo, Fraunhofer Institute for Reliability and Microintegration, Germany

Technical Sessions


21

Session C2 Materials & Substrates/Leadframe


Venue MR332

Chair LC Tan, NXP, Malaysia

[82] Warpage Control Technique for Thin Coreless Substrates Tito T. Mangaoang Jr., Jerome J. Dinglasan, Rammil A. Seguido, Jefferson S. Talledo and Godfrey C. Dimayuga

Presenter: Tito T. Mangaoang Jr., ST Micro electronics, Inc., Philippines

[108] A Halogen-free Epoxy with Intrinsic Flame Retardance for use in Electronic PackagingSong Kiat Jacob Lim, Jian Rong Eric Phua, Yu Bai, Xiao Hu and Chee Lip Gan

Presenter: Song Kiat Jacob, Lim, Nanyang Technological University, Singapore

[61] Leadframe-To-Mold Adhesion Performance Of Different Leadframe Surface Morphologies Matthew M. Fernandez, Marianne Therese Bauca and Richard Jan C. Malifer

Presenter: Matthew M. Fernandez, NXP Semiconductors Cabuyao Inc, Philippines

Technical Sessions


22

Session C3 Wafer/Package Level & TSV Testing & Characterization


Venue MR333

Chair Dr. Kim Do Won, Institute of Microelectronics, A*STAR, Singapore

[13] Stabilization and Utilization of Coupling MOS Capacitance between TSVs Runiu Fang, Huan Liu, Min Miao, Xin Sun and Yufeng Jin

Presenter: Runiu Fang, Peking University, China

[72] Gas Chromatography Mass Spectrometry (GC-MS) application in Back End Semiconductor: Chemical Cleaning Efficiency Assessment Lee Chai Ying and Lim Koo Foong

Presenter: Lee Chai Ying, Infineon Technologies (M) Sdn. Bhd., Malaysia

[137] Packaging Solution for a Novel Silicon-based Trace Humidity Sensor using Coulometric Method Piotr Mackowiak, Biswajit Mukhopadhyay, Oswin Ehrmann, Klaus-Dieter Lang, Michael Woratz, Peter Herrmann, Olaf Pohl, Volker Noack, Suyao Zhou, Quoc Cuong Dao,Thanh Hai Hoang and Ha-Duong Ngo

Presenter: Ha-Duong Ngo, Fraunhofer IZM, Germany

Technical Sessions


23

Session C4 Emerging Technologies


Venue MR334

Chair Prof. Chris Balley, University of Greenwich, UK

[85] Evaluation of Printed Heating Elements for Continuous Flow PCR Application W. Fan, B. K. Lok and F. K. Lai

Presenter: W. Fan, Singapore Institute of Manufacturing Technology (SIMTech), Singapore

[143] Highly Efficient and Flexible Plasma based Copper Coating Process for the Manufacture of Direct Metallized Mechatronic Devices Martin Mueller and Joerg Franke

Presenter: Martin Mueller, Friedrich-Alexander University Erlangen-Nuremberg (FAU), Germany

[77] Design and Optimization of Molding Process for MEMS WLSCP Bu Lin, Ding Mian Zhi, Ding Zhi Peng, Peter Chang Hyun Kee, Zhaohui Chen and Boo Yang Jung

Presenter: Lin Bu, IME, Singapore

Technical Sessions


24

Session C5 Processes and Automation/Equipment


Venue MR335

Chair Won Chul Do, Amkor, Korea

[147] Unconventional Copper Wirebond Looping Profile Approach Allen M. Descartin, Wei Yadong, Li Jun, Xu Xuesong and Song Zhanbin

Presenter: Allen M. Descartin, NXP Semiconductors, China

[218] A Novel Flexure-based XY�� Motion Compensator: Towards High-precision Wafer-level Chip Detection Sifeng He, Hui Tang, Qian Qiu, Xiaobin Xiang, JunjieChe, Chuangbin Chen, Jian Gao, Xin Chen and Yunbo He

Presenter: Hui Tang, Guangdong University of Technology, China

Technical Sessions


25

Session C6 Interconnection Technologies


Venue MR336

Chair Ser Choong Chong, Institute of Microelectronics, A*STAR, Singapore

[117] Dissolution in Service of the Copper Substrate of Solder Joints Wayne C. W. Ng, Keith Sweatman, Tetsuya Akaiwa, Takatoshi Nishimura, Michihiro Sato, Christopher Gourlay and Sergey Belyakov

Presenter: Wayne C. W. Ng, Nihon Superior Co. Ltd., Japan

[221] Process Optimization of Zinc Based High Temperature Lead Free Solder for die Attach Application Pan Wei Chih and Baquiran Joseph Aaron Mesa

Presenter: Joseph Aaron Mesa Baquiran, Heraeus Materials Singapore Pte Ltd, Singapore

[145] Investigations on the Oxide Removal Mechanism during Ultrasonic Wedge-Wedge Bonding Process Yangyang Long, Folke Dencker, Friedrich Schneider, Benjamin Emde, Chun Li, Jörg Hermsdorf, Marc Wurz and Jens Twiefel

Presenter: Yangyang Long, Leibniz Universität Hannover, Germany

Technical Sessions


26

10:00 - 11:20

Coffee/Tea Break/ Exhibition@ Summit 2

Advisian : Realistic Simulation and Infinite Opportunities, Mr. Nishant Kumar

CST : Signal and Power Integrity Simulations in Packages and PCBs, Mr. Klaus Krohne

ULVAC : ULVAC Solutions for Printed Circuit Board Packaging, Mr. James Tan

Nordson : X-ray Metrology “Measuring the Invisible”, Mr. Steve Hursey

CAD-IT : ANSYS Multiphysics Simulation for IoT, Dr. Lee Yong Jiun

AGC Asia Pacific Pte Ltd : "We are AGC !", Ms. Jasmine Chen

Technical Sessions


27

Session D1 Advanced Packaging


Venue MR331

Chair KL Heng, ACCURUS SCIENTIFIC, Taiwan

[201] Large Format Packaging-an Alternative Format for Discrete Packaging: Its Challenges and Solutions Eric Kuah, Hao JY, WL Chan, Wu Kai, C. Ashokkumar, SC Ho and Leroy Christie

Presenter: Eric Kuah, ASM Technology Singapore, Singapore

[236] Failure Mechanisms of Solder Interconnects under Current Stressing - a Progress Update from Recent Studies on Novel Interconnect Materials Yan Cheong Chan, Yi Li, Fengshun Wu and Zhong Chen

Presenter: Yan Cheong Chan, City University of Hong Kong, Hong Kong

[33] High Throughput Thermo-compression Bonding with Pre-applied Underfill for 3D Memory Applications Adeline B. Y. Lim, Alireza Rezvani, Ryjean Datinguinoo Bacay, Tom Colosimo, Oranna Yauw, Horst Clauberg and Bob Chylak

Presenter: Adeline B. Y. Lim, Kulicke and Soffa Pte Ltd, Singapore

[35] Development of Chip-to-Wafer (C2W) bonding process for High Density I/Os Fan-out Wafer Level Package (FOWLP) Sharon Pei-Siang LIM, Ser Choong Chong, Mian Zhi Ding and Vempati Srinivasa Rao

Presenter: Lim Sharon Pei Siang, Institute of Microelectronics, Singapore

Technical Sessions


28

Session D2 TSV/Wafer Level Packaging


Venue MR332

Chair Santosh Kumar, Yole Development, France

[54] Integrated Clean for TSV: Comparison Between Dry Process and Wet Processes and their Electrical Qualification S. Suhard, Y. Li, A. Iwasaki, S. Van Huylenbroeck, S. Draper, A. Mizutani T. Dory and F. Holsteyns

Presenter: S. Suhard, Imec, Kapeldreef 75 3001 Heverlee Belgium

[104] Board Level Reliability of Automotive eWLB (embedded wafer level BGA) FOWLP Lin Yaojian, Bernard Adams, Roberto Antonicelli, Luc Petit, Daniel Yap, Kim Sing Wong and Seung Wook Yoon

Presenter: Seung Wook Yoon, Stats Chippac Pte Ltd, Singapore

[116] TAIKO Wafer Ball Attach Saskia Schröder, Markus Schröder, Wolfgang Reinert and Karl Heinz Priewasser

Presenter: Saskia Schröder, Fraunhofer ISIT Fraunhofer Str. 1, 125524 Itzehoe, Germany

[120] MEMS WLCSP Development using Vertical Interconnection Boo Yang Jung, Chen Zhaohui, Bu Lin, Ding Mian Zhi, Ding Zhi Peng and Chai Tai Chong

Presenter: Chen Zhaohui, Institute of Microelectronics, Singapore

Technical Sessions


29

Session D3 Quality & Reliability


Venue MR333

Chair Li Ming, ASM, Singapore

[55] Key Parameters Influencing Cu-Sn Interfacial Void Formation Glenn Ross, Vesa Vuorinen and Mervi Paulasto-Kröckel

Presenter: Ross G, Aalto University, Finland

[56] Thin Copper Wire Under Extreme HTSL Stress Duration: Crack Failure Mechanism Characterization R. Enrici Vaion, A Mancaleoni, L Cola, M. De Tomasi and P Zabberoni

Presenter: R. Enrici Vaion, Via C. Olivetti n°2, Agrate Brianza (MB ), Italy

[100] Measuring Die Tilt Using Shadow Moiré Optical Measurements; New Techniques for Discontinuous and Semi-Reflective Surfaces–Phase 2 Neil Hubble

Presenter: Neil Hubble, Akrometrix, United States

[125] Reliability Evaluation of Copper (Cu) Through-Silicon Via (TSV) Barrier and Dielectric Liner by Electrical Characterization Jiawei Marvin Chan, Xu Cheng, Kheng Chooi Lee, Werner Kanert and Chuan Seng Tan

Presenter: Jiawei Marvin Chan, Nanyang Technological University of Singapore, Singapore

Technical Sessions


30

Session D4 Mechanical Modeling & Simulation


Venue MR334

Chair Tang Gong Yue, Institute of Microelectronics, A*STAR, Singapore

[164] Optimization of Electronic Enclosure Design for Thermal and Moisture Management using Calibrated Models of Progressive Complexity Sankhya Mohanty, Zygimantas Staliulionis, Parizad S. Nasirabadi, Rajan Ambat and Jesper H. Hattel

Presenter: Sankhya Mohanty, Technical University of Denmark, Denmark

[167] Influence of Sintering Conditions on Mechanical Properties of Ag-nano sintered material Shota Okuno, Qiang Yu and Yusuke Nakata

Presenter: Shota Okuno, Yokohama National University, Japan

[71] Molded Wafer Level Package Evaluation and Characterization Vito Lin, Nicholas Kao and Don Son Jiang

Presenter: Vito Lin, Siliconware Precision Industries Co. Ltd.,Taiwan

[173] Finite Element Analysis of Arbitrarily Complex Electronic Devices Mario Gschwandl, Peter Fuchs, Klaus Fellner, Thomas Antretter, Thomas Krivec and Tao Qi

Presenter: Mario Gschwandl, Polymer Competence Center Leoben, Austria

Technical Sessions


31

Session D5 Materials & Substrates/Leadframe


Venue MR335

Chair Tan Chuan Seng, Nanyang Technology University, Singapore

[144] Characterization of Anodic Bondable LTCC for Wafer-Level Packaging Xiaodong Hu, Manuel Bäuscher, Piotr Mackowiak, Yucheng Zhang, Ole Hoelck, Hans Walter, Martin Ihle, Steffen Ziesche, Ulli Hansen, Simon Maus, Oliver Gyenge, Biswajit Mukhopadhyay, Oswin Ehrmann, Klaus-Dieter Lang and Ha-Duong Ngo

Presenter: Xiaodong Hu, Technischen Universität Berlin, China

[180] A Study on Dimensional Variation in Flexible Printed Circuits During Post-Lamination Baking Ruey Jun Yan, Zalina Abdullah, Chee Wei Mok, Mihai D. Rotaru and Suan Hui Pu

Presenter: Ruey Jun Yan, University of Southampton Malaysia Campus, Malaysia

[209] Warpage Behavior of SiP's built with Different Bumping Solutions, Substrate Designs and Encapsulant Materials Quan Qi and Carlton Hanna

Presenter: Quan Qi, Intel, United States

[119] Study of De-gate Remnant Resolution with High Reliability Performance Moulding Compound Ng S.P, Wang H.T and Goo F.T

Presenter: Goo F.T, Infineon, Malaysia

Technical Sessions


32

Session D6 Electrical Modeling & Simulation


Venue MR336

Chair Mihai Rotaru, University of Southampton , UK

[57] Determination of Dielectric Thickness, Constant, and Loss Tangent from Cavity Resonators A. Ege Engin, Ivan Ndip, Klaus-Dieter Lang and Jerry Aguirre

Presenter: A. Ege Engin, San Diego State University, United States

[64] A Novel Trench Routing for Next-Generation High-Speed Serial Buses Beyond 10Gbps Applications Jackson Kong, Bok Eng Cheah, Khang Choong Yong, Howard Heck and Louis Lo

Presenter: Jackson Kong, Intel Microelectronics (M) Sdn. Bhd., Malaysia

[76] Novel Impedance Matching Technique for Pogo Pin Design Chee Hoe Lin

Presenter: Chee Hoe Lin, AMD Singapore, Singapore

[101] High Efficiency Energy Harvesting Circuit with Impedance Matched Antenna Yuharu Shinki, Kyouhei Shibata, Mohamed Mansour and Haruichi Kanaya

Presenter: Yuharu Shinki, Kyushu University, Japan

12:40 - 13:50

Lunch @ Summit 2

Presentation of Appreciation to Invited Papers' Authors

18th Electronic Packaging Technology Conference Organisation Committee Appreciation

19th Electronic Packaging Technology Conference Introduction

Technical Sessions


33

14:30 - 15.30 IEEE Region 10 CPMT Chapter's Chairs meeting @ Summit 2 Dr. Orii Yasumitsu, Director, Region 10

Invited Presenters

13:50 - 14:20

MR331

Enabling Design for Reliability in Advanced Interconnects for 3D IC and Next Generation Solar PV (Photovoltaics) Systems Prof. Arief Budiman, SUTD

MR332

Multi-die integration using advanced fan-out packaging technology Mr. WonChul Do, Amkor

MR333

Materials and Processes of Fan-out Wafer/Panel Level Packaging Dr. Li Ming, ASM

MR334

3D-Printing and Electronic Packaging: Current Status and Future Challenges Prof. Christopher Bailey, University of Greenwich

MR335

Patent Monetization Mr. Dexter Chin, Horizon IP Pte Ltd

MR336

Requirement for Advanced Packaging Technology of Power Semiconductor Module in High Power Density Converter for More Electric Transportation Dr. Rejeki Simanjorang, Rolls Royce

Technical Sessions


34

Session E1 Quality & Reliability


Venue MR331

Chair Chin Hui CHONG, Micron Technology, Singapore

[129] Bromine induces Corrosion in Reliability Test Ni Hsing Lee, Cheng Fu Yu, Orla O Halloran, Abdellatif Firiti, Zemre Acar , Nicolas Cannesan, Yuan Wen Hao, Jyun Ji Chen, Johan Tsai, Peter Sun and Sharon Chen

Presenter: Ni Hsing Lee, NXP Semiconductors, Taiwan

[133] Improving Intrinsic Corrosion Reliability of Printed Circuit Board Assembly Rajan Ambat and Hélène Conseil-Gudla

Presenter: Rajan Ambat, Technical University of Denmark, Denmark

[211] High Lead Solder Failure and Microstructure Analysis in Die Attach Power Discrete Packages Kenny Chiong, Hong Wen Zhang and Sze Pei Lim

Presenter: Kenny Chiong, Sr. Technical Engineer, Singapore

[148] Flip Chip Laser Mark Bare Die Strength Characterization Kesvakumar Muniandy, Ilko Schmadlak, Betty Yeung, Matt Lauderdale and Trent Uehling

Presenter: Kesvakumar Muniandy, NXP Semiconductor, Malaysia

Technical Sessions


35

Session E2 TSV/Wafer Level Packaging


Venue MR332

Chair Damo Srinivas, Lam Research, Singapore

[122] Novel WLCSP Technology Solution for Fusion Device of CMOS Integrated Circuit with MEMS. Takahide Murayama, Toshiyuki Sakuishi and Yasuhiro Morikawa

Presenter: Yasuhiro Morikawa, ULVAC,Inc.Institute of Semiconductor and Electronics Technologies Division 3rd Section 1st, Japan

[156] Integration of Low Temperature PECVD Deposited Silicon Oxides with Advanced Packaging Chunmei Wang, Steven Lee, Xiangyu Wang, King Jien Chui and Mingbin Yu

Presenter: Chunmei Wang, Institute of Microelectronics, Singapore

[185] Overlay Performance of Through Si Via Last Lithography for 3D Packaging Warren W. Flack, Robert Hsieh, Gareth Kenyon, John Slabbekoorn, Piotr Czarnecki, Bert Tobback, Stefaan Van Huylenbroeck, Michele Stucchi, Tom Vandeweyer and Andy Miller

Presenter: Gareth Kenyon, Ultratech, USA

[212] An Accurate Calculation Method on Thermal Effectiveness of TSV and Wire Yudan Pi, Wei Wang and Yufeng Jin

Presenter: Yudan Pi, Peking University, China

Technical Sessions


36

Session E3 Interconnection Technologies


Venue MR333

Chair Hong Meng HO, STATS ChipPAC Pte Ltd., Singapore

[157] The Exploration and Characterization of Insulated Au-Flash PdCu Wire Bonding Applications Siong Chin Teck, Eu Poh Leng, Tan Lan Chu, Su Dan, Tok Chee Wei, Loh Wan Yee and Zhangxi

Presenter: Siong Chin Teck, NXP Semiconductors, Malaysia

[160] Manufacturing and Characterization of Die to Die Interconnections for 3D Applications in Harsh Environmental Conditions C. Hartler, J. Siegert, F. Schrank, M. Schrems, Z. Hajdarevic and S. Bulacher

Presenter: C. Hartler, AMS AG, Austria

[225] Pressureless Low Temperature Sintering Paste for NiAu PCB Substrate Yong Ling Xin, Tan Juo Yan, Wolfgang Schmitt, Jens Nachreiner and Chew Ly May

Presenter: Ling Xin Yong, Heraeus, Singapore

[237] Double Side Sintered IGBT 650V/ 200A in a TO-247 Package for Extreme Performance and Reliability Gustavo Greca, Paul Salerno, Jeffrey Durham, Francois Le Henaff, Jean Claude Harel, Johan Hamelink and Weikun He

Presenter: Johan Hamelink, Boschman Technologies, Netherlands

Technical Sessions


37

Session E4 Emerging Technologies


Venue MR334

Chair Charles LEE, ASE, Singapore

[78] Gravure Printing of Ag Electrodes for Electroluminescent Lighting Vasudivan Sunappan

Presenter: Vasudivan Sunappan, Singapore Institute of Manufacturing Technology, Singapore

[178] Embedding of Wearable Electronics into Smart Sensor Insole M. Hubl, O. Pohl, V. Noack, P. Hahlweg, C. Ehm, M. Derleh, T. Weiland, E. Schick, H-H. Müller, D. Hampicke, P. Gregorius, T. Schwartzinger, T. Jablonski, J.-P. Maurer, R. Hahn, O. Ehrmann, K.-D. Lang, E. Shin and H.-D. Ngo

Presenter: M. Hubl, University of Applied Science (HTW), Germany

[190] Copper Circuit Traces by Laser Cladding with Powder Injection for Additive Manufactured Mechatronic Devices Martin Mueller, Oliver Hentschel, Michael Schmidt and Joerg Franke

Presenter: Martin Mueller, Friedrich-Alexander University Erlangen-Nuremberg (FAU), Germany

[188] An Innovative Approach to Accelerate High Temperature Operating Endurance Test for Automotive Electronic Control Units. Abdalla Youssef, Ingo Birner, Robert Vodiunig, Jean Thierauf, Holger Voelkel, Hans Walter, Andreas Middendorf, Klaus-Dieter Lang

Presenter: Abdalla Youssef, BMW Group, Germany

Technical Sessions


38

Session E5 Materials & Substrates/Leadframe


Venue MR335

Chair Vempati Srinivasa RAO, Institute of Microelectronics, A*STAR, Singapore

[224] Effect of Doping Element on the Interfacial Reaction Behavior of Ag Alloy Wires Bonding on Al Pad after HTST and TCT Tests Yu-Wei Lin, Mei-Chen Su, Wei-Hsiang Huang, Ying-Ta Chiu, Te-Ping Shih and Kwang-Lung Lin

Presenter: Yu-Wei Lin, R&D, Precision Packaging Materials Corp. (PPM), Taiwan

[96] Influence of Package Lead Type Onto Final Test Contacting Praveen Kumar Ramamoorthy, Tan Han Guan, Alfred Yeo and Yang Kai

Presenter: Praveen Kumar Ramamoorthy, Infineon Technologies Asia Pacific Pte Ltd, Singapore

[223] Test Method to Evaluate a Robust Ball Grid Array (BGA) Ball Mount Flux Sheng-Hung Chou, Yan Liu, Maria Durham, Sze Pei Lim, Te-Hua Fang and Yu-Jen Hsiao

Presenter: Sheng-Hung Chou, Indium Corporation 29 Kian Teck Avenue Singapore 628908

Technical Sessions


39

Session E6 Electrical Modeling & Simulation


Venue MR336

Chair Wui-Weng WONG, Advanced Micro Devices, Singapore

[136] Performance Modeling and Broadband Characterization of Chip-to-Chip Interconnects with Rough Surfaces Rohit Sharma and Somesh Kumar

Presenter: Rohit Sharma, IIT Ropar, India

[158] Signal Integrity and Crosstalk Analysis of the Transmission Lines on SOI Substrate for High-Speed up to 50 GHz Do-Won Kim, Chao Li and Patrick Lo Guo Qiang

Presenter: Do-Won Kim, Institute of Microelectronics, Singapore

[184] Multi-Port High Bandwidth Interconnect Equivalent Circuit Model for 3. 2 Gbps Channel Simulation Hui Lee Teng and Yee Huan Yew

Presenter: Hui Lee Teng, Altera Corporation, Malaysia

[227] Antenna Array Integrated on Multilayer Organic Package for Millimeter-wave Applications Cheng-Yu Ho, Ming-Fong Jhong, Po-Chih Pan, Chen-Chao Wang, Chun-Yen Ting, Ken-Huang, Lin, En-Yi, Hsueh, Shang-Hao, Liu, and Hung-Chia and Chang

Presenter: Cheng-Yu Ho, Advanced Semiconductor Engineering Group, Taiwan

Technical Sessions


40

15:40 - 16:10 Coffee/Tea break & Interactive Session II at Foyer 5

Interactive Session II at Foyer 5

[97] Thermal Design and Temperature Gradient Analysis for a Thermoelectric Energy Harvest Device in Off-shore and Marine Application Gongyue Tang, Sarbudeen Mohamed Rabeek and Muthukumaraswamy Annamalai Arasu

Presenter: Gongyue Tang, Institute of Microelectronics, Singapore

[130] Modeling The Package IP Physical Model and Verification. Che-Shuan Lin, Bo-You Chen, Sung-Mao Wu, Cheng-Chang Chen and Ming-Shan Lin

Presenter: Che-Shuan Lin, National University of Kaohsiung, Taiwan

[92] Development of Wafer Level Laminated Magnetic Thin Film for Integrated Voltage Regulator Application Jun Yu, Muthukumaraswamy Annamalai Arasu and Sunil Wickramanayaka

Presenter: Jun Yu, Institute of Microelectronics, Singapore

[152] Evaluation on Multiple Layer PBO-based Cu RDL Process for Fan-Out Wafer Level Packaging (FOWLP) Soh Siew Boon, K.J. Chui, David Ho S.W., S.A. Sek, Mingbin Yu, Prayudi Lianto, Yu Gu, Guan Huei See and Marvin L. Bernt

Presenter: Serine Soh, Institute of Microelectronics, Singapore

[171] Fabrication Process of a Triple-Layer Stacked TSV Interposer for Switch Matrix Consisting of Eight RF Chips Wei Meng, Yong Guan, Qinghua Zeng ,Jing Chen and Yufeng Jin

Presenter: Wei Meng, Peking University, China

[179] Interposer Fabrication with Annular Copper TSV and Multi-layered Redistribution Layer Yong Guan, Shenglin Ma, Qinghua Zeng, Wei Meng, Jing Chen and Yufeng Jin

Presenter: Yong Guan, Peking University, China

[181] Fine Pitch RDL Patterning Characterization Chen Bing, Soh Siew Boon, Ho Soon Wee and Jung Boo Yang

Presenter: Bing Chen, Institute of Microelectronics, Singapore

[183] Evolution of the Topographical and Chemical Signatures of Plasma-treated Surfaces along the Staging Time Pathway Ian Harvey Arellano and Amor Zapanta

Presenter: Ian Harvey Arellano, ST Micro electronics, Inc., Philippines

� �

Technical Sessions


41

[199] Process Considerations, Process Challenges and Manufacturing Systems for Roll-to-Roll Processing X. C. Shan, S. H. Chen, B. Salam, M. B. Mohahidin and J. Wei

Presenter: X. C. Shan, Senior Scientist, Singapore

[207] Plasma Etching of SiO2 with Tapered Sidewall for Thin Film EncapsulationVladimir Bliznetsov, Bin Li, Jae Wung Lee and Huamao Lin

Presenter: Vladimir Bliznetsov, Institute of Microelectronics, Singapore

[210] Ultrasonic Power Closed-loop Control on Wire Bonder He Yunbo, Hu Yongshan, Chen Xin, Gao Jian, Yang Zhijun, Zhang Kai, Chen Yun, Zhang Yu, Tang Hui and Ao Yinhui

Presenter: Hu Yongshan, Guangdong University of Technology, China

[213] Novel Correctable Testing Interface for High Speed/Frequency Device Testing Chih-Cheng Chuang, Kuan-I Cheng, Sung-Mao Wu, Lung-Shu Huang and Bang-Cheng Chiu

Presenter: Chih-Cheng Chuang, National University of Kaohsiung, Taiwan, Taiwan

[246] Thermal Effect on Fan-out Wafer Level Package Strength Cheng Xu, Z. W. Zhong and W. K. Choi

Presenter: Cheng Xu, Nanyang Technological University, Singapore

[267] Thermomechanical Reliability of a Cu-TSV Integration Model based on 3D Fabrication Processes Yunna Sun, Seung-lo Lee, Yanmei Liu, Jiangbo Luo, Yan Wang, Guifu Ding, Hong Wang and Jinyuan Yao

Presenter: Yunna Sun, Shanghai Jiao Tong University, China

[268] A High Efficient Integrated Heat Dissipation Systems with CNT Array based Heat Lines and Microchannel Heat Sink in 3D ICs Yunna Sun, Seung-lo Lee, Qiu Xu, Jiangbo Luo, Hongfang Li, Yan Wang, Guifu Ding and Xiaolin Zhao

Presenter: Yunna Sun, Shanghai Jiao Tong University, China

[193] The Study of Bond Pad Discoloration in Power Package Assembly Zhang Ruifen, Baquiran and Joseph Aaron Mesa

Presenter: Zhang Ruifen, project lead, Singapore

[216] Effects of Humidity on the Electro-Optical-Thermal Characteristics of High-Power LEDs T.K. Law, Fannon Lim, Y. Li, J.W.Ronnie Teo and Sophia Wei

Presenter: Thong Kok Law, University of Glasgow, UK. Nanyang Polytechnic, Singapore

� �

Technical Sessions


42

Session F1 Mechanical Modeling & Simulation


Venue MR332

Chair Prof. Yan Xiaojun, Beihang University, China

[194] Brittle Fracture and Damage in Bond Pad Stacks - A Study of Parameter Influences in Coupled XFEM and Delamination Simulation of Nanoindentation J. Albrecht, J. Auersperg, G. M. Reuther, P. W. Kudella, J. Brueckner, S. Rzepka and R. Pufall

Presenter: J. Albrecht, Micro Materials Center, Germany

[202] Modelling Solder Extrusion Using J-integral Method Cheryl Selvanayagam and Teng Di Sheng

Presenter: Cheryl Selvanayagam, AMD, Singapore

[208] Effect of Interconnect Plasticity on Soldering Induced Residual Stress in Thin Crystalline Silicon Solar Cells Sasi Kumar Tippabhotla, Ihor Radchenko, Wenjian Song, N. Tamura, Andrew A. O. Tay and A. S. Budiman

Presenter: Sasi Kumar Tippabhotla, Singapore University of Technology, Singapore

[168] Development of Evaluation Method That Takes into Account the Effect the Fine Structure of Adhesive Interface for Delamination Strength of the Packaging Resin Yukichi Furuyama, Okihisa Honda and Qiang Yu

Presenter: Yukichi Furuyama, Yokohama National University, Japan

Technical Sessions


43

Session F2 TSV/Wafer Level Packaging


Venue MR333

Chair Boo Yang JUNG, Global Foundries, Singapore

[195] Isolate Micro-bump Process Development and Improvement H. Y. Li, Leong Yew Wing, Hwang Gilho, Chong Kok Piau, Norhanani Binte Jaafar and Surasit Chungpaiboonpatana

Presenter: H. Y. Li, Institute of Microelectronics, Singapore

[233] Understanding Size Effects in the Advanced Through-Silicon Via Interconnect Schemes for 3D ICs Imran Ali, Ihor Radchenko, Sasi Kumar Tippabhotla, Song Wenjian M.Ridhuan, Andrew A. O. Tay, Nobumichi Tamura, Seung Min Han and Arief SuriadiBudiman

Presenter: Imran Ali, Pillar of Engineering Product Development, Singapore University of Technology & Design, Singapore 138682, Singapore

[205] Laser Multi Beam Full Cut Dicing of wafer level chip-scale packages (Fan In) Jeroen van Borkulo, Eric M. M. Tan and Richard Boulanger

Presenter: Jeroen van Borkulo, ASM Pacific Technology Ltd., Netherlands

[191] Thermal-Mechanical Reliability Assessment of TSV Structure for 3D IC Integration Huan Liu, Qinghua Zeng, Yong Guan, Runiu Fang, Xin Sun, Fei Su, Jing Chen, Min Miao and Yufeng Jin

Presenter: Huan Liu, Peking University, Beijing, China

Technical Sessions


44

Session F3 Quality & Reliability


Venue MR334

Chair Alfred YEO, Infineon Technology, Singapore

[172] Reliability Evaluation of Car Power Module using Electrical-Thermal-Structural Coupled Analysis based on Field Driving Data Shingo Nakayama, Hirotaka Morita and Qiang Yu

Presenter: Shingo Nakayama, Yokohama National University, Japan

[111] Drop Impact Reliability Study of High Density Fan-Out Wafer Level Package Zhaohui Chen, Faxing Che, Mian Zhi Ding, David Soon Wee Ho, Tai Chong Chai and Vempati Srinivasa Rao

Presenter: Zhaohui Chen, Institute of Microelectronics, Singapore

[189] Copper Ball Bond Recipe Cliff Test on Two Pad Aluminum Thicknesses Kok Inn Hoo, Edsel DeJesus, Priscila Brown, Rachel Wynder, Alan Eddington and Stevan Hunter

Presenter: Kok Inn Hoo, ON Semiconductor, Malaysia, ON Semiconductor, USA, and BYU-Idaho, USA

[135] Semi-Empirical Prediction of Moisture Build up in an Electronic Enclosure using Analysis of Variance (ANOVA) Parizad Shojaee Nasirabadi, Hélène Conseil-Gudla, Sankhya Mohanty, Masoud Jabbari, Rajan Ambat and Jesper H. Hattel

Presenter: Parizad Shojaee Nasirabadi, Technical University of Denmark, Denmark

Technical Sessions


45

Session F4 Advanced Packaging


Venue MR335

Chair Shan GAO, Global Foundries, Singapore

[140] 3D IC Assembly using Thermal Compression Bonding and Wafer-Level Underfill-Strategies for Quality Improvement and Throughput Enhancement Teng Wang, Pieter Bex, Giovanni Capuz, Fabrice Duval, Fumihiro Inoue, Carine Gerets, Julien Bertheau, Kenneth June Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Masanori Natsukawa, Kazuyuki Mitsukura and Keiichi Hatakeyama

Presenter: Kenneth June Rebibis, IMEC, Belgium

[99] Copper Wire Bond Pad/IMC Interfacial Layer Crack Study During HTSL (high temperature storage life) Test Mingchuan Han, Miao Wang, Lidong Zhang, Beiyue Yan, Jun Li, Meijiang Song and Varughese Mathew; Allen M. Descartin

Presenter: Allen M. Descartin, NXP semiconductor Tianjin, China

[200] Integration of MEMS/ Sensors in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP) André Cardoso, Steffen Kroehnert, Raquel Pinto, Elisabete Fernandes and Isabel Barros

Presenter: Steffen Kroehnert, NANIUM S. A., Portugal and Germany

[146] Copper Electrodeposition Advancements for FOWLP Bryan Buckalew

Presenter: Bryan Buckalew, Lam Research

Technical Sessions


46

Session F5 Thermal Characterization & Cooling Solutions


Venue MR336

Chair Edwin Teo, Nanyang Technology University, Singapore

[66] Heat Dissipation Capability of Package with Integrated Processor and 3D-Stacked Memory Yong Han, F. X. Che, Sharon Seow Huang Lim and Masaya Kawano

Presenter: Yong Han, Institute of Microelectronics, Singapore

[114] A Way for Measuring the Temperature Transients of Capacitors Zoltan Sarkany and Marta Rencz

Presenter: Zoltan Sarkany, Mentor Graphics, Hungary

[109] Thermal Design and Analysis of High Power SiC Module with Low Profile and Enhanced Thermal Performance Tang Gongyue, Lee Jong Bum and Chai Tai Chong

Presenter: Tang Gongyue, Institute of Microelectronics, Singapore

Session IEEE CPMT PKG Roadmap Workshop


Venue MR331

Chair Bill Chen, ASE, Singapore

17:30 - 18:00

Summit 2

Keynote Address 6: Light-Emitting Diodes for Non-Lighting Applications ~ beyond seeing and being seen ~ Prof. Ricky SW Lee, Hong Kong Univ. Science & Technology

18:00 - 18:20 Closing Ceremony and Lucky Draw @ Summit 2

�

Technical Sessions


47

Saturday, 3rd December 2016 �

08:30 - 12:00SUTD(Singapore University of Technology and Design) Visit to ( 3D fabrication lab / International Design Centre / Jackie Chan Ancient Chinese Structures)

�

Technical Sessions


48

Abdullah, Zalina 31Acar, Zemre 34Adams, Bernard 28Aguirre, Jerry 32Akaiwa, Tetsuya 25Albrecht, J. 42Ali, Imran 43Ambat, R. 20Ambat, Rajan 30, 34, 44Antonicelli, Roberto 28Antretter, Thomas 30Arasu, Muthukumaraswamy Annamalai 40Arellano, Ian Harvey 15, 40Ashokkumar, C. 27Atsumi, Ryosuke 18Au, K. Y. 2Auersperg, J. 42Bacay, Ryjean Datinguinoo 27Baeuscher, Manuel 20Bai, Yu 21Bailey, Christopher 33Bakar, Zaiton Bte 9Baquiran 41Barros, Isabel 45Bauca, Marianne Therese 21Baumbach, Tilo 9Belyakov, Sergey 25Bernt, Marvin L. 40Bertheau, Julien 45Besset, Carine 4Bex, Pieter 45Beyer, Gerald 7, 45Beyne, Eric 7, 45Bing, Chen 40Birner, Ingo 37Bliznetsov, Vladimir 41Boon, Soh Siew 40Borkulo, Jeroen van 43Bottoms, W. R. 5Boulanger, Richard 43Brown, Priscila 44Brueckner, J. 42Buckalew, Bryan 45Budiman, A. S. 42Budiman, Arief 33Bulacher, S. 36Bum, Lee Jong 46Bäuscher, Manuel 31Cabading Jr., Patricio, 15Cannesan, Nicolas 34Cao, Guo-Hao 17Capuz, Giovanni 45

Cardoso, André 45Carroll, Lee 15Cereno, Daniel Ismael 3, 7Chai, Tai Chong 3, 44Chan, Jiawei Marvin 29Chan, WL 27Chan, Yan Cheong 27Chang, Cheng-An 18Chang, Haoming 16Chang, Hong-Da 18Chang, Hung-Chia 39Chang, Ivan 18Chang, Jen-Hsien 17Chang, Ka Fai 4, 14Chang, Rong-Yeu 11Chang, Yuan-wei 9Chaudhary, Muhammad Waqas 11Che, F. X. 13, 46Che, Faxing 44Cheah, Bok Eng 32Chen, Bill 4Chen, Bo-You 3, 40Chen, Cheng-Chang 3, 40Chen, Chih 9Chen, Chih-Sung 20Chen, Chuangbin 24Chen, Jing 13, 40, 43Chen, Jyun Ji 34Chen, Pei-Ling 17Chen, S. H. 13, 41Chen, Sharon 34Chen, Tang-Yuan 6Chen, Xin 24Chen, Zhaohui 23, 44Chen, Zhong 27Cheng, Kuan-I 41Cheng, Xu 29Cheng, Yin 9Cheok, T. K. 8Chidambaram, Vivek 2Chih, Pan Wei 25Chin, Dexter 33Ching, Eva Wai Leong 2Chiong, Kenny 34Chiu, Bang-Cheng 41Chiu, Po-Wei 17Chiu, Ying-Ta 38Choi, W. K. 41Chong, Chai Tai 28, 46Chong, Fee Wah 6Chong, Ser Choong 2, 7, 27Choong, Lum Chee 17

Author Index


Chou, Sheng-Hung 38Chou, Wen 3Christie, Leroy 27Chu, Tan Lan 36Chua, Peng Koon 16Chuan, Tioh Beng 18Chuang, Chih-Cheng 41Chui, K. J. 40Chui, King Jien 35Chungpaiboonpatana, Surasit 43Chwan, Andrew Saw Khay 18Chylak, Bob 5, 27Clauberg, Horst 27Clemente, Laura May Antoinette 17Cola, L 29Colosimo, Tom 27Conseil-Gudla, Hélène 34, 44Cubillo, Joseph Romen 14Curti, Roberto 4Czarnecki, Piotr 35Dan, Su 36Danila, Bayaras Abito 9Dao, Quoc Cuong 22David, Ho 3DeJesus, Edsel 44Dencker, Folke 25Derleh, M. 37Descartin, Allen M. 24, 45Dimayuga, Godfrey C. 21Ding, Carter 18Ding, Guifu 41Ding, Mian Zhi 2, 27, 44Dinglasan, Jerome J. 21Do, WonChul 33Dolbear, Tom 2Dory, A. Mizutani T. 28Dote, Aki 7Draper, S. 28Ducoulombier, Aurelie 9Durham, Jeffrey 36Durham, Maria 38Dutta, Rahul 14Duval, Fabrice 45Eddington, Alan 44Ehm, C. 37.Ehrmann, O. 37Ehrmann, Oswin 20, 22, 31Emde, Benjamin 25Engin, A. Ege 32Fan, W. 23Fang, Runiu 22, 43Fang, Te-Hua 38

Farrugia, Mark Luke 8Fellner, Klaus 30Fere, Massimo 4Fernandes, Elisabete 45Fernandez, Matthew M. 10, 21Fiabane, Fabio Pietro 4Firiti, Abdellatif 34Fischer, Andreas 19Flack, Warren W. 35Foong, Lim Koo 22Franke, Joerg 23, 37Franzon, Paul D. 1Fuchs, Peter 30Fukuda, Shinji 2, 16Furuyama, Yukichi 42Galal, A. I. A. 11Gallois-Garreignot, Sebastien 19Gan, Chee Lip 21Gan, Tai Kwee 16Gao, Jian 24Garcia, Lester 15Ge, Dandong 9Ge, Garry 6Ge, Gary 4Gerets, Carine 45Gilho, Hwang 43Gobbato, Livio 4Goh, G. T. W. 13Goh, Jason 3Gongyue, Tang 46Gonzales, Emily A. 10Goo, F. T. 31Gourlay, Christopher 25Greca, Gustavo 36Gregorius, P. 37Gschwandl, Mario 30Gu, Yu 40Guan, Tan Han 17, 38Guan, Yong 40, 43Guene, Emmanuelle 9Gyenge, Oliver 20, 31Hahlweg, P. 37Hahn, R. 37Hajdarevic, Z. 36Halloran, Orla O 34Hamelink, Johan 36Hampicke, D. 37Han, Mingchuan 45Han, Seung Min 43Han, Yong 3, 46Hanna, Carlton 6, 31Hansen, Ulli 20, 31

49

Author Index


Hao, Yuan Wen 34Harel, Jean Claude 36Hartler, C. 36Hatakeyama, Keiichi 45Hattel, J. H. 20Hattel, Jesper H. 30, 44He, Sifeng 24He, Weikun 36He, Yunbo 24Heck, Howard 32Heinig, Andy 11Helfen, Lukas 9Henaff, Francois Le 36Hentschel, Oliver 37Hermsdorf, Jörg 25Herrmann, Peter 22Heylen, Nancy 7Hirao, Kiyoshi 2, 16Hirotsuru, Hideki 16Ho S. W., David, 40Ho, Cheng-Yu 39Ho, David Soon Wee 2, 44Ho, Ong Chen 17Ho, SC 27Ho, Soon Wee 3Hoang, Thanh Hai 22Hoelck, Ole 31Holsteyns, F. 7, 28Honda, Okihisa 42Hoo, Kok Inn 44Hsiao, H. Y. 3Hsiao, Hsiang-Yao 3Hsiao, Jay 18Hsiao, Yu-Jen 38Hsieh, Robert 35Hsu, Chih-Chung 11Hsu, H. S 18Hsueh, Lin En-Yi 39Hu, Xiao 21Hu, Xiaodong 20, 31Huang, Chao-Tsai 11Huang, Chien-Chih 17Huang, Lung-Shu 41Huang, Wei-Hsiang 38Huang, Y. 13Hubble, Neil 29Hubl, M. 37Hui, Chong Kim 9Hui, Tang 41Huneke, James T. 10Hung, Leo 3Hunter, Stevan 44

Hutt, David 19Huylenbroeck, S. Van 28Huylenbroeck, Stefaan Van 35Hwang, Gilho 3Hwang, How Yuan 15Hyuga, Hideki 16Ihle, Martin 31Inoue, Fumihiro 45Iwakiri, Shoji 2, 16Iwasaki, A. 7, 28Izu, Noriya 2Jaafar, Norhanani Binte 2, 43Jabbari, M. 20Jabbari, Masoud 44Jablonski, T. 37Jagadish, CV 4Jagtap, Piyush 10Jhong, Ming-Fong 39Jian, Gao 41Jiang, Don Son 3, 20, 30Jiang, James 18Jiang, Jase 18Jin, Yufeng 13, 22, 35, 40, 43Jinzhi, Liao 9Joshi, Yogendra 1Joshi, Yogendra 5Joshy, S. 20Jun, Li 24Jun, Wei 15Jung, Boo Yang 23, 28JunjieChe 24Jy, Hao 27Kai, Wu 27Kai, Yang 38Kai, Zhang 41Kalaiselvan, Ravanethran 3Kanaya, Haruichi 11, 32Kanert, Werner 29Kang, IT 14Kao, Nicholas 3, 18, 20, 30Katti, Guruprasad 14Kaur, Harvinderpal 9Kawano, Masaya 46Kee, Peter Chang Hyun 23Ken-Huang 39Kenyon, Gareth 35Keong, Loke Chee 9, 14Kermarrec, Olivier 4Kheng, Lee Teck 18Khoong, Ling Eng 16Kim, Do-Won 39Kim, Soon-Wook 7

50

Author Index


Kitada, Hideki 7Kong, Jackson 32Krivec, Thomas 30Kroehnert, Steffen 45Kuah, Eric 27Kudella, P. W. 42Kumar, Appukkutty Vinoth 14Kumar, Praveen 10Kumar, Santosh 5Kumar, Somesh 39Kumara, Kurnia 9Kurz, Florian 7Kyaw, Ko Lwin 8Lai, F. K. 23Lan, Albert 1Lang, K. -D. 37Lang, Klaus Dieter 20Lang, Klaus-Dieter 14, 22, 31, 32, 37Lau, B. L. 3Lau, Boon Long 3Lauderdale, Matt 34Law, T. K. 41Lee, Jae Wung 41Lee, Jun Su 15Lee, Kheng Chooi 29Lee, Ni Hsing 34Lee, Ricky SW 46Lee, S. W. Ricky 15Lee, Seung-lo 41Lee, Steven 35Leng, Eu Poh 36Leng, Ser Bok 18Li, Bin 41Li, Chao 39Li, Chun 25Li, H. Y. 43Li, Holden 1Li, Hong Yu 14Li, Hongfang 41Li, Jun 3, 4, 45Li, Xiangyang 3, 4Li, Xiaoyan 8Li, Y. 28, 41Li, Yi 27Li, Yushan 11Liang, Chuan Kai 2Liang, Xiaobo 8Lianto, Prayudi 40Liebens, M. 7Lim, Adeline B. Y. 27Lim, Fannon 41Lim, Sharon Pei Siang 2

Lim, Sharon Pei-Siang 27Lim, Sharon Seow Huang 46Lim, Song Kiat Jacob 21Lim, Sze Pei 34, 38Lim, Teck Guan 4Lim, Wee Kiat Crosby 9Lin, Bu 2, 23, 28Lin, Che-Shuan 40Lin, Chee Hoe 32Lin, Chun-Hung 17Lin, Huamao 41Lin, Kwang-Lung 38Lin, Ming-Shan 3, 40Lin, Mok Fock 14Lin, Vito 30Lin, Yu-Wei 38Liu, Haiyan 3, 4Liu, Huan 22, 43Liu, Kenny 18Liu, Shang-Hao 39Liu, Yan 38Liu, Yanmei 41Llana, Francis Ann 15Lo, Louis 32Lok, B. K. 23Long, Yangyang 25Low, Seow Meng 3Lu, Jianmin 11Luo, Jiangbo 41Lye, Gideon 6Ma, Shenglin 40Mackowiak, Piotr 20, 22, 31Maekawa, Katsuhiro 18Malabanan, Sotero 15Malifer, Richard Jan C. 10, 21Mancaleoni, A 29Mangaoang Jr., Tito T., 21Mansour, Mohamed 32Mathew, Varughese 45Maurer, J. -P. 37Maus, Simon 20, 31May, Chew Ly 36Meng, Maozhou 20Meng, Wei 40Mesa, Baquiran Joseph Aaron 25Mesa, Joseph Aaron 41Miao, Min 22, 43Michiel, Marco Di 9Middendorf, Andreas 37Miller, Andy 7, 35, 45Ming, Li 33Mita, Mamoru 18

51

Author Index


Mitsukura, Kazuyuki 45Miyahara, Shoichi 7Miyamoto, Ryoya 11Miyazaki, Hiroyuki 2, 16Mohahidin, M. B. 41Mohaime, B. M. 13Mohanty, S. 20Mohanty, Sankhya 30, 44Mok, Chee Wei 31Morikawa, Yasuhiro 35Morita, Hirotaka 44Morris, James E. 1Mueller, Martin 23, 37Mukhopadhyay, Biswajit 20, 22, 31Muniandy, Kesvakumar 34Murali, Sarangapani 14Murayama, Takahide 35Müller, H-H. 37Nachiappan, Vivek Chidambaram 3Nachreiner, Jens 36Nakata, Yusuke 30Nakayama, Shingo 44Nangia, Amit 17Nasirabadi, Parizad S. 30Nasirabadi, Parizad Shojaee 44Natsukawa, Masanori 45Ndip, Ivan 32Neelakandan, Sivanantham 16Ng, H. H. S. 13Ng, S. P. 31Ng, Wayne C. W. 25Ngo, H. -D. 37Ngo, Ha-Duong 20, 22, 31Nishimura, Takatoshi 25Noack, V. 37Noack, Volker 22O'Brien, Peter 15Oetzel, Christoph 3Okuno, Shota 30Otsuka, Kanji 2Pagala, Soriente Joshua 18Pan, George 18Pan, Po-Chih 39Pan, Y. J. 8Paulasto-Kröckel, Mervi 29Peng, Ding Zhi 23, 28Peng, Lan 7Peng, Ng Lay 17Petit, Luc 28Phua, Jian Rong Eric 21Pi, Yudan 35Piau, Chong Kok 43

Pinto, Raquel 45Piotr, Kropelnicki 2Pohl, O. 37Pohl, Olaf 22Priewasser, Karl Heinz 28Pu, Suan Hui 31Pufall, R. 42Qi, Quan 6, 31Qi, Tao 30Qiang, Patrick Lo Guo 39Qiang, Yan Guo 18Qiu, Qian 24Rabeek, Sarbudeen Mohamed 40Radchenko, Ihor 42, 43Ramamoorthy, Praveen Kumar 38Rao, Vempati Srinivasa 3, 27, 44Rebibis, Kenneth June 7, 45Reichardt, Maik 7Reinert, Wolfgang 28Rencz, Marta 46Reuther, G. M. 42Rezvani, Alireza 27Ridhuan, Song Wenjian M. 43Ross, Glenn 29Rotaru, Mihai D. 31Ruifen, Zhang 41Rzepka, S. 42Sakai, Taiji 10Sakuishi, Toshiyuki 35Sakuyama, Seiki 7, 10Salam, B. 15, 41Salerno, Paul 36Sarkany, Zoltan 46Sato, Michihiro 25Schick, E. 37Schmadlak, Ilko 34Schmidt, Michael 37Schmitt, Wolfgang 36Schneider, Friedrich 25Schrank, F. 36Schrems, M. 36Schröder, Markus 28Schröder, Saskia 28Schwartzinger, T. 37See, Guan Huei 40Seguido, Rammil A. 21Sek, S. A. 40Sek, Soon Ann 3Sekhar, Vasarla Nagendra 7Selvanayagam, Cheryl 42Senthilkumar, B. 14Seok, Tae Joon 15

52

Author Index


Shan, X. C. 13, 15, 41Sharma, Rohit 39Shaw, Mark 4Sheng, Teng Di 42Shi, Hong 17Shibata, Kyouhei 32Shih, Meng-Kai 6Shih, Te-Ping 38Shimada, Kazuhiko 2Shin, E. 37Shinki, Yuharu 32Siegert, J. 36Simanjorang, Rejeki 33Slabbekoorn, J. 7Slabbekoorn, John 35Sleeckx, Erik 7Song, Meijiang 45Song, Wenjian 42Sonoda, Hisaya 18Srinivas, Damo 19Staliulionis, Zygimantas 30Staliulionis, . 20Stiers, K. 7Struyf, Herbert 7Stucchi, Michele 35Su, Fei 43Su, Mei-Chen 38Suhard, S. 7, 28Sun, Peter 34Sun, Tommy 18Sun, Xin 22, 43Sun, Yunna 41Sunappan, Vasudivan 37Sureshkumar, Vinobaji 9SuriadiBudiman, Arief 43Sweatman, Keith 25Tadaki, Shinji 7Tae, Veera Sae 16Talledo, Jefferson S. 21Tamura, N. 42Tamura, Nobumichi 43Tan, C. E. 8Tan, Chuan Seng 19, 29Tan, Eric M. M. 43Tang, Gongyue 40Tang, Hui 24Tang, Leijun 2Tashiro, Hiroko 7Tay, Andrew A. O. 42, 43Tay, Swee Teck 10Teck, Siong Chin 3, 36Teng, Hui Lee 39

Teo, J. W. Ronnie 41Theint, Ei Phyu Phyu 14Thierauf, Jean 37Tian, Tian 9Ting, Chun-Yen 39Tippabhotla, Sasi Kumar 42, 43Tobback, Bert 35Tomasi, M. De 29Tremolada, Matteo 4Trewhella, Jean 4Tsai, Johan 34Tu, King-Ning 9Twiefel, Jens 25Uehling, Trent 34Uemura, Taiki 10Vaion, R. Enrici 29Vandeweyer, Tom 35Vodiunig, Robert 37Voelkel, Holger 37Vokmer, N. 20Vuorinen, Vesa 29Wagenleitner, Thomas 7Wai, Chan Kuok 17Wai, Leong Ching 3Walter, Hans 31, 37Wan, Lo Miew 9Wang, Chen-Chao 39Wang, Chunmei 35Wang, H. T. 31Wang, Hong 41Wang, Ji-Ye 17Wang, Jiaqi 15Wang, Jun 11Wang, Miao 45Wang, Sonder 6Wang, Teng 45Wang, Wei 35Wang, Xiangyu 35Wang, Yan 41Wee, Ho Soon 40Weerasekera, Roshan 14Wei, J. 41Wei, Sophia 41Wei, Tok Chee 36Weiland, T. 37Weon, Lim Yee 9Wickramanayaka, Sunil 3, 7, 40Wing, Leong Yew 43Wolf, Ingrid De 1Wong, Kim Sing 28Wong, Laiyin 2Woo, Jasmine 2

53

Author Index


Woratz, Michael 22Wu, Fengshun 27Wu, Ming C. 15Wu, Sung-Mao 3, 40, 41Wurz, Marc 25Wynder, Rachel 44Xi, Zhang 9Xian, Tee Swee 14Xiang, Xiaobin 24Xiaojun, Yan 19Xie, Ling 7Xin, Chen 41Xin, Yong Ling 36Xu, Cheng 41Xu, Feng 9Xu, Huan 9Xu, Qiu 41Xu, Sean 3, 4Xue, Ming 9Xuesong, Xu 24Yadong, Wei 24Yamamoto, K. 3Yamasaki, Kazuhiko 18Yan, Beiyue 45Yan, Ruey Jun 31Yan, Tan Juo 36Yang, Jung Boo 40Yao, Jinyuan 41Yao, Peng 8Yaojian, Lin 28Yap, Daniel 28Yauw, Oranna 27Yee, Loh Wan 36Yen, Freedman 3Yeo, Alfred 17, 38Yeo, Kok Siong 16Yeung, Betty 34Yew, Yee Huan 6, 39Ying, Lee Chai 22Yinhui, Ao 41

Yong, Khang Choong 32Yongshan, Hu 41Yoon, Seung Wook 5, 28You, Andrew 18Youssef, Abdalla 37Yu, Bo 8Yu, Cheng Fu 34Yu, Jun 40Yu, Mingbin 35, 40Yu, Qiang 30, 42, 44Yu, Zhang 41Yun, Chen 41Yunbo, He 41Yusoff, Hilmi B Mohamed 3Zabberoni, P 29Zapanta, Amor 40Zeng, Kejun 17Zeng, Qinghua 13, 40, 43Zhanbin, Song 24Zhang, H. 13Zhang, Hong Wen 34Zhang, Lidong 45Zhang, Songbai 14Zhang, Xueren 4Zhang, Yucheng 31Zhang, Yue 16Zhangxi 36Zhao, Bo 16Zhao, Xiaolin 41Zhaohui, Chen 28Zhi, Ding Mian 2, 23, 28Zhijun, Yang 41Zhong, Z. W. 13, 41Zhou, Suyao 22Zhu, Tammy 18Zhu, Wenhui 4Ziesche, Steffen 31Zinn, Alfred 5Zoschke, Kai 14Zou, Huayong 15

54

Author Index


_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

55

Notes


_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

_________________________________________________________________________________________________

56

Notes


Documents

Foreword - · PDF fileI-2 Foreword I-1 Introduction to EPTC I-9 Organizing Committee I-10 Technical Committees I-12 Keynote Address I-16 Panel Session I-21 Professional