For Final Year Students Manual made by Prof. N. V. Bhosalecoeosmanabad.com/etc/manual/BE VLSI LAB MANUALS.pdf · 2. Half Adder Using Dataflow Style 2a. Half Adder Using Behavioral

Tpct’s College of Engineering, Osmanabad

Laboratory Manual

VLSI DESIGN

For

Final Year Students

Manual made by

Prof. N. V. Bhosale

Author COE, Osmanabad

TPCT’s

College of Engineering

Solapur Road, Osmanabad

Department of Electronics &Telecommunication

Vision of the Department:

To be recognized by the society at large as an excellent department offering quality higher education in the Electronics & Telecommunication Engineering field with research focus catering to the needs of the public and being in tune with the advancing technological revolution.

Mission of the Department:

To achieve the vision the department will

Establish a unique learning environment to enable the student’s face the

challenges of the Electronics & Telecommunication Engineering

field.

Promote the establishment of centers of excellence in technology

areas to nurture the spirit of innovation and creativity among the

faculty & students.

Provide ethical & value based education by promoting activities

addressing the needs of the society.

Enable the students to develop skill to solve complete

technological problems of current times and also to provide a

framework for promoting collaborative and multidisciplinary

activities.

Tpct’s College Of Engineering, Osmanabad

Technical Document

This technical document is a series of Laboratory manuals of Electronics &

Telecommunication and is a certified document of College Of Engineering, Osmanabad

The care has been taken to make the document error free but still if any error is found kindly bring it to the notice of subject teacher and HOD.

Recommended by,

HOD

Approved by,

Principal

Copies:

• Departmental Library • Laboratory • HOD • Principal

VLSI Lab Manuals BE (ETC)

TPCT’S COLLEGE OF ENGINEERING, OSMANABAD Page 4

FOREWORD

It is my great pleasure to present this laboratory manual for Final year Engineering students for the subject of VLSI Design keeping in view the vast coverage required for visualization of concepts of VLSI Design

As a student, many of you may be wondering with some of the questions in your mind regarding the subject and exactly what has been tried is to answer through this manual.

Faculty members are also advised that covering these aspects in initial stage itself, will greatly relived them in future as much of the load will be taken care by the enthusiasm energies of the students once they are conceptually clear.

H.O.D.



LABORATORY MANUAL CONTENTS

This manual is intended for the Final year students of Engineering in the subject of VLSI Design. This manual typically contains Practical/Lab Sessions related to Electronics covering various aspects related to the subject to enhance understanding.

Students are advised to thoroughly go through this manual rather than only topics mentioned in the syllabus, as practical aspects are the key to understanding conceptual visualization of theoretical aspects covered in the books.

Good Luck for your Enjoyable Laboratory Sessions.

Prof. N. V. Bhosale



ELECTRONIS SYSTEM DESIGN

SUBJECT INDEX:

1. Dos and Don’ts in Laboratory.

2. Lab Exercises

1.Design Of Logic Gates

2. Half Adder Using Dataflow Style

2a. Half Adder Using Behavioral Style

2b. Half Adder Using Structural Style

3.Design of Full Adder

4. Design of 2:4 Decoders

5.Design of 8:1 Multiplexer

6. Design of Binary to Gray Code Converter

7. Design 4 Bit Comparator

8. Design of D Flip-Flop

9. Design of T Flip Flop

3. Quiz on the subject

4. Conduction of Viva-Voce Examinations

5. Evaluation and marking system

VLSI Lab Manuals BE(ETC)

COLLEGE OF ENGINEERING, OSMANABAD Page 7

1.Do’s and Don’ts in Laboratory:

1. Do not handle any equipment before reading the instructions/Instruction manuals

2. Observe type of sockets of equipment power to avoid mechanical damage

3. Do not forcefully place connectors to avoid the damage

4. Strictly observe the instructions given by the teacher/Lab Instructor

Instruction for Laboratory Teachers:

1. Submission related to whatever lab work has been completed should be done during the next lab session.

2. The promptness of submission should be encouraged by way of marking and evaluation patterns that will benefit the sincere students.



EXPERIMENT NO 1

----------------------------------------------------------------------------------

-- Project Name:DESIGN OF LOGIC GATES

-- Target Devices: SPARTAN2

-- Tool versions: ISE10.1

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EXPT1 is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

NOT1 : out STD_LOGIC;

AND1 : out STD_LOGIC;

OR1 : out STD_LOGIC;

NAND1 : out STD_LOGIC;

NOR1 : out STD_LOGIC;

XOR1 : out STD_LOGIC;

XNOR1 : out STD_LOGIC);

end EXPT1;

architecture Behavioral of EXPT1 is

begin

NOT1 <= NOT A;

AND1 <= A AND B;

OR1 <= A OR B;



NAND1 <= A NAND B;

NOR1 <= A NOR B;

XOR1 <= A XOR B;

XNOR1 <= A XNOR B;

end Behavioral;

RESULTS:

A] IDEAL RESULT:

TRUTH TABLE:

SR. NO A B NOT1 ANDI OR1 NAND1 NOR1 XOR1 XNOR1

1 0 0 1 0 0 1 1 0 1

2 0 1 1 0 1 1 0 1 0

3 1 0 0 0 1 1 0 1 0

4 1 1 0 1 1 0 0 0 1



B] SIMULATION RESULT:

1) TEST BENCH WAVEFORM

2) RTL SCHEMATIC :



EXPERIMENT NO 2

----------------------------------------------------------------------------------

-- Project Name: HALF ADDER USING DATAFLOW STYLE


-- Tool versions: ISE 10.1

----------------------------------------------------------------------------------

library IEEE;




entity EXPT2 is


B : in STD_LOGIC;

SUM : out STD_LOGIC;

CARRY : out STD_LOGIC);

end EXPT2;


begin

SUM <= A XOR B;

CARRY <= A AND B;

end Behavioral;



RESULTS:

A] IDEAL RESULT:

TRUTH TABLE:

Sr. No A B Sum Carry

1 0 0 0 0

2 0 1 1 0

3 1 0 1 0

4 1 1 0 1




EXPERIMENT NO 2A

---------------------------------------------------------------------------------

-- Project Name: HALF ADDER USING BEHAVIORAL STYLE

-- Target Devices: SPARTAN 2


---------------------------------------------------------------------------------

library IEEE;




entity EXP2A is


B : in STD_LOGIC;

S : out STD_LOGIC;

C : out STD_LOGIC);

end EXP2A;

architecture Behavioral of EXP2A is

begin

process (A,B)

begin

if (A= '0')then

if (B = '0')then

s <= '0';

c <= '0';

else

s <= '1';



c <= '0';

end if;

else

if (B = '0')then

s <= '1';

c <= '0';

else

s <= '1';

c <= '1';

end if;

end if;

end process;

end Behavioral;



RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Sr. No A B S C

1 0 0 0 0

2 0 1 1 0

3 1 0 1 0

4 1 1 0 1




EXPERIMENTS NO 2B

----------------------------------------------------------------------------------

-- Project Name: HALF ADDER USING STRUCTURAL STYLE



----------------------------------------------------------------------------------

library IEEE;




entity EXPT2B is

Port ( X : in STD_LOGIC;

Y : in STD_LOGIC;

Sout : out STD_LOGIC;

Cout : out STD_LOGIC);

end EXPT2B;

architecture Behavioral of EXPT2B is

component PXOR is

Port ( P: in STD_LOGIC;

Q : in STD_LOGIC;

R : out STD_LOGIC);

end component;

component PAND is

Port ( A: in STD_LOGIC;

B : in STD_LOGIC;

C : out STD_LOGIC);



end component;

begin

X1: PXOR port map(X, Y, Sout);

A1: PAND port map(X, Y, Cout);

end Behavioral;

RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Sr. No x y Sout Cout

1 0 0 0 0

2 0 1 1 0

3 1 0 1 0

4 1 1 0 1




EXPERIMENT NO 3

----------------------------------------------------------------------------------

-- Project Name: DESIGN OF FULL ADDER



---------------------------------------------------------------------------------

library IEEE;




entity EXPT3 is


B : in STD_LOGIC;

Cin : in STD_LOGIC;

SUM : out STD_LOGIC;

Cout : out STD_LOGIC);

end EXPT3;


signal X: STD_LOGIC;

begin

X <= (A XOR B)AND Cin;

SUM <= A XOR B XOR Cin;

Cout <= X OR (A AND B);

end Behavioral;



RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Sr. No a b Cin Sum Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1




EXPERIMRNT NO 4

----------------------------------------------------------------------------------

-- Project Name: DESIGN OF 2:4 DECODER


-- Tool versions: XILINX ISE 10.1

----------------------------------------------------------------------------------

library IEEE;




entity EXPT4 is

Port ( En : in STD_LOGIC;

I : in STD_LOGIC_VECTOR (01 downto 0);

Y : out STD_LOGIC_VECTOR (03 downto 0));

end EXPT4;


begin

process (En,I)

begin

if En = '0' then Y<= "0000";

else

case I is

when "00" => Y <= "1000";

when "01" => Y <= "0100";

when "10" => Y <= "0010";

when others => Y <= "0001";



end case;

end if;

end process;

end Behavioral;

RESULTS:

A] IDEAL RESULT

TRUTH TABLE

En I(0) I(1) Y(3) Y(2) Y(1) Y(0)

0 x x 0 0 0 0

1 0 0 1 0 0 1

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1




EXPERIMENT NO 5

----------------------------------------------------------------------------------

-- Project Name: DESIGN OF 8:1 MULTIPLEXER



----------------------------------------------------------------------------------

library IEEE;




entity EXPT6 is

Port ( En : in STD_LOGIC;

S : in STD_LOGIC_VECTOR (02 downto 00);

I : in STD_LOGIC_VECTOR (07 downto 00);

Y : out STD_LOGIC);

end EXPT6;


begin

process (En,S,I)

begin

if En = '0' then Y<= '0';

else

case s is

when "000" => Y <= I(00);

when "001" => Y <= I(01);

when "010" => Y <= I(02);

when "011" => Y <= I(03);

when "100" => Y <= I(04);

when "101" => Y <= I(05);

when "110" => Y <= I(06);

when others => Y <=I(07);



end case;

end if;

end process;

end Behavioral;

RESULTS:

A] IDEAL RESULT

TRUTH TABLE

En S(2) S(1) S(0) I(7) I(6) I(5) I(4) I(3) I(2) I(1) I(0) Y(0)

0 X X X X X X X X X X X 0

1 0 0 0 0 0 0 1 0 0 0 1 1

1 0 0 1 0 0 1 0 0 1 0 0 0

1 0 1 0 0 0 1 1 0 1 0 0 1

1 0 1 1 1 0 0 0 0 0 1 1 0

1 1 0 0 1 1 0 1 1 1 1 1 0

1 1 0 1 0 0 1 0 0 1 0 1 1

1 1 1 0 0 1 1 0 0 0 0 0 1

1 1 1 1 1 1 0 0 1 1 1 0 1

B] SIMULATION RESULT :



EXPERIMENT NO 6

----------------------------------------------------------------------------------

-- Project Name: DESIGN OF BINARY TO GRAY CODE CONVERTER



----------------------------------------------------------------------------------

library IEEE;




entity EXPT5 is

Port ( B : in STD_LOGIC_VECTOR (03 downto 00);

G : out STD_LOGIC_VECTOR (03 downto 00));

end EXPT5;


begin

G(3)<= B(3);

G(2)<= B(3)XOR B(2);

G(1)<= B(2)XOR B(1);

G(0)<= B(1)XOR B(0);

end Behavioral;



RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Sr. No. B(3) B(2) B(1) B(0) G(3) G(2) G(1) G(0) 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 1 3 0 0 1 1 0 0 1 0 4 0 1 0 0 0 0 1 1 5 0 1 0 1 0 1 1 1 6 0 1 1 0 0 1 0 1 7 0 1 1 1 0 1 0 0 8 1 0 0 0 1 1 0 0 9 1 0 0 1 1 1 0 1 10 1 0 1 0 1 1 1 1 11 1 0 1 1 1 1 1 0 12 1 1 0 0 1 0 1 0 13 1 1 0 1 1 0 1 1 14 1 1 1 0 1 0 0 1 15 1 1 1 1 1 0 0 0




EXPERIMENT NO 7

----------------------------------------------------------------------------------

-- Project Name: DESIGN 4 BIT COMPARATOR



----------------------------------------------------------------------------------

library IEEE;




entity EXPT7 is

Port ( A : in STD_LOGIC_VECTOR (03 downto 00);

B : in STD_LOGIC_VECTOR (03 downto 00);

Equal : out STD_LOGIC;

Grater : out STD_LOGIC;

Smaller : out STD_LOGIC);

end EXPT7;


begin

process (a,b) is

begin

if (A = B )then

Equal <= '1';

Grater <= '0';

Smaller <= '0';

else if (A < B)then



Equal <= '0';

Grater <= '0';

Smaller <= '1';

else

Equal <= '0';

Grater <= '1';

Smaller <= '0';

end if;

end if;

end process;

end Behavioral;

RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Sr. No.

A(3) A(2) A(1) A(0) B(3) B(2) B(1) B(0) Equql (A=B)

Grater (A>B)

Smaller (A<B)

0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 2 0 0 1 0 0 0 0 0 0 1 0 3 0 0 1 1 0 0 0 1 0 1 0 4 0 0 0 1 0 1 0 0 0 0 1 5 0 0 1 1 0 1 0 1 0 0 1 6 0 1 1 0 0 1 1 0 1 0 0 7 1 1 1 1 0 1 1 1 0 1 0 8 0 1 0 0 1 0 0 0 0 0 1 9 1 0 0 1 0 1 1 1 0 1 0 10 1 1 1 0 1 0 1 0 0 1 0 11 1 0 1 1 1 0 1 1 1 0 0 12 1 1 0 0 1 1 0 0 0 1 0 13 1 1 0 1 1 1 0 1 0 1 0 14 1 0 1 0 1 1 1 0 0 0 1 15 0 1 1 1 1 1 1 1 0 0 1



B]SIMULATION RESULT:



EXPERIMENT NO 8

---------------------------------------------------------------------------------

-- Project Name: DESIGN OF D FLIP-FLOP



-----------------------------------------------------------------------------------

library IEEE;




entity EXPT8 is

Port ( Clk : in STD_LOGIC;

Rst : in STD_LOGIC;

D : in STD_LOGIC;

Q : out STD_LOGIC);

end EXPT8;


begin

Dff: process(D,Clk,Rst)is

begin

if(Rst = '1')then

Q <= '0';

elsif(rising_edge(clk))then

Q <= D;

end if;

end process dff;

end Behavioral;



RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Clk Rst D Q

0 X X X

1 1 X 0

1 0 0 0

1 0 1 1




EXPERIMENT NO 9

----------------------------------------------------------------------------------

-- Project Name: DESIGN OF T FLIP FLOP



----------------------------------------------------------------------------------

library IEEE;




entity EXPT9 is

Port ( T : in STD_LOGIC;

Clk : in STD_LOGIC;

reset : in STD_LOGIC;

Tout : out STD_LOGIC);

end EXPT9;


begin

tff: process(T,Clk,reset)is

variable m:STD_LOGIC:= '0';

begin

if (reset = '1')then

m := '0';

elsif(rising_edge(clk))then

if (t = '1')then

m:= not m;



end if;

end if;

Tout<= m;

end process tff;

end Behavioral;

RESULTS:

A] IDEAL RESULT

TRUTH TABLE

Clk Rst T Q

0 X X X

1 1 X 0

1 0 0 Q

1 0 1 QN


Documents

For Final Year Students Manual made by Prof. N. V. Bhosalecoeosmanabad.com/etc/manual/BE VLSI LAB MANUALS.pdf · 2. Half Adder Using Dataflow Style 2a. Half Adder Using Behavioral