Half adder layout design

[HALF ADDER DESIGN] April 8, 2013

ELECTRICAL ENGINEERING DEPARTMENT

EE603-CMOS INTEGRATED CIRCUIT DESIGN

LAB REPORT 6DESIGNING HALF ADDER CIRCUIT

No Registration No. Name

1. 18DTK10F1036 CHONG WEI TING

2. 18DTK10F1034 ADLAN BIN ABDULLAH

CLASS : DTK 6B

LECTURER : EN. MUHAMAD REDUAN BIN ABU BAKAR

DATE SUBMITTED : 8th ARPIL 2013(Date submitted is one week after date lab)

DECEMBER 2012 SESSION Page 1

TUANKU SYED SIRAJUDDIN

POLYTECHNIC

MARKS

Lab Work :

Lab Report:

Total :


LAB 6 : DESIGNING HALF ADDER CIRCUIT

Aim: Designing half adder circuit using L-edit software.

Objective:After students had done this laboratory, then students should be able to:

1) Introduce schematic circuit, logic symbols and truth table of half adder.

2) Design half adder circuit using L-edit..

Apparatus: PC-set & L-edit student V 7.12 software.

Half adder is a combinational arithmetic circuit that adds two numbers and

produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then

sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B.

From this it is clear that a half adder circuit can be easily constructed using one X-OR

gate and one AND gate. Half adder is the simplest of all adder circuit, but it has a major

disadvantage. The half adder can add only two input bits (A and B) and has nothing to

do with the carry if there is any in the input. So if the input to a half adder have a carry,

then it will be neglected it and adds only the A and B bits. That means the binary

addition process is not complete and that’s why it is called a half adder. The truth table,

schematic representation and XOR//AND realization of a half adder are shown in the

figure below.


INTRODUCTION


Schematic symbol and truth table of exclusive OR (XOR) gate.

(5 mark)

Explanation of 1-bit half-adder circuit operation. (10mark)

The basic 1-bit half-adder circuits. The sum bit is calculated with XOR gates,

while the AND gates are used to check whether two (or more) inputs are 1, which

implies that the carry out bit must be set. The half adder adds two single binary

digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an

overflow into the next digit of a multi-digit addition. The value of the sum is 2C + S. The

simplest half-adder design, pictured on the right, incorporates an XOR gate for S and

an AND gate for C. With the addition of an OR gate to combine their carry outputs, two

half adders can be combined to make a full adder. These are the least possible single-

bit combinations. But the result for 1+1 is 10. Though this problem can be solved with

the help of an EXOR Gate, if you do care about the output, the sum result must be re-

written as a 2-bit output. Here the output ‘1’of ‘10’ becomes the carry-out. The result is

shown in a truth-table below. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.



From the equation it is clear that this 1-bit adder can be easily implemented with the

help of EXOR Gate for the output ‘SUM’ and an AND Gate for the carry.

1. DESIGN Individual xor GATES a) Created a new file in L-edit, and saved the file as Half_adder_chong.tdb.

b) Go to cell and then rename cell0 as XOR_gate.


LAB WORK ACTIVITY


c) In cell ‘XOR gate’, drawn the layout of XOR gate that according to XOR gate stick diagram in Appendix and then label its.

d) Selected ToolDRC, to ensure that the design does not violating any design

rules.



2. DESIGN Individual AND GATES a) Open a new cell and renamed it as ‘AND gate’.

b) In cell ‘AND gate’, drawn the layout of 2-input AND gate that according to AND

gate stick diagram in Appendix and label it.

c) Selected ToolDRC, to ensure that the design does not violating any design

rules.



3. DESIGN half adder. a) Open a new cell and renamed it as ‘half adder’.

b) Go to cell, and then Instanced the XOR gate layout and AND gate layout in this

new cell and made connection of these two layouts.



c) Selected ToolDRC, to ensure that the design does not violating any design

rules.


RESULT OF HALF ADDER


Area: 7.75µm X 21.25µm=164.688μm2(denote 1lamda=0.125micron)


CONCLUSION


This lab work will consider the complete half adder layout that based combination

of XOR gate and AND is presented, which after completing the lab phase, we will be

able to design an individual 2-input logic gates which is AND gate and XOR gate based

on given specification design rule. We had to combine these two gate together to form

the half adder layout.

Initially the design of XOR and AND layout, we able to recognize schematic circuit,

logic symbols and truth table of XOR gates and AND gate. In half adder lab, we can had

to design circuits that are capable of performing simple addition with the help of logic

gates.

APPENDIX


VDD

667 71

GND

F=A.B

A BSS

D D S

VDD

SD SD

2-input NAND gate Inverter

input

VDD

GND


Exclusive-OR (XOR) Stick Diagram

2-input AND gate Stick Diagram


F = A.B