FLIP-FLOP IMPLEMENTATION

1. BASIC RS FLIP –FLOP (Asynchronous Sequential Logic)

The above flip flop is used in asynchronous sequential circuits. The outputs of any combinational control logic, that drives the R and S inputs, must be glitch free. (eg. Lift Sets must be used to cover adjacent loops in the Karnaugh Maps)

2. CLOCKED FLIP-FLOPS (Synchronous Seqential.Logic)These circuits use a clock input in such a manner that there is no continuous path through the flip-flops at any time. The flip-flop inputs are disabled when their outputs change so that any glitches fed back into the inputs don’t have any effect.

2.1 RS Flip Flop with Enable Input An enable line can be used to turn off the path through the flip-flops when the enable is low, as indicated below.

Q

QR

S

Set = S or Preset, Reset = R or Clear

(b) RS with Preset and Clear Inputs

Q

QR

S

Preset

Clear(a) RS Flip-flop

S

R

Q

Q

Clear

Preset

R & S Inputs to Flip-Flops (must be glitch-free)

Asynchronous Sequential logic Circuit using Non Clocked Flip-Flops

Combinational Logic Inputs

Flip-Flop Outputs(State Variables)

This path is continually open, so logic must be glitch free

RS Flip-Flops( non-clocked)

OutputsInputs

EnableQ

R

S

S2 = S and EnableR2 = R and Enable

S2

R2

Q

Q

Clear

Preset Preset

S

R

Q

Q

Clear

Enable

RS with Preset, Clear and Enable Inputs

path no path

In this case the path through the 2 Nand gates is only opened then the enable line is at logic 1. However, there would still be a continuous unbroken loop around the circuit when the enable was true. Thus any combinational logic producing the R and S inputs would still have to be glitch-free as indicated below.

2.2 RS Master-Slave Flip Flop with Clock Input One way of ensuring that there is never a continuous path through the flip-flop is to use 2 flip-flops in series. The input flip-flop is the Master and the output flip-flop is the Slave as indicated below.

Note the asynchronous Preset and Clear inputs are inputs to the Slave flip-flop, and override the effect of the Master. Thus when a Clear is applied to the Slave, the RS inputs (and the clock) have no effect on the output Q’s, since the Slave is held in the OFF mode via its Clear input.

Glitches now have no effect on the Q outputs, as indicated below

RS Flip-Flops (with enable input)

R & S Inputs to Flip-Flops (must be glitch-free)

Sequential logic Circuit using Flip-Flops with Enable

Combinational LogicInputs Outputs

Flip-Flop Outputs(State Variables) This path is open when enable is true,

so logic must still be glitch free

Enable Open ClosedEnable

R

S

MASTER

Sm

Rm

Qm

Qm

Open Master(R,S => Master)

Preset

S

R

Q

Q

Clear

Clock

Clocked Master-Slave Flip Flop

Qs changes at this point when Master => Slave(Any glitches at R,S inputs are ignored by the Master)

Clock path

SLAVE

Ss

Rs

Qs

Qs

Clock

Preset

Clear

Open Slave(Master => Slave)

Open Slave(Transfer M to S)

Open Master(set up Master)

2.3 RS Flip Flop with Edge Triggered Clock Input Another way of ensuring that there is never a continuous path through the flip-flop is to use a single flip flop and only open its input circuit for a very short time (eg. 10nSecs). Thus by the time its outputs change state (and possibly produce glitches) the input gates are closed, so the glitches have no effect.

Note the asynchronous Preset and Clear inputs again override the effect of any RS inputs and clock.

Clocked RS Flip-Flops

Inputs to Flip-Flops (glitches OK)

Sequential logic Circuit using Clocked Flip-Flops

Combinational LogicInputs Outputs

Flip-Flop Outputs(State Variables) This path is never fully open

(so all glitches are neglected by FF’s)

ClockMastersSlavesM S M

Preset

S

R

Q

Q

Clear

Clock

Q’s changes at this point when a short delay after Clock goes 0 -> 1(Any glitches at R,S inputs are ignored by the flip-flop)

Clock path

BasicFlip-Flop

S

R

Qs

Qs

Clock

Preset

Clear

S

R

Clock

Edge Detector

Clocked, Edge Triggered Flip-Flop

Enable

Enablelock pathQ Output

(example)

Clock path

3. CLOCKED FLIP-FLOP TYPES 3.1 D-TypeA D-type flip flop is a clocked RS flip-flop (either edge triggered or Master–Slave) with an input inverter as shown below.

3.1 JK-TypeA JK flip flop is a clocked RS flip-flop (either edge triggered or Master–Slave) with input gating and additional feedback as indicated below.

Note: The two AND gates are usually incorporated into the input gating of the basic clocked RS flip-flop

3.1 T-TypeA T-type flip flop is essentially a clocked JK flip-flop (either edge triggered or Master–Slave) with both the J and K inputs tied together to form the T input, as indicated below.

Preset

D Q

Q

Clear

Clock

D

Preset

S

R

Q

Q

Clear

Clock

Preset

J Q

Q

Clear

Clock

Preset

S

R

Q

Q

Clear

ClockJ

K K

Preset

T Q

Q

Clear

Clock

T

Preset

J

K

Q

Q

Clear

Clock