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Jhih-Rong Gao and David Z. Pan
ECE Dept. Univ. of Texas at Austin
Flexible Self-aligned Double Patterning Aware Detailed Routing with Prescribed Layout Planning
Supported in part by NSF, Oracle, and NSFC
Outline
Introduction Motivation SADP-Compliant Routing Guidelines SADP-Aware Detailed Routing Experimental results Conclusion
2
Introduction
193nm lithography reaches its limit for sub-22nm Next generation lithography not yet ready
› EUV, E-beam, … DPL/MPL is necessary to meet current demand
31980 1990 2000 2010 2020
10
1
0.1
um
[Courtesy Intel]
X
SADP Advantage
Conventional LELE DPL: 2 exposures
SADP: 1 exposure + automatic aligned› Better overlay control
Hard mask 2Hard mask 2Hard mask 1
1st exposure etch 2nd exposure etch
Overlay error occurs!
Trim mask
mandrel maskexposure
Spacer deposition Substratematerial filling
trimming4
SADP Challenges
No stitch allowed to split conflicting patterns
Patterns interaction affects printing image quality Layout decomposition more complicated for 2D
patternsMight be too late to apply SADP after routing is done
5
Previous Works
LELE DPL-friendly routing› Main optimization goal: stitch minimization to reduce
overlay error» M. Cho et al [ICCAD 2008], K. Yuan et al [DAC 2009], X. Gao
et al [DATE 2010], etc
SADP› Most works focus on layout decomposition
» H. Zhang et al DAC 2011, Y. Ban et al DAC 2011, etc
› SADP-aware routing» M. Mirsaeedi et al SPIE 2011» Improve pattern quality by increasing spacer alignment» Lack of solution for conflicts
6
Main Contribution
Consider SADP compliancy in detailed routing stage1. Perform simultaneous routing and layout
decomposition2. Propose SADP-compliant routing guidelines to
prevent negative pattern interaction3. Perform multi-layer routing to prevent conflicts by
proper layer assignment
7
Preliminaries
Mandrel pattern: directly defined by mandrel mask Trim pattern: indirectly reserved by trim mask
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Target layout Mandrel mask Spacer deposition Filling & trimming
Mandrel pattern Trim pattern
Assist
Outline
Introduction Motivation SADP-Compliant Routing Guidelines SADP-Aware Detailed Routing Experimental results Conclusion
9
SADP-Compliant Routing Guidelines
When a routing path p is to be assigned to eithermandrel or trim mask1. Prefer mandrel mask when assigning p to mandrel
and trim are both conflict-free2. Seek to aligned to more spacer when p is assigned to
trim mask3. Encourage mandrel pattern and trim pattern to be
separated by at least “forbidden spacing”
10
SADP-Compliant Routing Guideline 1
Prefer mandrel (1st mask lithography)› Printability degrades for trim mask (2nd mask lithography) due to
the topography generated by 1st lithography on the wafer› Printability for mandrel pattern is more guaranteed
11
Curtesy [K. Lucas et al, JM3 2009]
1st litho pattern
2nd litho pattern
SADP-Compliant Routing Guidelines
When a routing path p is to be assigned to eithermandrel or trim mask1. Prefer mandrel mask when assigning p to mandrel
and trim are both conflict-free2. Seek to aligned to more spacer when p is assigned to
trim mask3. Encourage mandrel pattern and trim pattern to be
separated by at least “forbidden spacing”
12
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 1: trim pattern not aligned to spacer
13
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Final pattern
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 1: trim pattern not aligned to spacer
14
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Expected pattern
Overlay error!
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 1: trim pattern not aligned to spacer
15
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Expected pattern
Overlay error!
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 2: 1 side of trim pattern aligned to spacer
16
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Final patternFinal pattern
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 2: 1 side of trim pattern aligned to spacer
17
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Final patternFinal pattern
Overlay error!
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 2: 1 side of trim pattern aligned to spacer
18
WaferWafer
Etch layer
Resist
Trim mask
spac
er
FinalFinal
Overlay error!
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 3: both sides of trim aligned to spacer
19
WaferWafer
Etch layer
Resist
Trim mask
spac
er
FinalFinal
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 3: both sides of trim aligned to spacer
20
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Overlay error!
FinalFinal
SADP-Compliant Routing Guideline 2
Trim pattern seek to aligned to more spacer Case 3: both sides of trim aligned to spacer
21
WaferWafer
Etch layer
Resist
Trim mask
spac
er
Overlay error!
FinalFinal
spacer
Better overlay controlwhen more patternedge is protected byspacer
SADP-Compliant Routing Guidelines
When a routing path p is to be assigned to eithermandrel or trim mask1. Prefer mandrel mask when assigning p to mandrel
and trim are both conflict-free2. Seek to aligned to more spacer when p is assigned to
trim mask3. Encourage mandrel pattern and trim pattern to be
separated by at least “forbidden spacing”
22
SADP-Compliant Routing Guideline 3
Separate mandrel pattern and trim pattern by at leastforbidden spacing
› Trim pattern image interfered by close mandrel pattern› Forbidden spacing: recommended spacing for affordable trim
pattern image degradation
M
M
M
MT
Curtesy [M. Mirasaeedi et al, SPIE 2011]
Target layout
Printed image Trim imagedegrades
23
T
Outline
Introduction Motivation SADP-Compliant Routing Guidelines SADP-Aware Detailed Routing Experimental results Conclusion
24
SADP-Aware Detailed Routing Correct by construction
› Routing and layout decomposition result is done simultaneously› Objective
» Conflict-free DPL mask assignment» Low wirelength» Good printed image
25
Net Ordering
Unrouted Nets
3‐D Path Finding
Routing + LDResults
SADP‐AwareRouting Guidelines
Multi‐Layer Routing forConflict PreventionExploring Solution
by Dynamic Programming
Pattern Quality Affected by Routing Order
Good ordering encourages trim pattern to align to more spacer
› Trade-off with wirelength
26
Spacer
1 321 23
Aligned to more spacer
Route neighboring net togetherOrdered by net bbox size
Neighborhood-based Net Ordering
Give neighboring nets higher chance to sharespacer
› Each net is represented by its expanded bbox› Nets with overlapped bbox will be routed in series› Try to align to more spacer with affordable wirelength
overhead
27
Conflict Prevention with Multi-Layer Routing
Previous DPL-aware routing: single layer Multi-layer routing: solution space much larger
28
Advantages› Conflict prevention› Detour avoidance› Flexible layout
decomposition› More chances to
align to spacer
Routing Cost Function
costj(m)/costj(t): accumulated cost from sourceto grid j when j is assigned to mandrel/trim mask
Accumulated cost from grid gi to its neighbor gj› Same layer
› Different layer
29
cost j (m) = min { cost i (m), cost i (t )} +α · W L i j + γ · V I A + β · SADPCj (m)
cost j (t) = min { cost i (m), cost i (t )} +α · W L i j + γ · V I A + β · SADPCj (t)
cost j (m) = cost i (m) + α ·W L i j + β · SADPCj (m)cost j (t ) = cost i (t ) + α ·WL i j + β · SADPCj (t)
Mandrel/trimPattern interactionSpacer
Flexible layout decomposition
3-Dimensional Path Finding
Simultaneously routing and layoutdecomposition
Whenever a grid is reached› Consider assigning it to mandrel or trim› Candidate solutions blow when exploring paths
30
3-D Path Finding by Dynamic Programming
Efficiently solved by dynamic programming
Maintain only two best solutions for each grid› Minimum cost(m) and cost(t)› Works as an upper bound to prevent unnecessary
search Still keep optimality
31
R(paths,t , LD (paths,t )) =R(paths,i , LD (paths,i )) + R(pathi , t , LD (pathi , t ))
Path Finding Example
32
Pint
Pins
Partial solution 1 Partial solution 2 Partial solution 3
Only need to keep the best one
Routing gridcandidate
Outline
Introduction Motivation SADP-Compliant Routing Guidelines SADP-Aware Detailed Routing Experimental results Conclusion
33
Experimental Results Platform
› Intel Core2 2.66GHz CPU, 4Gb Memory DPL Setup
› Scale all benchmarks to 22nm technology› PatternWidth = SpacerWidth = MinSpacing = 50nm
ForbSpacing = 100nm Benchmarks
1. Randomly generated single layer benchmarks2. Industrial two-layer benchmarks
Compared terms› WL, VIA, #Conflicts, Runtime› #sp: number of trim grids which is aligned to spacer› #nsp: number of trim grids which is not aligned to any
spacer› #forb: number of trim grids which violates forbidden
spacing rule34
Single Layer Results Compared with previous SADP-aware router [M. Mirasaeedi
et al SPIE 2011]› Simpler cost function: Minimize un-aligned trim patterns
No conflicts for both routers Runtime overhead due to complex cost function: 3.82X Achieve better SADP-friendly result
35
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
WL #sp #nsp #forb
[1]Ours
51%
39%55%
3%
Ratio
favor
favor
Multiple Layer Results Compared with WL-driven routing Runtime overhead: 4.69X Improve SADP-compliancy with little wirelength overhead
36
0
0.5
1
1.5
2
2.5
3
3.5
WL #via #sp #nsp #forb #conflict
WL-drivenOurs2%
32%
187%
31% 49% 50%
Ratio
favor
favor
Conclusion
Consider SADP-compliancy in earlier stages isnecessary for successful SADP manufacturing
Provide SADP-compliant routing guidelines forrouting tools to follow
Improve layout decomposition capability Improve pattern image quality
› Obtain more than 50% self-aligned patterns withcomparable wirelength
Future works› More routing guidelines
» Jogs, U-shape, Z-shape patterns
› Post routing/layout perturbation37
Thank you
38