Finite State Machines

Mano and Kime

Sections 4-4, 4-5, 4-8

Canonical Sequential Network

Sta

te R

egis

ter

Com

bina

tion

alN

etw

ork

x(t)

s(t+1) s(t)

z(t)clk

init

present state

present input

nextstate

present output

Mealy Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)z(t)

clk

init

present state

present input

nextstate

C2

Moore Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)

z(t)

clk

init

present state

present input

nextstate

C2

VHDLCanonical Sequential Network

Sta

te R

egis

ter

Com

bina

tion

alN

etw

ork

x(t)

s(t+1) s(t)

z(t)clk

init

present state

present input

nextstate

present output

process(clk, init)

process(present_state, x)

VHDLMealy Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)z(t)

clk

init

present state

present input

nextstate

C2

process(clk, init)

process(present_state, x)

process(present_state, x)

VHDLMoore Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)

z(t)

clk

init

present state

present input

nextstate

C2

process(present_state, x) process(present_state)

process(clk, init)

ExampleDetect input sequence 1101

fsm

din

doutclk

clr

dindout

1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 00 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0

Easy Solution:Use Shift Register

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

CLK

Q0 Q1 Q2 Q3

1 0 1 1

dout

din

More General: Use State DiagramDetect input sequence 1101

S00

S10

S110

S1100

S11011

11

0

1

0 10

0

1

0

CLR

fsm.vhd

fsm

din

doutclk

clr

entity fsm is port (clk: in STD_LOGIC; clr: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC);end;

fsm.vhd

architecture fsm_arch of fsm is

type state_type is (S0, S1, S11, S110, S1101);signal present_state, next_state: state_type;

begin

synch: process(clk, clr)begin if clr = '1' then present_state <= S0; elsif clk'event and clk = '1' then present_state <= next_state; end if;end process;

fsm.vhd

fsm.vhdcomb1: process(present_state, din)begin case present_state is

when S0 => if din = '1' then next_state <= S1; else next_state <= S0; end if;when S1 => if din = '1' then next_state <= S11; else next_state <= S0; end if;

fsm.vhdwhen S11 => if din = '0' then next_state <= S110; else next_state <= S11; end if;when S110 => if din = '1' then next_state <= S1101; else next_state <= S0; end if; when S1101 => if din = '0' then next_state <= S0; else next_state <= S11; end if;when others => null;end case;

end process;

fsm.vhd

comb2: process(present_state)begin if present_state = S1101 then dout <= '1'; else dout <= '0'; end if;end process;

end fsm_arch;

fsmx.vhd

fsm

clk_pulse

SW1bn

BTN4

LD1

LD8din

doutclr

clk

fsmx

IBUFG

clkdivmclk

fsmx.vhd

entity fsmx is

port(

mclk : in STD_LOGIC;

bn : in STD_LOGIC;

SW : in STD_LOGIC_VECTOR(1 to 8);

BTN4 : in STD_LOGIC;

led: out std_logic;

ldg : out STD_LOGIC;

LD : out STD_LOGIC_VECTOR(1 to 8)

);

end fsmx;

fsmx.vhd

architecture fsmx of fsmx is component fsm port( clk : in std_logic; clr : in std_logic; din : in std_logic; dout : out std_logic); end component;

fsmx.vhdcomponent clk_pulse

port(

BTN4 : in std_logic;

cclk : in std_logic;

clr : in std_logic;

clk : out std_logic);

end component;

signal clr, clk, cclk, bnbuf: std_logic;

signal clkdiv: std_logic_vector(23 downto 0);

fsmx.vhd

U0: clk_pulse port map

(BTN4 => BTN4, cclk => cclk, clr =>clr, clk => clk);

U1: fsm port map

(clr =>clr, clk => clk, din => SW(1), dout => LD(8));

LD(1) <= SW(1);

Detect input sequence 1101