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Counters
Mano & Kime
Sections 5-4, 5-5
Counters
• Ripple Counter
• Synchronous Binary Counters– Design with D Flip-Flops– Design with J-K Flip-Flops
• Counters in VHDL
Counters ---
A 4-bit Ripple Counter
Recall...
Less SignificantBit output is Clockfor Next Significant Bit!(Clock - active low)
J-K Flip-Flop from a D Flip-Flop
DQ = J & !Q # !K & Q
DQ = Q
DQ = 0
DQ =!Q # Q = 1
DQ = !Q
Counters
• Ripple Counter
• Synchronous Binary Counters– Design with D Flip-Flops– Design with J-K Flip-Flops
• Counters in VHDL
CLK
D Q
!Q
CLK
D Q
!Q
CLK
D Q
!Q
Q0Q0.D
Q1
Q2
Q1.D
Q2.D
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
Divide-by-8 Counter
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
Divide-by-8 Counter
Q2
Q1 Q000 01 11 10
0
1 1 11
1
Q2.D
Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
Divide-by-8 Counter
Q2
Q1 Q000 01 11 10
0
1
1
11
1
Q1.D
Q1.D = !Q1 & Q0 # Q1 & !Q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
Divide-by-8 Counter
Q2
Q1 Q000 01 11 10
0
1
1
11
1
Q0.D
Q0.D = ! Q0
CUPL SimulationOutput File
CLK
D Q
!Q
CLK
D Q
!Q
CLK
D Q
!Q
Q0Q0.D
Q1
Q2
Q1.D
Q2.D
s0 0 0 0 1 1 1s1 0 0 1 0 0 0s2 0 1 0 0 0 1s3 0 1 1 0 1 0s4 1 0 0 0 1 1s5 1 0 1 1 0 0s6 1 1 0 1 0 1s7 1 1 1 1 1 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
3-Bit Down Counter
3-Bit Down Counter
Q2
Q1 Q000 01 11 10
0
1 1 11
1
Q2.D
Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0
s0 0 0 0 1 1 1s1 0 0 1 0 0 0s2 0 1 0 0 0 1s3 0 1 1 0 1 0s4 1 0 0 0 1 1s5 1 0 1 1 0 0s6 1 1 0 1 0 1s7 1 1 1 1 1 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
3-Bit Down Counter
Q2
Q1 Q000 01 11 10
0
1
1
11
1
Q1.D
Q1.D = !Q1 & !Q0 # Q1 & Q0
s0 0 0 0 1 1 1s1 0 0 1 0 0 0s2 0 1 0 0 0 1s3 0 1 1 0 1 0s4 1 0 0 0 1 1s5 1 0 1 1 0 0s6 1 1 0 1 0 1s7 1 1 1 1 1 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
3-Bit Down Counter
Q2
Q1 Q000 01 11 10
0
1
1
11
1
Q0.D
Q0.D = ! Q0
s0 0 0 0 1 1 1s1 0 0 1 0 0 0s2 0 1 0 0 0 1s3 0 1 1 0 1 0s4 1 0 0 0 1 1s5 1 0 1 1 0 0s6 1 1 0 1 0 1s7 1 1 1 1 1 0
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
Up-Down Counter
Up-DownCounter
Q0
Q1
Q2
clock
UD
UD = 0: count upUD = 1: count down
Up-Down Counter
1 0 0 0 1 1 11 0 0 1 0 0 01 0 1 0 0 0 11 0 1 1 0 1 01 1 0 0 0 1 11 1 0 1 1 0 01 1 1 0 1 0 11 1 1 1 1 1 0
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
0 0 0 0 0 0 10 0 0 1 0 1 00 0 1 0 0 1 10 0 1 1 1 0 00 1 0 0 1 0 10 1 0 1 1 1 00 1 1 0 1 1 10 1 1 1 0 0 0
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
Up-Counter Down-Counter
UD Q2
Q1 Q000 01 11 10
00
01
11
10
Up-Down Counter
Make Karnaugh maps for Q2.D, Q1.D, and Q0.D
Counters
• Ripple Counter
• Synchronous Binary Counters– Design with D Flip-Flops– Design with J-K Flip-Flops
• Counters in VHDL
J-K Flip Flop Design of a Binary Up Counter
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
Synchronous Binary Counters
4 - Bit CounterLogic Diagram
Counters
• Ripple Counter
• Synchronous Binary Counters– Design with D Flip-Flops– Design with J-K Flip-Flops
• Counters in VHDL
4-Bit Binary Counter with Reset