FINITE STATE MACHINES (FSMs)

FINITE STATE MACHINES (FSMs)

Dr. Konstantinos Tatas

ACOE161 - Digital Logic for Computers - Frederick University

Finite State Machine

• A generic model for sequential circuits used in sequential circuit design


Finite state machine block diagram

• State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states)

• Next state logic: Combinational circuit that determines the next state as a function of the current state and the input

• Output logic: Combinational circuit that determines the output as a function of the current state and the input

NEXT STATELOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

...

STATE MEMORY

OUTPUT LOGIC

CLK

INPUTS

PREVIOUS STATE

NEXT STATE

OUTPUTS


Finite State Machine types

• Mealy machine: The output depends on the current state and input

• Moore machine: The output depends only on the current state– State = output state

machine: A Moore type FSM where the current state is the output

COMBINATIONAL LOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

...

STATE MEMORY

OUTPUT LOGIC

CLK

INPUTS

PREVIOUS STATE

NEXT STATE

OUTPUTS

COMBINATIONAL LOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

...

STATE MEMORY

OUTPUT LOGIC

CLK

INPUTS

PREVIOUS STATE

NEXT STATE

OUTPUTS

COMBINATIONAL LOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

...

STATE MEMORY

CLK

INPUTS

PREVIOUS STATE

NEXT STATE

OUTPUTS


State diagram

1000

01 11

0/1

0/10/1

1/0

1/0

1/0

1/0

0/0

A state diagram represents the states as circles and the transitions between them as arrows annotated with inputs and outputs


Analysis of FSMs with D flip-flops

• Determine the next state and output functions

• Use the functions to create a state/output table that specifies every possible next state and output for any combination of current state and input


EXAMPLE

Q

QSET

CLR

D

Q

QSET

CLR

D

X

A

A’

B

B’CP

Y


Next state equations and state table for example

• A+=Ax+Bx• B+=A΄x• Y=(A+B)x΄

A B x A+ B+ y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 1 1 0

1 0 0 0 0 1

1 0 1 1 0 0

1 1 0 0 0 1

1 1 1 1 0 0


Q

QSET

CLR

D

Q

QSET

CLR

D

X

A

A’

B

B’CP

Y

• A+=Ax+Bx

• B+=A΄x

• Y=(A+B)x΄

A B x A+ B+ y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1


Sequential circuit design methodology• From the description of the functionality or the

state/timing diagram find the state table• Encode the states if the state table contains letters• Find the necessary number of flip-flops• Select flip/flop type• From the state table, find the excitation tables and

output tables• Using Karnaugh maps find the flip-flop input logic

expressions• Draw the circuit logic diagram


Example: Design the sequential circuit of the following state diagram

00

01 11

10

0

0

0

0

1

1

1

1


State/excitation table

A B x A+ B+ DA DB JA KA JB KB

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1


Karnaugh maps for combinational circuit


Circuit logic diagram


Example: counter000

001 110

010

100

101


Self-correcting state machines

• The previous example did not include two possible states “011” and “111”. If the counter unexpectedly falls into one of those states there are two possibilities:– The counter will recover by entering a valid state after

a finite number of cycles (self-correcting)– The counter will stay in a non-valid state until the f/fs

are reset (not self-correcting)• Finite state machines should be designed to be self

correcting by assigning non-valid states to a valid next state (no don’t cares in the excitation table)


Example

• Design a self-correcting one-digit BCD counter


State minimization/assignment

• Often the state of the circuit is not also the output and therefore the states are named abstractly

• State minimization and state assignment are then required

• State minimization is the simplification of the state diagram so that a circuit with less states produces the same output sequence

• State assignment is the process of assigning a binary number to each state


Example

a

0/0

b

1/0

c0/0

0/0

d

1/0

1/0

f

e0/0

0/0

1/1

1/1

1/1

g

0/0

1/1

0/0

•State values are not important just the input/output sequence

•States are symbolized with letters


State table

a

0/0

b

1/0

c0/0

0/0

d

1/0

1/0

f

e0/0

0/0

1/1

1/1

1/1

g

0/0

1/1

0/0

Current state

Input Nextstate

Output

a 0 a 0

a 1 b 0

b 0 c 0

b 1 d 0

c 0 a 0

c 1 d 0

d 0 e 0

d 1 f 1

e 0 a 0

e 1 f 1

f 0 g 0

f 1 f 1

g 0 a 0

g 1 f 1


State equivalence

• Two states are equivalent if for any element of the input set both produce the same output and send the circuit to the same state or an equivalent one.

• One of the two equivalent states can be eliminated from the state diagram

Current state

Input Nextstate

Output

a 0 a 0

a 1 b 0

b 0 c 0

b 1 d 0

c 0 a 0

c 1 d 0

d 0 e 0

d 1 f 1

e 0 a 0

e 1 f 1

f 0 g 0

f 1 f 1

g 0 a 0

g 1 f 1


State minimizationCurrent

stateInput Next

stateOutput

a 0 a 0

a 1 b 0

b 0 c 0

b 1 d 0

c 0 a 0

c 1 d 0

d 0 e 0

d 1 f 1

e 0 a 0

e 1 f 1

f 0 g 0

f 1 f 1

g 0 a 0

g 1 f 1

e

d

d

a

0/0

b

1/0

c0/0

0/0

d

1/0

1/0

e0/0

0/0

1/1 1/1


State assignment

• Since we don’t care about the actual flip-flop values for each state we can assign each state to any binary number we like as long as each state is assigned a unique binary number

• If we use 3 bits to encode the states, we have

possible encodings

)!58(!5

!8

5

8

state Encoding 1 (binary)

Encoding 2(Gray)

Encoding 3

a 000 000 000

b 001 001 100

c 010 011 010

d 011 010 101

e 100 110 011


One-hot encoding• One flip-flop per state

encoding• Leads to greater

number of flip-flops than binary encoding but possibly to simpler logic

state Encoding1 (binary)

Encoding 2 (Gray)

Encoding 3 (one-hot)

a 000 000 00001

b 001 001 00010

c 010 011 00100

d 011 010 01000

e 100 110 10000

Algorithmic State Machines


Introduction

Digital system is specified by the following three components:

• The set of registers in the system• The operations that are performed on the

data stored in the registers.• The control that supervises the sequences

of operations in the system.


Control and Datapath Interaction


Datapath

• Binary information in digital systems classified as either data or control.

• Data – bits of information manipulated by performing arithmetic and logic operations.

• Hardware components realizing above operations are adders, decoders, multiplexers, counters e.t.c


Control Path

• Command signals used to supervise execution of algorithms by datapath.

• Bi-directional communication with datapath through status conditions used to determine the sequence of control signals.

• Control logic inherently sequential.

• Control logic is usually implemented using FSMs


• Often we have to implement an algorithm in hardware instead of software

• Algorithm is a well defined procedure consisting of a finite number of steps to the solution of a problem.

• It is often hard to translate the algorithm into an FSM.

• ASMs can serve as stand-alone sequential network model.

Algorithm Implementation


Algorithmic State Machine•Used to graphically describe the operations of an FSM more concisely

•Resembles conventional flowcharts – differs in

interpretation.

•Conventional flowchart – sequential way of

representing procedural steps and decision paths

for algorithm

-No time relations incorporated

•ASM chart – representation of sequence of

events together with timing relations between

states of sequential controller and events

occurring while moving between steps


ASM Chart•Three basic elements: state box, decision

box and conditional box

-State and decision boxes used in conventional

flowcharts

-Conditional box characteristic to ASM

•State box

-Used to indicate states in control sequence

•Register operations and output signals used to

control generation of next state written


State box

•Represents one state in the ASM.

•May have an optional state output list.

•Single entry.

•Single exit to state or decision boxes.


State Box

State name T3

•Binary code of T3 – 011

•Register operation R <- 0

•START – name of

outputs signal generated

in this stage


Decision box

• Provides for next alternatives and conditional outputs.

• Conditional output based on logic value of Boolean expression involving external input variables and status information.

• Single entry.• Dual exit, denoting if Boolean

expression is true or false.• Exits to decision, state or conditional

boxes.


Decision Box

•Input condition subject to

test inside diamond shape

box

•Two or more outputs

represent exit paths

dependant on value of

condition in decision box

•Two paths for binary based conditions


Conditional output box

• Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted.

• Single entry from decision box.• Single exit to decision or state box.


•In state T1

Output signal START

generated

Status of input E

checked

•If E = 1, R <- 0,

otherwise remains

unchanged

•Conditional

operation executed

depending on result

of coming from

decision box

Conditional Box


ASM Block

• Consists of the interconnection of a single state box along with one or more decision and/or conditional boxes.

• It has one entry path which leads directly to its state box, and one or more exit paths.

• Each exit path must lead directly to a state, including the state box in itself.

• A path through an ASM block from its state box to an exit path is called a link path.


Timing Considerations All sequential elements in datapath and control

path controlled by master-clock generator.

Does not necessarily imply single clock in design.

•Multiple clocks can be obtained through division of clock

signals from master-clock generator.

•Not only internal signals, but also inputs

synchronized with clock.

•Normally, inputs supplied by other devices working

with the same master clock.

•Some inputs can arrive asynchronously

Difficult to handle by synchronous designs, require

asynchronous glue-logic.


•In conventional flowchart, evaluation of each chart element takes one clock cycle

Step 1: Reg A incremented

Step 2: Condition E evaluated

Step 3: Based on evaluation results, state

T2, T3 or T4 entered

•In ASM the entire block considered

as one unit

•All operations within block occurring

during single edge transition

The next state evaluated during the same clock

System enters next state T2, T3 or T4 during transition of next clock

ASM Block


ASM Block

• An ASM block describes the operation of the system during the state time in which it is in the state associated with the block.

• The outputs listed in the state box are asserted.

• The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed.

• If a conditional box is found in the selected path then the outputs found in its output list are asserted.

• Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1.


Example 2

• Extract the FSM diagram from the ASM diagram

T0

x

F

T1

T2

x

E

T4

T6

T3

T7

0

0

0

T5

1

0

1

1


Example

• Design a circuit that implements the following pseudocode:

a=0;

for (i=0;i<5;i++)

if b=0 then //boolean

a = a+i;

out = a;

else out = a-i;


ASM charta <- 0i <- 0

Load

b=0

a <- a+IOut <- ai <- i+1

a <- aOut <- a-i

i <- i+i

T F

if else

i=5

end

T F


Control/datapath partitioninga=0;for (i=0;i<5;i++)if b=0 then a = a+i; out = a;else out = a-i;

External control inputs: bInput data: a, iStatus conditions: i< 5Commands: i++, a = a+i, out=a, out=a-i


Datapath design

a=0; // register for a

for (i=0;i<5;i++) // adder for i++

if b=0 then

a = a+i; //adder for a+i

out = a;

else

out = a-i; //adder for a-i

//mux for out


ASM charta <- 0i <- 0

Load

b=0

a <- a+IOut <- ai <- i+1

a <- aOut <- a-i

i <- i+i

T F

if else

i=5

end

T F


Datapath design

counter

+

-

a

reg

3i

a+i

a-i

2X 1 MUX

S0

out

fineni

ena

2 X 1

MUX

S1


Control logic design

• State Diagram

• State encoding:

• Load:00• If: 01• Else: 10• End: 11

LOAD

IF ELSE

END

b=0/eni=1ena=1S0 =x

fin=0/eni=0ena=0S0=0

fin=1/eni=0

ena=0S0=0

fin=1/eni=0ena=0S0 =1

b=1/eni=1ena=1S0=x


S1 =x

S1 =x

S1 =x S1 =x

S1 =1S1 =0


State/excitation

table

A B b fin DA DB eni ena S0 S1

0 0 0 0 0 1 1 1

0 0 0 1 0 1 1 1

0 0 1 0 1 0 1 1

0 0 1 1 1 0 1 1

0 1 0 0 0 0 0 0

0 1 0 1 1 1 0 0

0 1 1 0 0 0 0 0

0 1 1 1 1 1 0 0

1 0 0 0 0 0 0 0

1 0 0 1 1 1 0 0

1 0 1 0 0 0 0 0

1 0 1 1 1 1 0 0

1 1 0 0 1 1 0 0

1 1 0 1 1 1 0 0

1 1 1 0 1 1 0 0

1 1 1 1 1 1 0 0

LOAD

IF ELSE

END

b=0/eni=1ena=1S0 =x


fin=1/eni=0

ena=0S0=0

fin=1/eni=0ena=0S0 =1

b=1/eni=1ena=1S0=x


S1 =x

S1 =x

S1 =x S1 =x

S1 =1S1 =0


ASM versus FSM


Timing of Transition Between States

During single clock cycle

•Reg A incremented

Condition E evaluated

• If E=1 then R <-0

• Control transferred to state T2, T3 or T4

• Control path and datapath work simultaneously


Design Example – Initial Spec

•Hardware spec:

-Two DFFs (E and F) and one 4-bit binary counter A

DFFs in A referred to as A4, A3, A2 and A1

-A4 stores MSB, A1 LSB

•Operation spec:

Start signal S = 1

-A4-A1 regs cleared (counter set to 0)

-F reg cleared

•From next clock cycle counter increments by one every clock cycle until operation stops


ASM Chart

Three states and

three blocks


Timing Sequence

•Operation in each ASM block executed in one clock cycle

-Operations in state and conditional boxes executed by datapath

-Changes from one state to other performed in by control path


Two Flip-Flops (E,F) and one4-bit counter A.The system is initiated by a start Signal S, by clearing the counter A And flip-flop F. The counter is thenIncremented by one starting for thenext clock and continues to increment Until the operations stop. Bits A3 and A4Determine the sequence of operations:

1. If A3=0, E is cleared to 0 and the count continues.

2. If A3=1, E is set to 1; then if A4=0, the count continues, but if A4=1, F is set to 1 on the next clock pulse and the system stops counting.

3. Then if S=0, the system remains in the initial state, but if S=1, the

operation cycle repeats.

Design Example


•Upon entering T1 E=1 (no change from T0), F=0 (cleared in T0,S=1)

•System in T1 for 13 clocks

-At each clock counter

incremented

-Depending on current state of

A3 and A4 E cleared or set

•When A3,A4=1 state T2 entered

-Controller in T2 for one clock

-As A3=1, F=1, state T0 entered

•System in state T0 until S =1

Sequence of Operations


State Table

•Many minimization methods of sequential circuits

involve circuit description in form of state table

•Number of states in ASM determines number of

DFFs implementing states

-n flip-flops result in 2 n states

-Three states in ASM – two flip-flops needed

•State diagram converted into state table

•Controller state table – list of present states and

inputs, with corresponding next states and outputs

-Don’t care conditions used for hardware minimization


State Table, cont.

•Example: T0 = 00, T1 = 01, T2 = 11

-State 10 not used (don’t care assignment)

•Flip-flops represented states labeled G1 and G0

•Three inputs and three outputs

-Inputs taken from conditions in decision boxes

-Outputs equivalent to present states of controller


State Table, cont.


Datapath Design


Register Transfer Representation


Example

• Draw the ASM diagram and control logic of a digital circuit that counts the number of people in a room. People enter the room through a door with a sensor that makes a signal x change from 1 to 0. People exit through a second door with a similar y input. x and y are synchronized with the clock but can stay in one state for more than a single pulse. The datapath is an up/down counter and an LCD display.

Sequential circuits and MSI devices

Dr. Konstantinos Tatas


Register

• A register is a sequential circuit that stores a word.

• It is composed of flip-flops (usually D-type)

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

CP

I1

I2

I3

I4

A1

A2

A3

A4


Shift Register• A register that “shifts” its contents in one direction• Composed of D f/fs chained so that each Q output

is connected to the next D input

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D OutputInput

Clk


Bidirectional Shift Register with Parallel Load

• Inputs:– Clock

– Reset

– 2 Control bits• 00: no shift

• 01: shift right

• 10: shift left

• 11: parallel load

– Parallel load inputs

• Outputs:– Parallel output


Bidirectional Shift Register with Parallel Load Circuit Diagram


Ring Counter

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FINITE STATE MACHINES (FSMs)