Finger print Mr Adapanwar AN.pdf

7/29/2019 Finger print Mr Adapanwar AN.pdf

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Finger print recognition usingMATLABMr. Abhay N. AdapanawarAssistant Professor (Electronics Dept) B.V.D.U.C.O.E., PUNE.Mr. R. Y. MaliM.E. (Electronics) B.V.D.U.C.O.E., PUNE.ABSTRACT: This report concerns thedesign and implementation of afingerprint verificationJidentificationSystem for a small-scale organizationparticularly for research &developmentdepartment, which requires high securitywith the limited number of users.The purpose of the project was toimplement the system withthe use of anImage processing with programmingtool Matlab. Different methods wereevaluated and efforts were put intofinding the best suitable for that specialenvironment. Main issues encounteredare image enhancement, featureextraction, template generation and"verification/identification.To make good use of the advantagesof the image processing most of theprocessing was made in the spatialdomain. A number of simulations wereperformed and evaluated. Overall resultswere considered sufficiently good, andmet the predefined specifications.BASIC FLOW:There are two phases in our projectonline phase and Offline phase. Inoffline phase person has to fill theinformation form, after which he will beassigned a unique tD.The fingerprint ofthe concerned person will be processedto extract the minutiae points. Thesepoints are used to generate a template,which will bestored in thedatabase.During the online phase person hasto enter his name and allottedidentification number. This is comparedwith data stored in the database.Aftermatching of name and identificationnumber the person has to input hisfingerprint which will be processed and

a temporary template will be generatedwhich will be compared with the onestored inthedatabase. And according tomatching score, the person will begranted access or denyPLAN OF WORK:Ihave divided the work in stepwiseupgrading manner. This can behighlighted as follows.l.Study of biometrics literature chosethebest suitable method for security system.2.Study of fingerprint as a biometricmethod andhow torepresent it.3.study of basics of image processingalgorithms.4.Study of Matlab as a programmingtool for imageprocessing.5.1mplement the algorithms forpreprocessing of fingerprint imageincluding enhancement, segmentation,binarization, thinning, Implementationof featureextraction algorithm.6.1mplementation of feature validationalgorithm.Theory:Minutiae extraction is relatively morerobust to various sources of fingerprintdegradation. Therefore, in AFIS I usedthe two most prominent types of minutedetails for their stability and robustness:(i) ridge ending and (ii) ridge bifurcationAlgorithms:l . Binarization: In a fingerprint image,the background regions generally exhibita very low gray-scale variance value,whereas the foreground regions have avery high variance. Hence, a methodbased on variance thresholding can beused to perform the segmentation.Firstly, the image isdivided into blocks


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NCES'06handling and digital signal processing. Wehave compared our architecture against instruction

level models of some commercial microprocessorslike Motorolas 68I1C08, 68000, Intels 80SI, 8Ox86and Tis MSP4JO but it was very difficult to obtainfair results. Most of the parameters of ourmicroprocessor are scalable (word width, cache andregister me dimensions. ALU functions), thereforewe tried to adapt it as close as possible. to thecapabilities of the respective opponent and achieved

.powerdelay product Savings between 50% to 85/.using our test suite. To avoid a dependence on thequality of a C compiler all of the benchmarkprograms lor each processor. have been coded inassembler, Aller system simulation of one instanceof tbe proposed new architecture we transferred allmodules into symhesizable VUDL and generated agate level netlist to use it as the control part of amedical implant for neural stimulation.

VI. CONCLUSIONWe presented a new microprocessorarchitecture targeting on the reduction of the powerdissipation in modem systems-on-a-chip like

medical implants or micro-transponders. Weintroduced concepts to optimize data and controlflow by utilizing the local characteristic ofcomputation. New types of data storage files, asophisticated multi-level instruction-cache togetherwith some other concepts lead to an essentialdecrease of :;,e power-delay product compared toother architect UI cs.

REFERESCES(1\ Pigue. C: Masgonty J .,.M.: ArmC; DurandS.,

Schneider T.; Rampogna F.; Scarnera c.,lscli C: Bardyn l-P.; Pache R.: Dijkstra E.Low-power design of 8-b embeddedCooIRi5C rnicrocontroller cores. In Solid-State Circuits, IEEE Journal of , July1997.\'01.32, ~o.7, Pagers): \067-1078.Biermann B.; Both A. W.; Lerch R.G.;I~anoliY.~Sie\ ert K..A new 8 bit C-prograrnmablemicroconirollerfor embedded multitaskingapplications, In European Solid StateCi-cuits Conference S.378-3g1.Horowitz M.; Indermaur T.; GonzalezR.Lo"P'Ower digital design. In Low PowerElectronics. 199t Digest of TechnicalPapers., 1tEE Symposium. Pagers): 8-11.Chandrakasan A.P.: Sheng S.; Brodersen

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Lo..power CMOS digital design. In IEEEJoumal of Solid-State Circuits, April 1992,VoL:!7, ~o.4, Page(s): - t 73-484.[5} Lefurgy C;Bird P.; Chen L-C.;Mudgc: T.

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Improving code density using compression techniques.In Microarchitecture, 1997. Proceedings., ThirtiethAnnual IEEElACM International Symposium on.Page(s): 194-203.Hakenes R.; Manoli Y. A Segmented Gray Codefor Low-Power Microcontroller Address Buses. InEUROMICRO 99, Workshop on Digital SystemDesign, 1999. EUROMICR099. Proceedings. VolumeI,Pages(s): 240-243.Hakenes R.;Manoli Y.lmproving MicrocontrollerPower Consumption through a Segmented Gray CodeCounter. In Computer Design: VLSI inComputers andProcessors, 1999. ICCD 99. Proceedings. InternationalConference on, Pagers): 277- 278.Hakenes R.: Manoli Y. The Microcoredevelopment system: a unified environment fordesigning new microprocessors. In Computer Design:VLSI in Computers and Processors. 1998_ ICCD 98.Proceedings. International Conference on, Pagc(s):190-191.

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NCES'06cache and register filecontexts are switched back tothe calling function. During the subroutine call theinstructions and data of the calling function keeptheir relevance and are reactivated after the return.Additionally a multiple call of a function, which isstill stored in one of the cache segments. can behandled completely without any external mernoryaccesses. This implies that each of the cachesegments owns a separate cache pointer. which isbearable due to the short pointer width. The cachecontroller tracks the validity of the code stored in asegment and manages seamcssly the loading ofrequired subroutines. This concept docs an effectivepower saving by reusing formerly loaded programcodes and issuitable for function calls as well as forinterrupts. To enhance tho: savings even more weadded table-lookup based function calls managed bythe cache controller .

IV. CACHE CONTROllERInitiated by a special opcode a table of

maximum 32 elements is loaded into the cachecontroller which associates a function number withIts external memory address. During the programonly this function number. which can be specifiedby the compiler. is used to call the function. Thisreduces the code size as well as the dissipatedpower of the function call. Additionally it decouplesthe processor core completetly from the xternalmemory. The processor itself does not need to haveany access to the external memory. all of thecommunication to the outside is performed by thecache controller. It handles the transport of data toand from the register files and to the cachesegments. The only exception is a specialinstruction to access external peripherals. which ispossible through a register content used as datapointer. Rcsuiting from this decoupling ofcomputational core and memory the external busdesign is completely independent from internalneeds like data word width or clocking frequency.This is extremely useful for embedded systems-on-a-chip. which are often limted in the amount ofpads. because it easily enables. for example, the useof a serial EEPROM as program memory. The onlyrequirement isa sufficient core-memory bandwidth.othcrv vise th< processor has to perform energyconsumng wait-states.

Another interesting possibility enabled by thedecoupling mentioned is coding of the programdata. As shown in (Fig. 5) some power savings canbe- achieved by using compression/decompression'algorithms on the program code. We haveimplemented a Huffman decompression algorithminto the cache controller. which decreases theneeded size of theexternal memory by a factor of 2.but enlarges

"he cache controller. by a factor of 2 'as well.Whether this does any power saving depends on thedesign of the external buses, the narrower they are.

TSEC Mumbaithe better is the performance. This is due to the fact, thatdecompression is a bit oriented algorithm. that does its bestjob on bit streams. Therefore we do not recommend this inany case. but it demonstrates the possibilities of the approach.

v. EXTERNAL MEMOR Y AC CF SSTo reduce the transitions on the external memory buses,

we implemented a 16-bit segmented gray code programcounter (see fig. 6,7), which saves about 25-30"1. of the bustransitions an equivalent binary counter would cause.Additionally the size of the counter is about 10"1. smaller thanits binary counterpart, which avoids some internal transitionsas well. Due to the sequential memory access scheme of theproposed architecture abig benefit is taken from the usage ofa gray code.

The introduced mcroprocessor architecture wasdeveloped using a high level simulation approach. Allmodules have been implemented in C within a standardizedenvironment and many architectural alternatives have beeninvestigated. A specially designed test suite for embeddedsystems has been used to compare the switching activities onarchitectural level. This benchmark consists of typicalapplications of mcrocontrollers, including arithmeticoperations. interrupt driven control tasks, field bus

f u I O ] O J O j - . 0 L i l i l 1 I t l - . 810 [ 1 ) 0 10 1 - 1 1110 [ 11 ,1 - 911 [ 11010 i - 2 10101111 1 - 101 1 1 0 1 0 1 01 . J IGEliliI- 1 111101011 ] . 4 1 0 [ 1 1 1 1 0 1 . 12[OfOJ il lj - S I I I [ i l i l - 13[~[{@liJ . 6 m~!1lO l . 141 ,1 11011 1 .. . 7 10101 ,1 0 1 .. . 15

Fig. 7. Optimal GraySegment

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Fig. 4. Straight Forward Cache OperationThe' concept just presented mnimzes the

energy for local variable accesses as well as forfunction calls. Rut additionally each program needsglobal data to run. To cope with this issue weimplemented a frequently used compileroptimzation technique into our architecture. theelimnation and compaction of constants. Weprovide a second segmented register file like theformerly presented but without the automatic copyfeature. This file is used to store constant values andglobal variables and is loaded by the cachecontroller presented in section 4 with blocks of databefore thev are needed by the processor. To controlthis. the compiler has to collect portions of data(variables and constants) at the beginning of thecode sequence (see fig. 3). The processor accessesthese constants by addressing the preloaded internalregisters, which is more efficient concerning energyand decreases the sizeof the program code. becausethe value of the data can be 'replaced by a shortreference to it. For example. if the l6-bit constantvalue 0 has to be used within a function seventimes. the achieved saving hy this method is 75 outof 11~ bit code size and the same amount ofexternal memory accesses. The seven movements of16-bit constant data can be replaced by a single 16-bit transfer followed by seven 3-bit registerreferences,

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Fig.. 5. Subroutine Cache Management

III. INSTRUCTION SETTo optimze the control parts of themcroprocessor architecture we applied simlar

methods as used inthe datapath. The key concept isagain ~ng advantage of the local characteristic of

TSEC , Mumbaicomputation. We implemented a restriction into theinstruction set, which does not cause any functionallimtation. but enables an effective way of power savingthrough instruction caching. The conditional branches or ourinstruction set arc:restricted to the backward direction. with arelative displacement. These branches have to beperformedwithin the range of the instruction cache. which is in our case32 words. This size "as selected as an optimum afterintensive simulation and power estimation using the test suitefor embedded applications introduced in section 5. Resultingfrom this restriction. a r-owerful caching scheme is possible.During straight forward operation the cache: controllerpermanently transports the following opcode to the nextunused cache location using a ring buffer scheme (fig. 4).Every time a conditional branch applies. the external programcounter is marked inva!;d and an internal cache pointer takesover its function. As J .:-:--~:1$ the processor performs the localloop no external memory access is needed. Additional1?' thereare no transitions of the external program counter during theloop. while the cache pointer ismuch smaller in size and onlydrives small capacitances of a small internal memory. Thisalso contributes to a reduced power consumption. To makesure that frequent cache-msses do not cut the aspired benefit,the compiler has to take care of dividing the code into smallportions. One concept 10 do this ctli~entl~ with .ourarchitecture is to introcuce as much as possible hierarchy totothe code.Another regularly used mechanism (If programmnglanguages is function calling. We provide i.nstructi~ns !'orconditional and unconditional function calls m combinationwith a multi-level caca.r-g scheme. Like the register file thecache is segmented ::-,:0 8 parts. which are separatelymanaged by the: cache controller (:'


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NCES'06There have been some approaches in the pastto reduce the number of transitions (clock cycles)

per operation for microprocessors Ref. (II. but veryfew on the architectural level. This worlc. presents anew microprocessor architecture. whichconcentrates on the avoidance of data transports andtransitions. The main concept is utilizing the localcharacteTistic of computation, which means alloperations should be performed within themicroprocessor core whenever possible. To reachthis aim we reorganized the data and control flow ofthe architecture. Section 2 introduces the localstorage concept which minimizes data transports forarithmetic operations and function calls. Section 3deals wit'" the multi-level instruction cache andsome control flow optimizations.

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Fig. 2. Subroutine Call TransfcrsSection 4 describes the cachecontrollcr. whichmanages the table-lookup function call scheme andand optional Huffman-decoding. Section 5explainsthe external gray-code address encoding. and section6concludes thepaper.

11. EFFECTIVE LOCAL STORAGEAs shown in Fig. I. the amount of internalregisters intluences heavily the required number ofdata transports per calculation. because most of thearithmetic algorithms c;;~t into quite local

computations. Therefore local registers can beefficiently used to store intermediate results. But themore internal registers exist. the less is the benefitcompared to the external memory access. due:to theincreasing capacitance of the register file hit linesand the growing opcode width of the: processor.which has to beable to address all storage cells, Ourapproach uses a segmented structure of theregisterfile, prov.ding access to 256 registersorganized into 8 rows with 8 registers each (fig. I).The processor can only address registers within thecurn:ntly selected row. This decreases the numberof addressing bits from eight to three. which saves62.5 % of the transitions and opcode size perregister access. As a minor disadvantage an

TSEC ,Mumbaiadditional opcode is necessary to control row switching. Thisrow switching concept matches perfectly with the commonlyused local scope variables of programming languages like Cand can act as an improved stack. Usually the callingparameters are copied into the local data scope of thesubroutine during a function call and after computation theresults are copied back. To reduce the amount of C O e T & Ywhich is necessary for that regularly needed operation weadded the capability to the register file to directly copy fromone row to the next during a context switch. for that purposethe switching opcode contains a copy mask that selects theregisters to be copied (see fig. 2). During thc function returnthe same method is used tv copy the results back to the dataspace of the calling function. The resu It is that the subroutinesfind themselves within an indepenrantly usable: data space ofregisters with some of them preloaded by calling parameters.If more registers are necessary than one row can offer. thesubroutine can switch itself to another free row of eightregisters. Unlike other concepts Ref: (2) which aim insimplifying subroutine calls this method has the advantage ofperforming the program language demanded parameter copywithin the register file. That can be done very efficientlywithout using any buses Of" large parasitic capacitances.

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End points Image I Image2

Filtered points ImageI Image2References :l. Matlab Toolbox: Image processing manual.2. IEEE signal processing magazine: Color image processing [Volume 22 ,NumberI.January 2005].3. Digital Image processing: R. C. Gonzalez ,R. E.Woods [Pearson education]4. UK Government's Biometrics Working Group, "Best Practices in Testing andReportingPerformance of Biometric Devices", January 2000(http://www.atb.org.uk/bwg/bestpracIO.pdt)5. J.L. Wayman, "ThePhilippine AFIS Benchmark Test" in National test center collectedworks 1997-2000 Sept 2000 (http://www. Engr.sjsu.edu/biometrics/collected)


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and the gray-scale variance is calculatedfor each block in the image. If thevariance is lessthan theglobal threshold,then the block is assigned to be abackground region; otherwise, it isassigned to bepart of theforeground.

;=3 j=8Local mean= 1/64* L 'Lf(i,j);= j=\

This gray scalevalue of eachpixel iscompared withthis local mean (1) andthepixel will bemarked asbackgroundor foreground.Qx, y)=background point-if f(x, y)>T=Foreground pointif f(x, y)

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Finger print Mr Adapanwar AN.pdf