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Final Exam Review

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word7 is high if

A2 A1 A0 = 111

word0 is high if

A2 A1 A0 = 000

logical effortof each inputis (1+3.5)/3per wordline output

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Skewed gates

HI-skew gu = 2.5/3 = 5/6

gd = 2.5/1.5 = 5/3

gavg = 5/4

p = 2.5/3 = 5/6

4

LO-skew gu = 2/1.5 = 4/3 (unskewed inverter with equal rise time pMOS size 1, nMOS size 0.5

gd = 2/3 (unskewed inverter with equal fall time pMOS size 2, nMOS size 1

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HI- and LO-Skew

• Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.

• Skewed gates reduce size of noncritical transistors– HI-skew gates favor rising output (small nMOS)– LO-skew gates favor falling output (small pMOS)

• Logical effort is smaller for favored direction• But larger for the other direction

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Asymmetric Gates

• Asymmetric gates favor one input over another• Ex: suppose input A of a NAND gate is most critical

– Use smaller transistor on A (less capacitance)– Boost size of noncritical input– So total resistance is same

• gA = 10/9

• gB = 2

• gtotal = gA + gB = 28/9

• Asymmetric gate approaches g = 1 on critical input• But total logical effort goes up

Areset

Y

4

4/3

22

reset

A

Y

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Input Order• Our parasitic delay model was too simple

– Calculate parasitic delay for Y falling• If A arrives latest? 2• If B arrives latest? 2.33

6C

2C2

2

22

B

Ax

Y

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a unit CMOS inverter delivers current I in both rising and falling transitions

Pseudo-nMOS inverter: pMOS delivers I/3; nMOS delivers 4I/3 (net pull down current is 4I/3 – I/3 = I

logical effort gd = (4/3)/3 = 4/9 parasitic delay pd = (6/3)/3 = 6/9

logical effort gu = gd x 1/3 = 4/3 parasitic delay pu = pd x 3 = 18/9 ( only I/3)

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10

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4-input NAND unfooted + Hi INV

g = 4/3; g = 5/6

G = 20/18=10/9

p = 5/3; p = 2.5/3 = 5/6

4-input NAND footed + Hi INV

g = 5/3; g=5/6

G = (5/3)(5/6) = 25/18

p = 6/3 p = 5/6

P = 6/3 + 5/6 = 17/6

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8-input footed domino AND gate

For H > 2.9 4-stage is better

electrical effort

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Chapter 1:

Chapter 2:

Chapter 3:

Chapter 4:

Chapter 6:

Chapter 7:

Chapter 11:

Flash Memory