Final Design Report_Steven Motes

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ELEC 2210 Final Design Project

Auburn University

Steven Motes

4/22/2012



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Overview

For the final design project, I designed a finite-state machine (FSM) to drive one of two loads (either a fan

or a speaker) based on an entered code. Specifically, a pre-programmed code is entered via the DIO4-DIO7 bits ,

which is compared to the user-inputted code. Assuming the codes match, it drives the ‘good code’ load— a fan.

Otherwise it drives the ‘bad code’ load, a speaker. The overall FSM was divided into four subparts: code input,

driving the fan load, driving the speaker load, and driving a blinking LED during code input. To accomplish this, Iused, in total, seven integrated circuits and two bipolar-junction transistors. The complete list is as follows:

- 74LS164 serial-in shift register with asynchronous, falling-edge triggered reset (x1)

- 74LS161 4-bit binary counter with as ynchronous, falling-edge triggered reset (x1)

- 74LS04 hex inverters (x2)

- 74LS08 quad 2-input AND (x2)

- 74LS86 quad 2-input XOR (x1)

- 2N3904 bipolar junction trans istor (x2)

Code input & compare

The code input section is nothing more than inputting a 4-bit code via the 74164 shift register andcomparing it with the pre-programmed DIO4-DIO7 bits using XOR and AND gates . First, DIO0 is tied to the

asynchronous resets (~CLR) on both the shift register and the binary counter in order to reset the circuit to its initial

state at any time. DIO1 is directly tied to the rising-edge triggered clock on the shift register and also inverted via

one of the hex inverters to drive the falling-edge triggered clock on the counter. DIO2 is tied to inputs A and B of

the shift register to input the code bits, while the clock is toggled to write the bits into the shift register. The counter

inputs A-D are all tied to ground to initialize the count to 0. Note that the shift register and the counter have

synchronized clock signals; therefore, since the code is only 4 bits long, the count output QC (count > 4) is used to

signify a complete code. The diagram of the input circuit is shown in Figure 1, while the code comparison logic is

shown by the diagram and truth table in Figures 2 and 3.

Figure 1: Code input circuit



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Figure 2: Code compare logic diagram

Figure 3: Code compare truth table

QA DIO4 QB DIO5 QC DIO6 QD DIO7 STATUS

1 1 1 1 1 1 1 1 1

1 1 0 1 1 1 1 1 0

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 1 0

0 0 1 1 1 1 0 0 1

1 1 0 0 1 1 1 0 0

Driving the fan/speaker loads

Given the code output bit STATUS and counter output QC (not to be confused with the shift register output

QC) defined in the previous section, they are used to drive both the ‘good’ fan load and the ‘bad’ speaker load. TheSTATUS bit, along with the counter output QC, are directly tied to one 2-IN AND gate for the fan load. Similarly,

the inverted STATUS bit and counter output QC are tied to the 2-IN AND gate for the speaker load. Both of the

AND gates are tied to separate bipolar junction transistors, which act to s witch on the respective loads. Each load is

driven by a waveform generator generating enough voltage to drive each load in series with a 330Ω resistor (5 Vpk

60 Hz was us ed in the in-lab demonstration to drive both loads). A diagram of this subcircuit is shown in Figure 5 on

the next page.

Figure 4: Load state table

QC STATUS LOAD

1 1 Fan

1 0 Speaker

Note that th e status bit is only high when all the underlying

code bits match their respective counterpart:

DIO4 ↔ QA, DIO5 ↔ QB, DIO6 ↔ QC, DIO7 ↔ QD



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Figure 5: Load circuits

Driving the blinking LED

Recall that the counter output QC is high whenever 4 code bits have been entered to the shift register;

therefore, this bit is inverted to also drive the blinking LED, which blinks only during the code input stage. Note that

once QC goes high (all code bits are entered), the blinking stops and one of two loads switch on depending on how

the codes compared. The subcircuit itself is simple — QC is inverted using the 7408 and connected, along with

FGEN (5 Vpk 2 Hz was used in the lab), to a 2-IN AND gate, which drives the LED load in series with a 330Ω

resistor. This, in effect, will caus e the LED to blink twice per second while QC is low (code input is not complete).

A diagram of this circuit is shown in Figure 6 on the next page.

Figure 6: Blinking LED circuit



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FSM function block diagram

Multisim simulation

The entire FSM was tes ted in Multisim to verify the interoperability of eac h subcircuit and the validity of

the des ign operation itself. Simple indicators were used to represent each load (fan, s peaker, and LED). Frequencies

of the waveform generators also do not match the in-lab demonstrations due to how time is handled in Multisim

simulations . The s imulation was wired using the actual IC chips rather than individual gates in order to show the

power supply and ground connections as well as to show the interconnections of each IC and how many of each IC

was used for the overall design. Screenshot shown below in Figure 8:

Figure 8: Multisim simulation screenshot



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Conclusion

Though an extra 7408 and 7404 must be used, the overall des ign only calls for only six ICs total, two

separate waveform generators of different frequencies (2 Hz and 60 Hz), two transistors, and three loads plus

resistors. The FSM was des igned in a highly modularized manner as it was presented in this report itself. Each

subcircuit contains a distinct input, usually related to another subcircuit (ex: QC), which then drives a distinct

output, whether it be an input to another subcircuit or a load itself. In effect, then, the design proves to be organizedand simplistic while meeting all of the project ’s operational requirements .

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Final Design Report_Steven Motes