8/9/2019 FFT64_GN_DT_1_0

1/4

Fast 64-points FFT / IFFT

1/4

1 Features

64-Point complex FFT or IFFT algorithm

Configurable word width (10- to 32-bit words)

Dynamic selection between FFT and IFFT

Dynamic normalization selection

Split-radix FFT algorithm for enhancedperformance

New FFT transform result is available after amaximum of 69 clock cycles resulting in 1.38us@ 50 MHz per FFT operation

Synthesizable and configurable RTL (VHDL)netlist

Support for ASIC and FPGA technology Validated on FPGA @ 16 MHz

Provided with test bench and test vectors

Implemented in standard logic gates only (noRAM)

2 General Description

The Fast Fourier Transform (FFT) core computes a64-point complex forward FFT or inverse FFT (IFFT).Direction of Transform can be selected dynamically.

The input data is a vector of 64 complex elements.Real and imaginary parts of each complex elementare represented as 10- to 32-bit 2s complementnumbers.

The output data as well is a vector of 64 complexelements each of which is represented by two 10- to32-bit 2s complement numbers.

Normalization (division by 64) is selectabledynamically.

The applied algorithms enable the block to computeone FFT / IFFT transform within 64 to 69 clockcycles, depending on the selected word width.

Selecting the word width (prior to synthesis) isbasically a tradeoff between accuracy, transform timeand gate count / power consumption and needs to bedone according to system application.

A number of selected test vectors are provided astest bench. The solution vectors calculated by theFFT block can be compared to solution vectorscalculated by specialized standard software such asMATLAB.

3 Block Diagram

Figure 1: Functional Block Diagram

8/9/2019 FFT64_GN_DT_1_0

2/4

2/4

4 Signal Description

Signal Name Direction Size Active

Description

masterclk Input 1 N.A. Master clock.Note: maximal allowable clock frequency is technology dependent.(Example: With TSMC 0.18 um at 3.3 V, typical process, max frequency is 75MHz)

reset_n Input 1 low Global asynchronous reset.If this signal is set to low an asynchronous global reset is performed.All registers and all output signals are set to zero.

start_fft Input 1 high Start of conversion.If this signal is set to high for at least one clock cycle FFT / IFFToperation will be started. Once start has occurred, this signalbecomes redundant and can be either high or low.

Note: Before start_fft is latched high by a rising edge of masterclk valid datamust be presented to the data inputs. Once start of operation has occurred,input data must remain valid for at least nine clock cycles. After that, input

data becomes redundant and new data may be presented to the data inputs.Note: If this signal is set to high continuously (see Figure 3 restart condition)and input data is presented right in time a continuous conversion mode isreached. In this mode output data will be available after every {64 to 69} + 1clock cycles.Note: To avoid continuous mode operation (see Figure 3 Stopcondition)this signal must be set to low before the trailing edge of signal fft_done.

ifft_mode Input 1 N.A. Operation mode selection.If this signal is set to low FFT operation is performed, if it is set tohigh IFFT operation is performed.

ifft_norm Input 1 high Normalization mode for IFFT.If this signal is set to high normalization is performed on the outputdata. That is to say, all output values are divided by a factor of 64.

Note: When the block performs an FFT conversion (ifft_mode = low) this

signal is redundant and does not affect the operation.x_in[63:0] Input 64 N.A. Real part of complex input vector.

Note: Complex input vector's element n is equal to x_in[n] + j y_in[n].

y_in[63:0] Input 64 N.A. Imaginary part of complex input vector.

fft_done Output 1 high FFT / IFFT operation completed.Once the selected operation (FFT / IFFT) is finished, this signal willbecome high for one clock cycle.

x_out[63:0] Output 64 N.A. Real part of complex output vector.Note: Complex output vector's element n is equal to x_out[n] + j y_out[n].

y_out[63:0] Output 64 N.A. Imaginary part of complex output vector.

Table 1: Signal Description

5 Symbol

Figure 2: Block Symbol

reset_n

start_fft

masterclk

ifft_norm

ifft_mode

FFT

x_out [63:0]

y_out [63:0]

fft_done

Generics:data_size_g

y_in [63:0]

x_in [63:0]

8/9/2019 FFT64_GN_DT_1_0

3/4

3/4

6 Computation Timing

Figure 3 shows the computation timing conditions, which need to be respected in any circumstances.

Figure 3: Computation Timing

7 Theory of Operation

The Discrete Fourier Transform (DFT) formula is:

nkN

n

nk WxX

=

=1

0

withnjn

NNeW2

=

The inverse DFT operation is defined as:

nkN

k

kk WXN

x

=

=1

0

1

8 Data Format

Input and output data vectors consist of 64 fixed-point complex vector elements, each represented bya real part and an imaginary part. The word width of

each of the two values of each vector element can

be configured prior to synthesis using the genericsdata_size_g. Word width may be between 10 and32 bits. Input and output values are represented as2s complement numbers.

Note: It is a matter of interpretation, where to put thedecimal point within the 10- to 32-bit fixed pointinput values.

However, the position of the decimal point in theoutput values is shifted to the right by 6 digitsreferring to the position of the decimal point in theinput values.

This measure does increase accuracy withoutaffecting gate count and transform time.

9 Accuracy

Computation accuracy increases with increasingword width and so does gate count and transformtime. So basically it is a trade off between accuracy,gate count and transform time.

10 Transform Time

As shown in Table 2 transform time depends on theword width used to represent real and imaginaryparts of the elements of input and output vectors.

Wordwidth in

bits

Transformtime inclockcycles

Transformtime @

20MHz inus

10 to 12 64 3.20

13 to 16 65 3.25

17 to 20 66 3.3021 to 24 67 3.35

25 to 28 68 3.40

29 to 32 69 3.45

Table 2: Transform Time

Transform time 64 to 69 cycles

Valid data required 9 Cycles

masterclk

start_fft

fft_done

data

Restart condition

Stop condition

In case of restart

> 1 Cycle

8/9/2019 FFT64_GN_DT_1_0

4/4

4/4

11 Gate Count

As shown in Figure 4 the number of standard logicgates consumed by the block is highly dependent

on the word width used to represent input andoutput data.

30

40

50

60

70

80

90

100

110

120

130

140

150

160

10 12 14 16 18 2 0 2 2 2 4 2 6 2 8 3 0 3 2

Word width in bits

Figure 4: Gate Count vs. Word Width

12 Power Consumption

An increasing number of standard logic cells willresult in increasing power consumption. Hence, asgate count is dependent on word width powerconsumption is too.

Furthermore, power consumption depends on theclock frequency and on the applied technology. Theprovider of the standard cell library and the foundry

will provide numbers for the term Power/Gate/MHz.

13 Test Bench

A number of carefully selected test vectors areprovided as test bench. The solution vectorscalculated by this FFT block can be compared tosolution vectors calculated by specialized standardsoftware such as MATLAB.

14 Deliverables

As part of the License Agreement the components

listed below will be delivered: VHDL Netlist (Verilog TBD)

Test Bench

Datasheet

Synthesis Scripts (Ambit + Synopsys)

15 References

[1] A. V. Oppenheim and R. W. Schafer, Discrete-time signal processing, Prentice-Hall, pp. 514661.

16 Contact

For more details about our products and services,please visit us at www.newlogic.com orwww.wipro.com or contact us at:United StatesWipro Technologies1300, Crittenden Lane2nd Floor, Mountain ViewCA 94043USA

Tel.: +1-650-316 3555Fax: +1-650-316 3468

EuropeNewLogic Technologies(a Wipro Company)Millennium Park 6A 6890 LustenauAustriaTel.: +43-5577 995-0Fax: +43-5577 995-988

JapanWipro Technologies

#911A, Landmark Towers2-1-1, Minatomirai 2-ChomeNishi-Ku, Yokohama 220-8109JapanTel.: +81-45-650 3950Fax: +81-45-650 3951IndiaWipro TechnologiesGanappa Towers53/1, Hosur Main RoadMadiwala, Bangalore 560 068 KarnatakaIndiaTel.: +91-80-550 2001

Information furnished is believed to be accurate and reliable. However, Wipro-NewLogic assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of Wipro-NewLogic. All information issubject to change without notice, 2006 NewLogic, a Wipro Company. Version 1.1, January 2006. All Trademarks are theproperty of their respective owners.

GatecountinK-Gates