FET-Basics-1.ppt

8/10/2019 FET-Basics-1.ppt

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FET ( Field Effect Transistor)

1. Unipolar device i. e. operation depends on only one type ofcharge carriers (hor e)

2. Voltage controlled Device (gate voltage controls draincurrent)

3. Very high input impedance (109-1012 )

4. Source and drain are interchangeable in most Low-frequencyapplications

5. Low Voltage Low Current Operation is possible (Low-powerconsumption)

6. Less Noisy as Compared to BJT7. No minority carrier storage (Turn off is faster)

8. Self limiting device9. Very small in size, occupies very small space in ICs10. Low voltage low current operation is possible in MOSFETS11. Zero temperature drift of out put is possiblek

Few important advantages of FET over conventional Transistors


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Types of Field Effect Transistors(The Classification)

JFET

MOSFET(IGFET)

n-Channel JFET

p-Channel JFET

n-ChannelEMOSFET

p-ChannelEMOSFET

EnhancementMOSFET

DepletionMOSFET

n-ChannelDMOSFET

p-ChannelDMOSFET

FET


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Figure: n-Channel JFET.

The Junction Field Effect Transistor (JFET)


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Gate

Drain

Source

SYMBOLS

n-channel JFET

Gate

Drain

Source

n-channel JFET

Offset-gate symbol

Gate

Drain

Source

p-channel JFET


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Figure: n-Channel JFET and Biasing Circuit.

Biasing the JFET


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Figure: The nonconductive depletion region becomes broader with increased reverse bias.

(Note:The two gate regions of each FET are connected to each other.)

Operation of JFET at Various Gate Bias Potentials


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P P +

-

+

-+

-

N

N

Operation of a JFET

Gate

Drain

Source


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Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.

Non-saturation (Ohmic) Region:

The drain current is given by

2

22

2

DS

DSPGS

P

DSS

DS

V

VVV

V

I

I

2

2 PGS

P

DSS

DSVV

V

I

I

2

1and

P

GS

DSSDS V

V

II

Where,IDSSis the short circuit drain current, VPis the pinch off voltage

Output or Drain (VD-ID) Characteristics of n-JFET

Saturation (or Pinchoff) Region:

PGSDSVVV

PGSDSVVV


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Figure: n-Channel FET for vGS = 0.

Simple Operation and Break down of n-Channel JFET


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Figure: If vDGexceeds the breakdown voltage VB, drain current increases rapidly.

Break Down Region

N-Channel JFET Characteristics and Breakdown


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Figure: Typical drain characteristics of an n-channel JFET.

VD-IDCharacteristics of EMOS FET

Saturation or Pinch

off Reg.

Locus of pts where PGSDS VVV


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Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

2

1

P

GS

DSSDS V

VII

IDSS

VGS (off)=VP

Transfer (Mutual) Characteristics of n-Channel JFET


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JFET Transfer CurveThis graph shows the value of IDfor a given

value of VGS


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Biasing Circuits used for JFET

Fixed bias circuit

Self bias circuit

Potential Divider bias circuit


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JFET (n-channel) Biasing Circuits

2

1

P

GS

DSSDS V

VII

, GGSGSGGGG IFixedVVRIV

DDSDDDS

P

GS

DSSDS

RIVV

V

VII

and

1

2

S

GS

DS

SDSGS

R

VI

RIV

0

For Self Bias Circuit

For Fixed Bias Circuit

Applying KVL to gate circuit we get

and

Where, Vp=VGS-off& IDSSis Short ckt. IDS


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JFET BiasingCircuits Count

or Fixed Bias Ckt.


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JFET Self (or Source) Bias Circuit

2

1and

P

GS

DSSDS V

V

II

S

GS

P

GS

DSS R

V

V

V

I

2

1

021

2

S

GS

P

GS

P

GS

DSS R

V

V

V

V

VI

This quadratic equation can be solved for VGS& IDS


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The Potential (Voltage) Divider Bias

01

2

S

GSG

P

GS

DSS R

VV

V

V

I

DSGS

IVgivesequationquadraticthisSolving and


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A Simple CS Amplifier and Variation in IDSwith Vgs


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FET Mid-frequency Analysis:

g

s

rdgmvpvi = vp

iiio

vo

d

s

+ +

_ _

mid-frequency CE amplifier circuit

RD RLRThvs

+

_

is

' 'o o ivi m L L d D L vs vi

i s s i

ii Th Th 1 2

i

Analysis of the CS mid-frequency circuit above yields:v v Z

A = = -g R , where R = r R R A = = Av v R + Z

vZ = = R , where R = R R

i

L

o iI vi

i L

o oo d D P vi I

o iseen by R

i Z A = = A

i R

v pZ = = r R A = = A A

i p

A common source (CS) amplifier is shown

to the right.

Rs CiRL

Co

CSSvi

vo+

+

vs

+

__

_

io

ii

D

S

G

VDD VDD

R1

RSS

RD

R2

The mid-frequency circuit is drawn as follows: the coupling capacitors (Ciand Co) and the

bypass capacitor (CSS) are short circuits

short the DC supply voltage (superposition)

replace the FET with the hybrid-pmodel

The resulting mid-frequency circuit is shown below.


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FET Mid-frequency Analysis:

g

s

rdgmvpvi = vp

iiio

vo

d

s

+ +

_ _

mid-frequency CE amplifier circuit

RD RLRThvs

+

_

is

' 'o o ivi m L L d D L vs vi

i s s i

ii Th Th 1 2

i

Analysis of the CS mid-frequency circuit above yields:

v v ZA = = -g R , where R = r R R A = = A

v v R + Z

vZ = = R , where R = R R

i

L

o iI vi

i L

o oo d D P vi I

o iseen by R

i Z A = = A

i R

v pZ = = r R A = = A A

i p

A common source (CS) amplifier is shown

to the right.

Rs CiRL

Co

CSSvi

vo+

+

vs

+

__

_

io

ii

D

S

G

VDD VDD

R1

RSS

RD

R2

The mid-frequency circuit is drawn as follows:

the coupling capacitors (Ciand Co) and the

bypass capacitor (CSS) are short circuits

short the DC supply voltage (superposition)

replace the FET with the hybrid-pmodel

The resulting mid-frequency circuit is shown below.


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Procedure: Analysis of an FET amplifier at mid-frequency:

1) Find the DC Q-point. This will insure that the FET is operating in the saturation

region and these values are needed for the next step.2) Find gm. If gmis not specified, calculate it using the DC values of VGSas follows:

3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for

the appropriate amplifier configuration (CS, CG, CD, etc).

DSSDm GS P2

GS P

Dm GS T

GS

GS

2IIg = = V - V (for JFET's and DM MOSFET's)

V V

Ig = = V - V (for EM MOSFET's)

V

(Note: Uses DC value of V )

K


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PE-Electrical Review Course - Class 4 (Transistors)

Example 7:

Find the mid-frequency values for Avi, Avs, AI, AP, Zi,

and Zofor the amplifier shown below. Assume that

Ci, Co, and CSSare large.

Note that this is the same biasing circuit used in Ex. 2,

so VGS= -0.178 V.

The JFET has the following specifications:

DSS= 4 mA, VP= -1.46 V, rd= 50 k

10 kCi

8 k

Co

CSSvi

vo+

+

vs

+

__

_

io

ii

D

S

G

18 V 18 V

800 k

2 k

500

400 k


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FET Amplifier Configurations and

Relationships:

'

' ' m Lvi m L m L '

m L

'

L d D L d D L SS L

i Th SS Th

m

o d D d D SS

m

i i ivs vi vi vi

s i s i s i

i i iI vi vi vi

L L L

P vi I vi I

CS CG CD

g RA -g R g R 1 g R

R r R R r R R R R

1Z R R R

g

1Z r R r R R g

Z Z ZA A A A

R + Z R + Z R + Z

Z Z ZA A A A

R R RA A A A A

vi I

Th 1 2

A A

where R = R R

VCC

RD

S

R2

RSS

RsCi

RL

Co

C2

vi vo

+

+

vs

+

___

ioii

Common Gate (CG) Amplifier

R1

D

G

Note: The biasing circuit is the same for each amp.

RsCi RL

Co

CSSvi

vo+

+

vs

+

__

_

io

ii

D

S

G

VDD VDD

R1

RSS

RD

R2

Common Source (CS) Amplifier

Rs C i

vi

+

vs

+

_

_

ii G

VDD VDD

R1

RSS

R2

Common Drain (CD) Amplifier (also called source follower)

RL

C o

vo

+

_

io

D

S


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Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.


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Figure: n-Channel Enhancement MOSFET showing channel lengthLand channel width W.


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Figure: For vGS< Vtothepnjunction between drain and body is reverse biased and iD=0.


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Figure: For vGS>Vtoa channel of n-type material is induced in the region under the gate.

As vGSincreases, the channel becomes thicker. For small values of vDS,iDis proportional to vDS.The device behaves as a resistor whose value depends on vGS.


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Figure: As vDSincreases, the channel pinches down at the drain end and iDincreases more slowly.

Finally for vDS> vGS -Vto, iDbecomes constant.


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Current-Voltage Relationship of

n-EMOSFET

Locus of points where


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Figure: Drain characteristics


32/63

Figure: This circuit can be used to plot drain characteristics.


33/63

Figure: Diodes protect the oxide layer from destruction by static electric charge.


34/63

Figure: Simple NMOS amplifier circuit and Characteristics with load line.


35/63

Figure: Drain characteristics and load line


36/63

Figure vDSversus time for the circuit of Figure 5.13.


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Figure Fixed- plus self-bias circuit.


38/63

Figure Graphical solution of Equations (5.17) and (5.18).


39/63

Figure Fixed- plus self-biased circuit of Example 5.3.


40/63

Figure The more nearly horizontal bias line results in less change in the Q-point.


41/63

Figure Small-signal equivalent circuit for FETs.


42/63

Figure FET small-signal equivalent circuit that accounts for the dependence of iDon vDS.


43/63

Figure Determination ofgmand rd. See Example 5.5.


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Figure Common-source amplifier.


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For drawing an a c equivalent circuit of Amp.

Assume all Capacitors C1, C2, Cs as shortcircuit elements for ac signal

Short circuit the d c supply

Replace the FET by its small signal model

Analysis of CS Amplifier


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Analysis of CS Amplifier

LgsmLoo

gs

o

v

RvgRiv

v

vA

gain,Voltage

dDLLmgs

o

vrRRRg

v

vA ,

Dd

Dd

Ddo Rr

RrRrZ

imp.,putOut

21imp.,Input RRRZ

Gin

A C Equivalent Circuit

Simplified A C Equivalent Circuit

Analysis of CS Amplifier with Potential Divider Bias


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Analysis of CS Amplifier with Potential Divider Bias

)R||(rgAv Ddm

DR10rD,m

dRgAv

)R||(rgAv Ddm

This is a CS amplifier configuration therefore the

input is on the gate and the output is on the drain. 21 R||RZi

Dd R||rZo

DdD

10RrRZo


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Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.

A A lifi Ci it i MOSFET(CS A )


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Figure Common-source amplifier.

An Amplifier Circuit using MOSFET(CS Amp.)


50/63

Figure Small-signal equivalent circuit for the common-source amplifier.

A small signal equivalent circuit of CS Amp.


51/63

Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.


52/63

Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.


53/63

Figure Source follower.


54/63

Figure Small-signal ac equivalent circuit for the source follower.


55/63

Figure Equivalent circuit used to find the output resistance of the source follower.


56/63

Figure Common-gate amplifier.


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Figure See Exercise 5.12.


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Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.


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Figure n-Channel depletion MOSFET.


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Figure Characteristic curves for an NMOS transistor.


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Figure Drain current versus vGSin the saturation region for n-channel devices.


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Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,

except for the directions of the arrowheads.


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Figure Drain current versus vGSfor several types of FETs. iDis referenced into the drain terminal

for n-channel devices and out of the drain forp-channel devices.

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FET-Basics-1.ppt