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FAC. Fast Access Controller in FLASH in-system programming. Shahar Ben-Yehuda. What is FLASH memory?. FLASH memory is used (also) in processors Has two standards: NOR and NAND It substitutes pre-programmed memory hardware PCB’s may have many FLASH devices - PowerPoint PPT Presentation
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Fast Access Controller
in FLASH in-system programming
Fast Access Controller
in FLASH in-system programming
Shahar Ben-Yehuda
What is FLASH memory? What is FLASH memory?
• FLASH memory is used (also) in processors
• Has two standards: NOR and NAND
• It substitutes pre-programmed memory hardware
• PCB’s may have many FLASH devices
• It stores the system’s firmware (program code)
• It can be changed and updated
• Bug fixes can be made easily with it
Traditional FLASHprogramming methods
Traditional FLASHprogramming methods
Gang & In-LineFlash programmers
Emulation based Flash Programming
ICTFlash Programming
Flash Programming with Boundary-Scan
Flash Programming with Boundary-Scan
Traditional FLASHprogramming methods
Traditional FLASHprogramming methods
Boundary Scan disadvantagesBoundary Scan disadvantages
• Today’s Boundary-scan devices have a large Pin-count
• More and more Boundary-scan devices are needed in each PCB
• The length of the scan path becomes a major limiting factor
• Programming a FLASH take 10s of minutes
• We can improve that only by half
The SolutionThe Solution
• InfraStructure IP Block• InfraStructure IP Block
• Uses IEEE-1149.1 Standard for Bounary-Scan• Uses IEEE-1149.1 Standard for Bounary-Scan
• Used for FLASH programming and in-system testing• Used for FLASH programming and in-system testing
• Can achieve optimal throughput even in lower TCK’s• Can achieve optimal throughput even in lower TCK’s
• Not affected by the scan length or the number of JTag devices• Not affected by the scan length or the number of JTag devices
• Can be used in many memory types: NOR & NAND FLASH EEPROM, serial EEPROM, SRAM, SDRAM, DDRAM etc.• Can be used in many memory types: NOR & NAND FLASH EEPROM, serial EEPROM, SRAM, SDRAM, DDRAM etc.
• Implemented in a CPU or ASIC• Implemented in a CPU or ASIC
FPGA
FAC ArchitectureFAC Architecture
TD
OT
MS
TC
KT
DI
TD
OT
MS
TC
KT
DISysCLK(s)SysCLK(s)
State diagram of the FSMState diagram of the FSMPP
FAC Block-DiagramFAC Block-DiagramThe PFSM is
connected also to the bypass register and
the BSR
The PFSM is connected also to the bypass register and
the BSR
Each of the blocks has one or more
Data Registers
Each of the blocks has one or more
Data Registers
These DRs may be used with the FAC,or can be shared by
the BSR
These DRs may be used with the FAC,or can be shared by
the BSR
The Blocks receive control input from the
PFSM and the IR
The Blocks receive control input from the
PFSM and the IR
The PCS provides theFLASH’s Control
signals via the test multiplexors
The PCS provides theFLASH’s Control
signals via the test multiplexors
The IR and the PFSM will control the PCS to
work using their current instructions
The IR and the PFSM will control the PCS to
work using their current instructions
It also interfaces the other blocks of the
FAC to sequence them for accessing the
FLASH
It also interfaces the other blocks of the
FAC to sequence them for accessing the
FLASH
The FAC logic can besynchronized with
either the TCK clock or system clocks
The FAC logic can besynchronized with
either the TCK clock or system clocks
The AG logic outputs address sequences onto the FLASH’s
Address bus
The AG logic outputs address sequences onto the FLASH’s
Address bus
The AG may contain one or more address
generation circuits
The AG may contain one or more address
generation circuits
The AG sequencesare controlled by
specific instructions from the PFSM & PCS
The AG sequencesare controlled by
specific instructions from the PFSM & PCS
The DATA register is a simple DR
The DATA register is a simple DR
It is used to keepdata to be written to the memory, or data that has been read from the memory
It is used to keepdata to be written to the memory, or data that has been read from the memory
The DATA and PDS logic are used for
read/write operations, and special data
sequences, to/from the FLASH device
The DATA and PDS logic are used for
read/write operations, and special data
sequences, to/from the FLASH device
The DATA DR is separated from
the PDS DR, so it could be scanned while the PDS is outputting data
The DATA DR is separated from
the PDS DR, so it could be scanned while the PDS is outputting data
The PDS isprogrammed with data sequences required for
the FLASH’s program/erase
commands
The PDS isprogrammed with data sequences required for
the FLASH’s program/erase
commands
As a result, concurrent writing and reading of
data can be done
As a result, concurrent writing and reading of
data can be done
Performance Example:Performance Example:
The PCB containing the FLASH and IC with Boundary Scan requires 736 BSR cells in the 1149.1 chain in order to access the FLASH device.
• The TCK clock rate is 10MHz.
• It takes 19 scan operations to program 1 buffer of 16 words.
The PCB containing the FLASH and IC with Boundary Scan requires 736 BSR cells in the 1149.1 chain in order to access the FLASH device.
• The TCK clock rate is 10MHz.
• It takes 19 scan operations to program 1 buffer of 16 words.
Boundary scan in EXTEST:Boundary scan in EXTEST:
128Mbits of Intel StaraFLASH memory, with a 16 bit data bus and 8M addresses.
The typical burn time is 218us per buffer (16 words),
512k (524,288) buffer writes are required to program the entire 128Mbit FLASH.
128Mbits of Intel StaraFLASH memory, with a 16 bit data bus and 8M addresses.
The typical burn time is 218us per buffer (16 words),
512k (524,288) buffer writes are required to program the entire 128Mbit FLASH.
Boundary scan in EXTEST:Boundary scan in EXTEST:• Time for 1 buffer = #BSR cells * #scans = 736 * 19 = 1.4ms TCK 10us
• Time for entire FLASH = buffer time * #buffers = 1.4ms * 524,288 = 734 secs
• Time for 1 buffer = #BSR cells * #scans = 736 * 19 = 1.4ms TCK 10us
• Time for entire FLASH = buffer time * #buffers = 1.4ms * 524,288 = 734 secs
This doesn’t include the device burn time, which can add up to 114 second to the entire FLASH!!!This doesn’t include the device burn time, which can add up to 114 second to the entire FLASH!!!
What) The FAC: (What) The FAC: (• scan length is 16 data bits * 16 words, or 256 bits long
• Only one scan is required to write a Buffer
• Each buffer write takes two TCK cycles because of the APG2_DR and the update/capture2_DR
• scan length is 16 data bits * 16 words, or 256 bits long
• Only one scan is required to write a Buffer
• Each buffer write takes two TCK cycles because of the APG2_DR and the update/capture2_DR
• Time for 1 buffer = #BSR cells * #scans = 258 * 1 = 25.8us TCK 10us
• Time for entire FLASH = buffer time * #buffers = 25.8us * 524,288 = 13.5 secs
• Time for 1 buffer = #BSR cells * #scans = 258 * 1 = 25.8us TCK 10us
• Time for entire FLASH = buffer time * #buffers = 25.8us * 524,288 = 13.5 secs
• Shifting of next data and ‘burn time’ of current data can occur concurrently, burn time is bigger.
• Burn time is typically 218us per Buffer
• Multiplying it by 524,288 gives: approximately 114 seconds…
• Shifting of next data and ‘burn time’ of current data can occur concurrently, burn time is bigger.
• Burn time is typically 218us per Buffer
• Multiplying it by 524,288 gives: approximately 114 seconds…
What) The FAC: (What) The FAC: (
ConclusionConclusion
• FAC gives a good solution for programming external FLASH in a production environment• FAC gives a good solution for programming external FLASH in a production environment
• It’s flexible and can be used even if we don’t know how our BS chain will look like, and which memory we’ll use• It’s flexible and can be used even if we don’t know how our BS chain will look like, and which memory we’ll use
•It’s fast as the Off-board methods and also as the Complex Direct Access method•It’s fast as the Off-board methods and also as the Complex Direct Access method
•It’s faster than any other in-system method•It’s faster than any other in-system method
• This method will be even faster when the FLASH memory’s “Burn time” will improve• This method will be even faster when the FLASH memory’s “Burn time” will improve
ReferencesReferences
• http://www.cs.huji.ac.il/~dft/Course outline/Course outline.html
• http://www.asset-intertech.com/jtag_scanworks.html
•http://www.fairchildsemi.com/an/AN/AN-890.pdf
• http://www.intellitech.com/products/fac.asp
• http://www.intellitech.com/technologies/infrastructureip.asp
• CJ Clark, Mike Ricchetti, “Infrastructure IP for Configuration and Test of Boards and Systems”, IEEE Design & Test of Computers, vol. 20, no. 3, May-June
• CJ Clark, Mike Ricchetti, “A Fast Access Controller for In-System Programming of FLASH Memory Devices”
• http://www.cs.huji.ac.il/~dft/Course outline/Course outline.html
• http://www.asset-intertech.com/jtag_scanworks.html
•http://www.fairchildsemi.com/an/AN/AN-890.pdf
• http://www.intellitech.com/products/fac.asp
• http://www.intellitech.com/technologies/infrastructureip.asp
• CJ Clark, Mike Ricchetti, “Infrastructure IP for Configuration and Test of Boards and Systems”, IEEE Design & Test of Computers, vol. 20, no. 3, May-June
• CJ Clark, Mike Ricchetti, “A Fast Access Controller for In-System Programming of FLASH Memory Devices”