Fall 08, Oct 31ELEC2200-002 Lecture 8 (Updated) 1 Lecture 8: Design, Simulation Synthesis and Test Tools ELEC 2200: Digital Logic Circuits Nitin Yogi ([email protected])[email protected]

Fall 08, Oct 31 ELEC2200-002 Lecture 8 (Updated) 1

Lecture 8: Design, Simulation Synthesis and Test Tools

ELEC 2200: Digital Logic CircuitsNitin Yogi ([email protected])


X-Win32

X-Win32 is used to log into UNIX session

Use Windows Auburn login and password to log into X-Win32 session.


Start X-Win32 from here


Windows Security Alert Warning

If Windows Security Alert window pops up, press OK


You might also get this screenDouble click on “Scan for Unix/Linux hosts”

Click on any of the server names and click on “Select”


You might also get this screen

Click “OK”


X-Win32 Login Screen


UNIX session

Setup the softwares required to run the tools for simulation, synthesis and test

At the command prompt type the following command and hit “Enter”>> user-setup

Command prompt to type commands in


User Setup screen

Click on button “Electronics Data Analysis (EDA)”


1. Go to the bottom of the option screen

2. Click on the following software packages:eda/Modelsim/6.4eda/ICFlow/2006.1eda/DFT/2006.3

3. Click the X button on the top right


Click on “Save and Quit”


Press “Commit Changes”

The Added modules will be displayed here


X-Win32 reset

Exit X-Win32 and restart the X-Win32 session again as described earlier


UNIX environment

When you log-in into X-Win32, the current default directory is the H: of windows system

Some useful UNIX commands >> cd <directory_name>: change directory >> cd .. : go up one directory >> ls: list contents of directory >> pwd: display the full path of the current dir. >> mkdir: create directory


Setting the simulation environment In the current default directory, create another

directory for your designs by using the mkdir command. Ex. >> mkdir my_name Do not use spaces while giving names as it may create

problems in UNIX This new directory can be accessed in windows in H drive

Ex. by accessing H:\my_name Change to this new directory using the cd command

Ex. >> cd my_name In the current design directory (ex. my_name) run the

following commands: >> vlib work >> vmap work work


Example VHDL codelibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;

entity my_ckt is port ( A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit );end my_ckt ;

architecture behav_seq of my_ckt issignal Xtmp: bit;begin p1: process (A,B,S,Xtmp)

begin if (S=‘0’) then Xtmp <= A; else Xtmp <= B; end if;

if ((Xtmp = ‘0’) and (S = ‘0’)) then Y <= ‘1’; else Y <= ‘0’; end if; X <= Xtmp; end process p1;

end;

Need to add this for compiling


Designing, compiling and simulating designs Write VHDL description in any text editor (notepad,

wordpad) and save the file as *.vhd

To simulate any design, you need to compile your design first. Compile your VHDL design using the command:>> vcom <VHDL filename>e.g.>> vcom my_ckt.vhd

We shall use the tool ModelSim for simulating the designTo invoke ModelSim, use the following command:>> vsim <design_name>e.g.>> vsim my_ckt



1. Click on “View > List” to select it (displayed as a tick)

2. Click on “View > Objects” to select it (displayed as a tick)



1. Select the input and output signals by clicking and holding the CTRL key

2. Click “Edit > Copy”


Click on the list window and then click “Edit > Paste”



Right click the input signal name and then click Force


Enter the value of the signal over here and then click OK

If the signal is of type bit_vector you will assign binary values here. Ex. “010” for a signal of type bit_vector(2 downto 0)


To simulate, click Simulate > Run > Run 100




Click on the list window then on File > Export > Tabular list



Useful resource

VHDL Design and Simulation using ModelSim http://www.eng.auburn.edu/department/

ee/mgc/quickvhdl/modelsim.html


Synthesis

We shall use the tool Leonardo to synthesize the behavioral description into structural level netlist

Command to invoke Leonardo is:>> leonardo


Click on LeonardoSpectrum Level 3 and then click OK


1. Click on Advanced FlowTabs

2. Under the “Technology” tab, click on the ASIC plus sign


Click ADK then TSMC 0.18 micron (typ), then click on “Load Library”


Click the “Input” tab and then the button besides “Open files”


Select the required VHDL file and click “Open”


Current selected designs will be displayed in this list

Click on the “Read” button to read the current selected VHDL design(s) into the tool


2. Click the type of optimization: area or delay

3. Click “Optimize”

1. Click on “Optimize” tab


1. Click on “Report” tab

2. Click on “Report Area”


1. Select the report being displayed

2. Select Edit > Copy to copy the report. This can then be pasted in MS Word




Click on the “Report Delay” tab and then on the button “Report Delay”





1. Select “Output” tab

2. Select the Verilog option in the Format menu and enter a name for the output netlist file (*.v)

3. Click “Write”


Changes in design performed by Synthesis tool Leonardo

Data-type changes Integer data type in behavioral design is mapped

to bit_vector data type (array of bits) in structural design Ex. a signal A of integer data type of range -27 to

+27-1 defined in the behavioral design is mapped/changed to a data type bit_vector(0 to 7)

Enumerated / User-defined data types are encoded as binary numbers Ex. A signal of type temperature with values

(high, medium, low) defined at the behavioral level may be encoded as (00, 01, 11) at the structural level


Preparing for simulation of netlist The netlist saved from Leonardo is in Verilog format

(and not VHDL) You need to compile your verilog netlist to simulate it Before you compile your verilog netlist, you need to

compile all the gate designs that your netlist uses. The gate designs are in a file named adk.vhd at the

location $ADK/technology To compile the gate designs, type the following

command in your current working directory at the command prompt: >> vcom $ADK/technology/adk.vhd -work ./work/


Simulation of netlist You need to compile your verilog netlist in

order to simulate it. Command to compile Verilog netlist:

>> vlog <Verilog file_name>e.g. >> vlog my_ckt.v

Simulate the design using ModelSim Command to invoke ModelSim:

>> vsim <design_name>e.g.>> vsim my_ckt



Test generation

We shall use the tool FlexTest to generate test vectors for the netlist

Command to invoke FlexTest:>> flextest


1. Select the output netlist file generated by Leonardo using the Browse button

2. Click on the “Browse” button to select the ATPG Library


1. Select the file adk.atpg in the directory /opt/ADK3.1/technology/and then click OK


Invoke FlexTest


Click on “Done With Setup”


Click on “Pattern Generation”


Click on “Fault Universe”


Click on “Typical”


Click on “Pattern Source”


Click on “Typical”


Click on “Test Generation”


Click on “Run with Existing Settings”


Click on “Save Patterns”



1. Check “Save the Pattern Set to a File” 2. Enter a

filename for the test vector file

3. Click OK


Opening the pattern file saved

You can open the pattern file you just saved in the windows environment using any text editor (notepad, wordpad, Word,etc.)

The pattern file you saved will be in your current working design directory e.g. H:\my_name\

Next slide shows the pattern file


Total no. of faults

Fault Coverage

Total no. of test cycles (vectors)

User CPU time

Documents

Fall 08, Oct 31ELEC2200-002 Lecture 8 (Updated) 1 Lecture 8: Design, Simulation Synthesis and Test Tools ELEC 2200: Digital Logic Circuits Nitin Yogi ([email protected])[email protected]