eZdspTM F2812 - C2000 DSP Development Toolsc2000.spectrumdigital.com/ezf2812/docs/ezf2812_techref.pdf · 2004-11-17 · About This Manual This document describes board level operations

eZdspTM F2812

2003 DSP Development Systems

ReferenceTechnical

eZdspTM F2812 Technical Reference

506265-0001 Rev. FSeptember 2003

SPECTRUM DIGITAL, INC.12502 Exchange Dr., Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware, products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user, at his own expense, will be required to take any measures necessary to correct this interference.

TRADEMARKS

eZdsp is a trademark of Spectrum Digital, Inc.

Copyright © 2003 Spectrum Digital, Inc.

Contents

1 Introduction to the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides a description of the eZdspTM F2812, key features, and board outline.

1.0 Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1 Key Features of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Functional Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2 Operation of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the eZdspTM F2812. Information is provided on the DSK’s various interfaces.

2.0 The eZdspTM F2812 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1 The eZdspTM F2812 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 eZdspTM F2812 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 eZdspTM F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.3 P3, Parallel Port/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.4 P4,P8,P7, I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.5 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.6 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.7 Connector Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4 eZdspTM F2812 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.1 JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.4.2 JP4, JP5, Voltage Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.4.2.1 JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.4.2.2 JP5, +3.3/5 Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.4.4 JP9, PLL Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

A eZdspTM F2812 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the socketed and unsocketed versions of the eZdspTM F2812

B eZdspTM F2812 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the socketed and unsocketed versions of the eZdspTM

F2812

List of Figures

Figure 1-1, Block Diagram eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 2-1, eZdspTM F2812 PCB Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2, eZdspTM F2812 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-3, eZdspTM F2812 Connector Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Figure 2-4, Connector P1 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Figure 2-5, Connector P2 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Figure 2-6, Connector P4/P8/P7 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Figure 2-7, Connector P5/P9 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Figure 2-8, Connector P6 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Figure 2-9, eZdspTM F2812 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Figure 2-10, eZdspTM F2812 Jumper Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Figure 2-11, eZdspTM F2812 Voltage Jumper Positions(Bottom side) . . . . . . . . . . . . . . 2-16

List of Tables

Table 2-1, External Chip Select and Usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Table 2-2, eZdspTM F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Table 2-3, P1, JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Table 2-4, P2, Expansion Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Table 2-5, P4/P8, I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Table 2-6, P7, I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Table 2-7, P5/P9, Analog Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Table 2-8, Connector Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-9, eZdspTM F2812 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Table 2-10, JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Table 2-11, JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Table 2-12, JP5, +3.3/ Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Table 2-13, JP7,JP8, JP11, JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Table 2-14, JP9, PLL Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Table 2-15, LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Table 2-16, Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

About This Manual

This document describes board level operations of the eZdspTM F2812 based on theTexas Instruments TMS320F2812 Digital Signal Processor.

The eZdspTM F2812 is a stand-alone module permitting engineers and softwaredevelopers evaluation of certain characteristics of the TMS320F2812 DSP todetermine processor applicability to design requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The “eZdspTM F2812” will sometimes be referred to as the “eZdsp”.

“eZdsp” will include the socketed or unsocket version

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide,literature #SPRU430

Texas Instruments TMS320C28x Assembly Language Tools Users Guide, literature #SPRU513

Texas Instruments TMS320C28x Optimizing C/C++ Compiler User’s Guide,literature #SPRU514

Texas Instruments Code Composer Studio Getting Started Guide,literature #SPRU509

1-1

Chapter 1

Introduction to the eZdspTM F2812

This chapter provides a description of the eZdspTM for the TMS320F2812Digital Signal Processor, key features, and block diagram of the circuit board.

Topic Page

1.0 Overview of the eZdspTM F2812 1-21.1 Key Features of the eZdspTM F2812 1-21.2 Functional Overview of the eZdspTM F2812 1-3

Spectrum Digital, Inc

1-2 eZdspTM F2812 Technical Reference

1.0 Overview of the eZdspTM F2812

The eZdspTM F2812 is a stand-alone card--allowing evaluators to examine theTMS320F2812 digital signal processor (DSP) to determine if it meets their applicationrequirements. Furthermore, the module is an excellent platform to develop and runsoftware for the TMS320F2812 processor.

The eZdspTM F2812 is shipped with a TMS320F2812 DSP. The eZdspTM F2812allows full speed verification of F2812 code. Two expansion connectors are providedfor any necessary evaluation circuitry not provided on the as shipped configuration.

To simplify code development and shorten debugging time, a C2000 Tools CodeComposer driver is provided. In addition, an onboard JTAG connector providesinterface to emulators, operating with other debuggers to provide assembly languageand ‘C’ high level language debug.

1.1 Key Features of the eZdspTM F2812

The eZdspTM F2812 has the following features:

• TMS320F2812 Digital Signal Processor

• 150 MIPS operating speed

• 18K words on-chip RAM

• 128K words on-chip Flash memory

• 64K words off-chip SRAM memory

• 30 MHz. clock

• 2 Expansion Connectors (analog, I/O)

• Onboard IEEE 1149.1 JTAG Controller

• 5-volt only operation with supplied AC adapter

• TI F28xx Code Composer Studio tools driver

• On board IEEE 1149.1 JTAG emulation connector


1-3

1.2 Functional Overview of the eZdspTM F2812

Figure 1-1 shows a block diagram of the basic configuration for the eZdspTM F2812.The major interfaces of the eZdsp are the JTAG interface, and expansion interface.

TMS320F28xx

ANALOG TODIGITAL

CONVERTER

PARALLEL

Figure 1-1, BLOCK DIAGRAM eZdspTM F2812

ANALOG

EXPANSION

I/O

EXPANSION

JTAGPORT/JTAGCONTROLLER

PARALLEL

PORT EXTERNAL

JTAG

30 Mhz. XTAL1/OSCIN

64K x 16SRAM

XZCS6AND7n



2-1

Chapter 2

Operation of the eZdspTM F2812

This chapter describes the operation of the eZdspTM F2812, keyinterfaces and includes a circuit board outline.

Topic Page

2.0 The eZdspTM F2812 Operation 2-22.1 The eZdspTM F2812 Board 2-22.1.1 Power Connector 2-32.2 eZdspTM F2812 Memory 2-32.2.1 Memory Map 2-42.3 eZdspTM F2812 Connectors 2-52.3.1 P1, JTAG Interface 2-62.3.2 P2, Expansion Interface 2-72.3.3 P3, Parallel Port/JTAG Interface 2-92.3.4 P4,P8,P7, I/O Interface 2-92.3.5 P5,P9, Analog Interface 2-112.3.6 P6, Power Connector 2-132.3.7 Connector Part Numbers 2-142.4 eZdspTM F2812 Jumpers 2-142.4.1 JP1, XMP/MCn Select 2-152.4.2 JP4, JP5 Voltage Jumpers 2-162.4.2.1 JP4, +3.3/5 Volts for P8, P4 2-172.4.2.2 JP5, +3.3/5 Volts for P2 2-172.4.3 JP7,JP8,JP11,JP12, Boot Mode Select 2-182.4.4 JP9, PLL Disable 2-182.5 LEDs 2-192.6 Test Points 2-19



2.0 The eZdspTM F2812 Operation

This chapter describes the eZdspTM F2812, key components, and operation.

Information on the eZdsp’s various interfaces is also included. The eZdspTM F2812consists of four major blocks of logic:

• Analog Interface Connector• I/O Interface Connector• JTAG Interface • Parallel Port JTAG Controller Interface

2.1 The eZdspTM F2812 Board

The eZdspTM F2812 is a 5.25 x 3.0 inch, multi-layered printed circuit board, poweredby an external 5-Volt only power supply. Figure 2-1 shows the layout of both thesocketed and unsocketed version of the F2812 eZdsp.

Figure 2-1, eZdspTM F2812 PCB Outline


2-3

2.1.1 Power Connector

The eZdspTM F2812 is powered by a 5-Volt only power supply, included with theunit. The unit requires 500mA. The power is supplied via connector P6. If expansionboards are connected to the eZdsp, a higher amperage power supply may benecessary. Section 2.3.6 provides more information on connector P6.

2.2 eZdspTM F2812 Memory

The eZdsp includes the following on-chip memory:

• 128K x 16 Flash• 2 blocks of 4K x 16 single access RAM (SARAM)• 1 block of 8K x 16 SARAM• 2 blocks of 1K x 16 SARAM

In addition 64K x 16 off-chip SRAM is provided. The processor on the eZdsp can beconfigured for boot-loader mode or non-boot-loader mode.

The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For largersoftware projects it is suggested to do a initial debug with on eZdsp F2812 modulewhich supports a total RAM environment. With careful attention to the I/O mapping inthe software the application code can easily be ported to the F2812.

The table below shows the external chip select signal and its use.

Table 1: External Chip Select and Usage

Chip Select Signal

Use

XZCS0AND1n Expansion header

XZCS2n Expansion Header

XZCS6AND7n External SRAM



2.2.1 Memory Map

The figure below shows the memory map configuration on the eZdspTM F2812.

Note: The on-chip flash memory has a security key which can prevent visibility whenenabled.

Figure 2-2, eZdspTM F2812 Memory Space


2-5

2.3 eZdspTM F2812 Connectors

The eZdspTM F2812 has five connectors. Pin 1 of each connector is identified by asquare solder pad. The function of each connector is shown in the table below:

The diagram below shows the position of each connector

Table 2: eZdspTM F2812 Connectors

Connector Function

P1 JTAG Interface

P2 Expansion

P3 Parallel Port/JTAG Controller Interface

P4/P8/P7 I/O Interface

P5/P9 Analog Interface

P6 Power Connector

Figure 2-3, eZdspTM F2812 Connector Positions

P1

P5/P9

P3

P2

P6

P4/P8/P7



2.3.1 P1, JTAG Interface

The eZdspTM F2812 is supplied with a 14-pin header interface, P1. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.

The positions of the 14 pins on the P1 connector are shown in the diagram below asviewed from the top of the eZdsp.

The definition of P1, which has the JTAG signals is shown below.

Table 3: P1, JTAG Interface Connector

Pin # Signal Pin # Signal

1 TMS 2 TRST-

3 TDI 4 GND

5 PD (+5V) 6 no pin

7 TDO 8 GND

9 TCK-RET 10 GND

11 TCK 12 GND

13 EMU0 14 EMU1

Fig 2-4, P1 Pin Locations

1

2

P1

JTAG

1

2

3

4

57

8

9

10

11

12

13

14


2-7

2.3.2 P2, Expansion Interface

The positions of the 60 pins on the P2 connector are shown in the diagram below asviewed from the top of the eZdsp.

WARNING !The TMS320F2812 supports +3.3V Input/Output levelswhich are NOT +5V tolerant. Connecting the eZdsp toa system with +5V Input/Output levels will damage theTMS320F2812. If the eZdsp is connected to anothertarget then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

P2

Figure 2-5, Connector P2 Pin Locations

39

40

15

16

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60



The definition of P2, which has the I/O signal interface is shown below.

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JP5.

Table 4: P2, Expansion Interface Connector

Pin # Signal Pin # Signal

1 +3.3V/+5V/NC * 2 +3.3/+5V/NC *

3 XD0 4 XD1

5 XD2 6 XD3

7 XD4 8 XD5

9 XD6 10 XD7

11 XD8 12 XD9

13 XD10 14 XD11

15 XD12 16 XD13

17 XD14 18 XD15

19 XA0 20 XA1

21 XA2 22 XA3

23 XA4 24 XA5

25 XA6 26 XA7

27 XA8 28 XA9

29 XA10 30 XA11

31 XA12 32 XA13

33 XA14 34 XA15

35 GND 36 GND

37 XZCS0AND1n 38 XZCS2n

39 XREADY 40 10K Pull-up

41 XRnW 42 10K Pull-up

43 XWE 44 XRDn

45 +3.3V 46 XNMI/INT13

47 XRSn/RSn 48 No connect

49 GND 50 GND

51 GND 52 GND

53 XA16 54 XA17

55 XA18 56 XHOLDn

57 XHOLDAn 58 No connect

59 No connect 60 No connect


2-9

2.3.3 P3, Parallel Port/JTAG Interface

The eZdspTM F2812 uses a custom parallel port-JTAG interface device. This deviceincorporates a standard parallel port interface that supports ECP, EPP, andSPP8/bidirectional communications. The device has direct access to the integratedJTAG interface. Drivers for C2000 Code Composer tools are shipped with the eZdspmodules

2.3.4 P4/P8/P7, I/O Interface

The connectors P4, P8, and P7 present the I/O signals from the DSP. The layout ofthese connectors are shown below.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20

Figure 2-6, P4/P8/P7 Connectors

15 16 P4

P8

P7

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40



The pin definition of P4/P8 connectors are shown in the table below.

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JP4.

Table 5: P4/P8, I/O Connectors

P4Pin #

P4 SignalP8

Pin #P8 Signal

P8 Pin #

P8 Signal

1 +3.3V/+5V/NC * 1 +3.3V/+5V/NC * 2 +3.3V/+5V/NC *

2 XINT2/ADCSOC 3 SCITXDA 4 SCIRXDA

3 MCLKXA 5 XINT1n/XBIOn 6 CAP1/QEP1

4 MCLKRA 7 CAP2/QEP2 8 CAP3/QEPI1

5 MFSXA 9 PWM1 10 PWM2

6 MFSRA 11 PWM3 12 PWM4

7 MDXA 13 PWM5 14 PWM6

8 MDRA 15 T1PWM/T1CMP 16 T2PWM/T2CMP

9 No connect 17 TDIRA 18 TCLKINA

10 GND 19 GND 20 GND

11 CAP5/QEP4 21 No connect 22 XINT1N/XBIOn

12 CAP6/QEPI2 23 SPISIMOA 24 SPISOMIA

13 T3PWM/T3CMP 25 SPICLKA 26 SPISTEA

14 T4PWM/T4CMP 27 CANTXA 28 CANRXA

15 TDIRB 29 XCLKOUT 30 PWM7

16 TCLKINB 31 PWM8 32 PWM9

17 XF/XPLLDISn 33 PWM10 34 PWM11

18 SCITXDB 35 PWM12 36 CAP4/QEP3

19 SCIRXDB 37 T1CTRIP/PDPINTAn 38 T3CTRIP/PDPINTBn

20 GND 39 GND 40 GND


2-11

The pin definition of P7 connector is shown in the table below.

2.3.5 P5/P9, Analog Interface

The position of the 30 pins on the P5/P9 connectors are shown in the diagram belowas viewed from the top of the eZdsp.

Table 6: P7, I/O Connector

P7 Pin #

P7 Signal

1 C1TRIPn

2 C2TRIPn

3 C3TRIPn

4 T2CTRIPn/EVASOCn

5 C4TRIPn

6 C5TRIPn

7 C6TRIPn

8 T4CTRIPn/EVBSOCn

9 No connect

10 GND

P9

Figure 2-7, Connector P5/P9 Pin Locations

7531

2018161412108642

19171513119

ANALOG

1 2 3 4 5 6 7 8 9 10

P5



The definition of P5/P9 signals are shown in the table below.

* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.

Table 7: P5/P9, Analog Interface Connector

P5Pin #

SignalP9

Pin #Signal

P9 Pin #

Signal

1 ADCINB0 1 GND 2 ADCINA0








9 ADCREFM 17 GND 18 VREFLO *

10 ADCREFP 19 GND 20 No connect


2-13

2.3.6 P6, Power Connector

Power (5 volts) is brought onto the eZdspTM F2812 via the P6 connector. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2 mm. Theposition of the P6 connector is shown below.

The diagram of P6, which has the input power is shown below.

Figure 2-8, Connector P6 Location

PO

WE

R

TP1

PC Board

P6+5V

Ground

Front ViewFigure 2-9, eZdspTM F2812 Power Connector



2.3.7 Connector Part Numbers

The table below shows the part numbers for connectors which can be used on the

eZdspTM F2812. Part numbers from other manufacturers may also be used.

*SSW or SSQ Series can be used

2.4 eZdspTM F2812 Jumpers

The eZdspTM F2812 has 8 jumpers available to the user which determine how

features on the eZdspTM F2812 are utilized. The table below lists the jumpers and theirfunction. The following sections describe the use of each jumper.

Table 8: eZdspTM F2812 Suggested Connector Part Numbers

Connector Male Part Numbers Female Part Numbers

P1 SAMTEC TSW-1-10-07-G-T SAMTEC SSW-1-10-01-G-T

P2 SAMTEC TSW-1-20-07-G-T SAMTEC SSW-1-20-01-G-T

Table 9: eZdspTM F2812 Jumpers

Jumper # Size FunctionPosition As

Shipped From Factory

JP1 1 x 3 XMP/MCn 2-3

JP4 1 x 3 +3.3/5 Volts to P8,P4 Not connected

JP5 1 x 3 +3.3/5 Volts to P2 Not Connected

JP7 1 x 2 Boot Mode 3 2-3


JP9 1 x 3 PLL Disable 1-2



WARNING!

be installed in either the 1-2 or 2-3 positionUnless noted otherwise, all 1x3 jumpers must


2-15

The diagram below shows the positions of six jumpers on the component side of theeZdspTM F2812.

2.4.1 JP1, XMP/MCn Select

Jumper JP1 is used to select the XMP/MCn option. The 1-2 selection allows the DSP tooperate in the Microcontroller mode. The 2-3 selection allow the DSP to operate in theMicroprocessor mode. The positions are shown in the table below.

* as shipped from factory

Table 10: JP1, XMP/MCn Select

Position Function

1-2 Microprocessor mode

2-3 * Microcomputer mode

Figure 2-10, eZdspTM F2812 Jumper Positions

JP1DS2

JP12

JP7

TP2

DS1

JP8

JP11

JP9

TP1



2.4.2 JP4, JP5 Voltage Jumpers

Jumpers JP4 and JP5 are an unpopulated jumpers on the bottom side of the board thatprovide either +3.3 volts or +5 volts to pins on the expansion connectors. Thesejumpers are shipped uninstalled to prevent accidental damage by connecting wires orcircuitry to the expansion connector. The user may connect these jumpers by installinga jumper wire or zero ohm resistor. The position of these jumpers are shown in thefigure below.

Figure 2-11, eZdspTM F2812 Voltage Jumper Positions (Bottom Side)

JP5

JP4


2-17

2.4.2.1 JP4, +3.3/5 Volts for P8, P4

Jumper JP4 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 ofexpansion connector P8, and pin 1 of P4. The settings for this jumper are shown in thetable below

* As shipped from factory

2.4.2.2 JP5, +3.3/5 Volts for P2

Jumper JP5 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 ofexpansion connector P2. The settings for this jumper are shown in the table below.

* As shipped from factory

Table 11: JP4, +3.3/5 Volts for P8, P4

Position Function Jumper Position

1-2Connect +5 Volts to P8, pins 1,2,

and P4 pin1

2-3Connect +3.3

Volts to P8, pins 1,2, and P4 pin1

No connect *

Table 12: JP5, +3.3/5 Volts for P2

Position Function Jumper Position

1-2Connect +5 Volts to P2, pins

1,2

2-3Connect +3.3 Volts to P2,

pins 1,2

No connect *

3.3V5VJP4

JP4

3.3V5V

JP4

3.3V5V

3.3V5VJP5

JP53.3V5V

JP53.3V5V



2.4.3 JP7, JP8, JP11, JP12, Boot Mode Select

Jumpers JP7, JP8, JP11, JP12 are used to determine what mode the DSP will use forbootloading on power up. To set a signal high, place the jumper in the 1-2 position. For a low signal, use the 2-3 position.The options are shown in the table below.

* factory default

2.4.4 JP9, PLL Disable

Jumper JP9 is used to enable/disable the use of the Phase Lock Loop (PLL) logic onthe DSP. The selection of the 1-2 position enables the use of the PLL. If the 2-3position is used the PLL is disabled. This signal is latched at reset and may be used asXF after reset. The positions are shown in the table below.

* as shipped from the factory

Table 13: JP7, JP8, JP11, JP12, Boot Mode Select

JP7, BOOT3SCITXDA

JP8, BOOT2MDXA

JP11, BOOT1SPISTEA

JP12, BOOT0SPICLKA

MODE

1 X X X FLASH

0 1 X X SPI

0 0 1 1 SCI

0 0 1 0 H0 *

0 0 0 1 OTP

0 0 0 0 PARALLEL

Table 14: JP9, PLL Disable

Position Function

1-2 * PLL Enabled

2-3 PLL disabled


2-19

2.5 LEDs

The eZdspTM F2812 has two light-emitting diodes. DS1 indicates the presence of+5 volts and is normally ‘on’ when power is applied to the board. DS2 is under softwarecontrol and is tied to the XF pin on the DSP through a buffer. These are shown in thetable below.

2.6 Test Points

The eZdspTM F2812 has two test points. The signals they are tied to are shown in thetable below.

Table 15: LEDs

LED # Color Controlling Signal

DS1 Green +5 Volts

DS2 Green XF bit (XF high = on)

Table 16: Test Points

Test Point Signal

TP1 Ground

TP2 Analog Ground



A-1

Appendix A

eZdspTM F2812 Schematics

The schematics for the eZdspTM F2812 can be found on the CD-ROM thataccompanies this board. The schematics were drawn on ORCAD.

The schematics are correct for both the socketed and unsocketed version

of the eZdspTM.

Design Notes:

1. The TMS320F2812 X1/CLKIN pin is +1.8 volt input. The clock input is buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides +3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the schematics.

WARNING !The TMS320F2812 supports +3.3V Input/Output levelswhich are NOT +5V tolerant. Connecting the eZdsp toa system with +5V Input/Output levels will damage theTMS320F2812. If the eZdsp is connected to anothertarget then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.


A-2 eZdspTM F2812 Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QA

4CU

SE

D O

N

EN

GR

-MG

R

RLS

E

DA

TE

DA

TE

RE

V

SH

DA

TE5

C 62

DA

TE

RE

VIS

ION

STA

TUS

OF

SH

EE

TS

RE

V

SH

DW

N

CD

ATE

EN

GR

SH

DA

TE

C

CH

K

BM

FG

1A

PP

LIC

ATI

ON

NE

XT

AS

SY

DA

TE

3

C

RE

V

RE

VIS

ION

S

DE

SC

RIP

TIO

NR

EV

DA

TEA

PP

RO

VE

D

AP

RO

TOTY

PE

S04

-Apr

il-20

02

The

TMS3

20F2

812

EzD

SP d

esig

n is

bas

ed o

npr

elim

inar

y in

form

atio

n(SP

RS1

74G

) for

the

TMS

320F

2812

dev

ice.

Thi

s sc

hem

atic

is s

ubje

ct to

chan

ge w

ithou

t not

ifica

tion.

Spe

ctru

m D

igita

l Inc

.as

sum

es n

o lia

bilit

y fo

r app

licat

ions

ass

ista

nce,

cust

omer

pro

duct

des

ign

or in

fring

emen

t of p

aten

tsde

s crib

ed h

erei

n.

BP

RO

DU

CTI

ON

RE

LEA

SE

07-J

une-

2002

CU

PD

ATE

PE

R S

PR

S17

4G20

-Jan

-200

3

5062

62C

TMS

320F

2812

EzD

SP

B

16

Wed

nesd

ay, J

une

04, 2

003

SPEC

TRU

M D

IGIT

AL IN

CO

RPO

RATE

DTi

tle

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DSP

LOC

ATE

NEA

R DS

P( 3.3

V )

( 1.8

V )

SIN

GLE

PO

INT

CON

NEC

TIO

N

TAIY

O Y

UD

EN E

MK3

25F1

06ZH

-T

SPEC

TRU

M D

IGIT

AL IN

CO

RPO

RATE

D

5062

62C

TMS

320F

2812

EzD

SP

B

26

Wed

nesd

ay, J

une

04, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

XA0XA1XA2XA3XA4XA5XA6XA7XA8XA9XA10XA11XA12XA13XA14XA15XA16XA17XA18

XD

0X

D1

XD

2X

D3

XD

4X

D5

XD

6X

D7

XD

8X

D9

XD

10X

D11

XD

12X

D1 3

XD

1 4X

D15

VD

DA

1

AD

CB

GR

EFI

N

VD

DA

1

VD

D1

1.8V

C28

_TR

STn

(5)

C2 8

_EM

U1

(5)

C28

_EM

U0

(5)

C28

_TC

K(5

)C

28_T

MS

(5)

XD

[0..1

5](3

,4)

XRnW

(4)

XZC

S2n

(4)

XMP

_MC

n(4

)XR

EA

DY

(4)

PW

M1

(4)

PW

M2

(4)

PW

M3

(4)

PW

M4

(4)

PW

M5

(4)

PW

M6

(4)

PW

M7

(4)

PW

M8

(4)

PW

M9

(4)

PWM

10(4

)PW

M11

(4)

CA

P1_

QE

P1

(4)

CA

P2_

QE

P2

(4)

CA

P3_

QE

PI1

(4)

CA

P4_

QE

P3

(4)

CA

P5_

QE

P4

(4)

CA

P6_

QE

PI2

(4)

T1P

WM

_T1C

MP

(4)

T2P

WM

_T2C

MP

(4)

T3P

WM

_T3C

MP

(4)

T4P

WM

_T4C

MP

(4)

TDI R

A(4

)TC

LKIN

A(4

)

TDIR

B(4

)TC

LKIN

B(4

)

PWM

12(4

)

SC

ITX

DA

(4)

SC

IRX

DA

(4)

CA

NTX

A(4

)C

AN

RX

A(4

)

SP

ISIM

OA

(4)

SP

ISO

MIA

(4)

SP

ICLK

A(4

)S

PIS

TE

A(4

)

T1C

TR

IP_P

DP

INT

An

(4)

T3C

TR

IP_P

DP

INT

Bn

(4)

MC

LKX

A(4

)M

CLK

RA

(4)

MFS

XA

(4)

MF

SR

A(4

)M

DX

A(4

)M

DR

A(4

)

XF

_XP

LLD

ISn

(4)

XIN

T1n_

XBI

On

(4)

XIN

T2n_

AD

CS

OC

(4)

XN

MIn

_XIN

T3(4

)

C1T

RIP

n(4

)C

2TR

IPn

(4)

C3T

RIP

n(4

)

C4T

RIP

n(4

)C

5TR

IPn

(4)

C6T

RIP

n(4

)

T2C

TRIP

n_E

VA

SO

Cn

(4)

T4T

RIP

n_E

VB

SO

Cn

(4)

XHO

LDn

(4)

XHO

LDA

n(4

)

XZC

S0A

ND

1n(4

)

XWE

n(3

,4)

XZC

S6A

ND

7n(3

)

1.8V

(4,6

)

XTE

STS

EL(3

,4,5

,6)

XRSn

(5)

X1_C

LKIN

(4)

XCLK

OU

T(4

)

VRE

FLO

(4)

VD

D3V

FL

(6)

SC

ITX

DB

(4)

SC

IRX

DB

(4)

C28

_TD

O(5

)C

28_T

DI

(5)

XRD

n(3

,4)

ADC

INA

0(4

)AD

CIN

A1

(4)

ADC

INA

2(4

)AD

CIN

A3

(4)

ADC

INA

4(4

)AD

CIN

A5

(4)

ADC

INA

6(4

)AD

CIN

A7

(4)

ADC

INB

0(4

)AD

CIN

B1

(4)

ADC

I NB

2(4

)AD

CIN

B3

(4)

ADC

INB

4(4

)AD

CIN

B5

(4)

ADC

INB

6(4

)AD

CIN

B7

(4)

AD

CR

EFP

(4)

AD

CR

EFM

(4)

GN

D(3

,4,5

,6)

AG

ND

(3,4

,5,6

)

XA

[0..1

8](3

,4)

3.3V

3.3V

TP2

AG

ND

1

C37

.001

uF

C56

.001

uF

RN

2A33

116

AB

RN

2B33

215

AB

RN

2D33

413

AB

RN

2E33

512

AB

RN

2F33

611

AB

RN

2C33

314

AB

C35

10U

F C

ER

AM

IC L

OW

ES

R

C36

10U

F C

ER

AM

IC L

OW

ES

R

R26

24.9

K

ADC

FLASH - 3.3V

VDD I/0 -3.3V

VDD CORE - 1.8V

1.8V

U8 TM

S32

0F28

12P

GF

18438085103108111118121125130132138141144148152156158

21 24 27 30 33 36 39 54 65 68 73 74 96 97 139

147

44 88 133

84 42 51 161

17 159

82 77 76 134

160

67 66 135

136

126

131

127

137

146

174

173

172

171

170

169

168

167 2 3 4 5 6 7 8 9 11 10 16 12 13 175

164 92 93 94 95 98 101

102

104

106

107

109

116

117

122

123

124 45 46 47 48 49 50 53 55 57 59 60 71 72 61 62 63 110

115 79 83 149

151

150

40 41 34 35 155

157

87 8928 25 26 29 22 20 140

90 91

69

1416615165

162163

1176

193238525870

8699105113120129142153

78

316481114145

23375675100112128143154

119

XA0XA1XA2XA3XA4XA5XA6XA7XA8XA9

XA10XA11XA12XA13XA14XA15XA16XA17XA18

XD

0X

D1

XD

2X

D3

XD

4X

D5

XD

6X

D7

XD

8X

D9

XD

10X

D11

XD

12X

D13

XD

1 4X

D15

XZC

S0A

ND

1nXZ

CS

2nXZ

CS

6AN

D7n

XW

En

XR

Dn

XR

nWX

RE

AD

YX

MP

/MC

nX

HO

LDn

XH

OLD

An

X1/

XC

LKIN X2

TE

STS

EL

XR

Sn

TE

ST1

TE

ST2

TR

STn

TC

KTM

ST

DI

TDO

EM

U0

EM

U1

AD

CIN

A0A

DC

INA1

AD

CIN

A2A

DC

INA3

AD

CIN

A4A

DC

INA5

AD

CIN

A6A

DC

INA7

AD

CIN

B0A

DC

INB1

AD

CIN

B2A

DC

INB3

AD

CIN

B4A

DC

INB5

AD

CIN

B6A

DC

INB7

AD

CR

EF

PA

DC

RE

FM

AD

CR

ES

EX

TA

VS

SR

EFB

GA

VD

DR

EFB

GA

DC

LOA

DC

BG

RE

FIN

GP

IOA

0-P

WM

1G

PIO

A1-

PW

M2

GP

IOA

2-P

WM

3G

PIO

A3-

PW

M4

GP

IOA

4-P

WM

5G

PIO

A5-

PW

M6

GP

IOA

6-T

1PW

M_T

1CM

PG

PIO

A7-

T2P

WM

_T2C

MP

GP

IOA

8-C

AP

1_Q

EP

1G

PIO

A9-

CA

P2_

QE

P2

GP

IOA

10-C

AP

3_Q

EPI1

GP

IOA

11-T

DIR

AG

PIO

A12

-TC

LKIN

AG

PIO

A13

-C1T

RIP

nG

PIO

A14

-C2T

RIP

nG

PIO

A15

-C3T

RIP

n

GP

IOB

0-P

WM

7G

PIO

B1-

PW

M8

GP

IOB

2-P

WM

9G

PIO

B3-

PW

M10

GP

IOB

4-P

WM

11G

PIO

B5-

PW

M12

GP

IOB

6-T

3PW

M_T

3CM

PG

PIO

B7-

T4P

WM

_T4C

MP

GP

IOB

8-C

AP

4_Q

EP

3G

PIO

B9-

CA

P5_

QE

P4

GP

IOB

10-C

AP

6_Q

EPI2

GP

IOB

11-T

DIR

BG

PIO

B12

-TC

LKIN

BG

PIO

B13

-C4T

RIP

nG

PIO

B14

-C5T

RIP

nG

PIO

B15

-C6T

RIP

n

GP

IOD

0-T

1CT

RIP

_PD

PIN

TAn

GP

IOD

1-T

2CTR

IPn_

EV

AS

OC

nG

PIO

D5-

T3C

TR

IP_P

DP

INTB

nG

PIO

D6-

T4C

TRIP

n_E

VB

SO

Cn

GP

IOE

0-X

INT1

_XB

IOn

GP

IOE

1-X

INT

2_A

DC

SO

CG

PIO

E2-

XN

MI_

XIN

T13

GP

IOF0

-SP

ISIM

OA

GP

IOF1

-SP

ISO

MIA

GP

IOF2

-SP

ICLK

AG

PIO

F3-S

PIS

TEA

GPI

OF4

-SC

ITX

DA

GP

IOF5

-SC

IRX

DA

GP

IOF

6-C

AN

TXA

GP

IOF

7-C

AN

RX

A

GP

IOF

8-M

CLK

XA

GP

IOF

9-M

CLK

RA

GP

IOF

10-M

FS

XA

GP

IOF

11-M

FS

RA

GP

IOF1

2-M

DX

AG

PIO

F13-

MD

RA

GP

IOF1

4-X

F-X

PLL

DIS

n

GP

IOG

4-S

CIT

XD

BG

PIO

G5-

SC

IRXD

B

VDD3VFL

VDDA1VDDA2VSSA1VSSA2

VDD1VSS1

VDDAIOVSSAIO

VSS2VSS3VSS4VSS5VSS6VSS7

VSS9VSS10VSS11VSS12VSS13VSS14VSS15VSS16

VSS8

VDDIO1VDDIO2VDDIO3VDDIO4VDDIO5

VDD2VDD3VDD4VDD5VDD6VDD7VDD8VDD9

VDD10

XC

LKO

UT

C58

.1uF

L4

BLM

21P

221S

N

TP3

TP

C2

1uF

C3

1uF

C57

.1uF

L3

BLM

21P

221S

NC

38.1

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AS

RA

M

64K

x16

and

256K

x16

Com

patib

le

SPEC

TRU

M D

IGIT

AL IN

CO

RPO

RATE

D

5062

62B

TM

S32

0F28

12 E

zDS

P

B

36

Wed

nesd

ay, J

une

04, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

XA

15

XA

10

XA

13

XA5

XA2

XA8

XA9

XA

14

XA6

XA1

XA0

XA4

XA3

XA7

XA

11X

A12

XD

4

XD

15

XD

1

XD

13

XD

3

XD

0

XD

12

XD

10

XD

7

XD

5

XD

2

XD

9X

D8

XD

6

XD

11

XD

14

XA

16X

A17

XW

En

(2,4

)X

RD

n(2

,4)

XA

[0..1

8](2

,4)

XD

[0..1

5](2

,4)

GN

D(2

,4,5

,6)

XZC

S6A

ND

7n(2

)

3.3 V

C22

0.1u

FC

100.

1uF

U4

IS61

LV64

16-1

2T

1 2 3 4 5 18 19 20 21 22 2324 25 26 27 42 43 44

7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38

6 17 41 40 39

28

1133

1234

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A1 2

A13

A1 4

A15

A16

A17

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D1 0

D11

D1 2

D13

D14

D15

CS

WE

OE

BH

EB

LE

NC

VDD1VDD2

VSS1VSS2


A-5

8 8

7 7

6 6

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

XF

XF

X TES

TSE L

X MPN

MC

BOOT MODE

PLLD

ISn BO

OT-

0

B OO

T-1

B OO

T-2

BOO

T-3

BO

OT-

3B O

OT-

2B O

OT-

1B O

OT-

0

FLAS

H

SPI

SCI

H0

OTP

PARA

LLEL

SC

ITXD

AM

DXA

SPIS

TEA

SPIC

LKA

MO

DE

0 0 0 0 0

0 0 0 0

0 00

0

1

1

1 1

11

XX X

X X

SMT/

4PIN

DIP

OPT

ION

AL

Con

nect

VR

EFLO

to A

GND

or

t o V

REF

LO o

f tar

get s

yste

mfo

r pro

per A

DC

ope

ratio

n.

Sch

emat

ic c

hang

e fro

m v

ersi

onA

/B to

C.

F281

2 clk

in is

1.8

Vin

put.

Tie

off u

nuse

d F2

4xx

com

patib

le s

igna

ls.

Mak

e a

sold

er c

onne

ctio

n on

JP4

and/

or J

P5 to

the

appr

opria

te p

ower

sup

ply.

TM

S32

0F28

12

sup

port

s 3.

3Vi n

put/

out

put

leve

ls w

hic

h a

reN

OT

5V

to

lera

nt.

Con

nec

tin

gt h

e eZ

dsp

to a

sys

tem

wit

h 5V

i npu

t/o

utpu

t le

vels

will

dam

age

t he

TM

S32

0F28

12.

If

the

eZ

dsp

i s c

onn

ecte

d t

o a

not

her

targ

ett h

en t

he e

Zds

p m

ust

be

p ow

ered

up

firs

t an

d p

owe

red

d ow

n la

st t

o pr

eve

nt la

tchu

pco

ndi

t ion

s.

5062

62C

TM

S32

0F28

12 E

zDS

P

B

46

Wed

nesd

ay, J

une

04, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

ISn

ST

RB

n

DSP

_RS

n

ISn

STR

Bn G

ND

SC

IRX

DA

(2)

CA

P1_

QE

P1

( 2)

CA

P3_

QE

PI1

(2)

PW

M2

(2)

PW

M4

(2)

PW

M6

( 2)

SP

ISO

MIA

(2)

SP

IST

EA

(2)

CA

NR

XA

(2)

XD

0(2

,3)

XD

1(2

,3)

XD

2( 2

,3)

XD

3( 2

,3)

XD

4(2

,3)

XD

5(2

,3)

XD

6(2

,3)

XD

7(2

,3)

XD

8(2

,3)

XD

9(2

,3)

XD

10( 2

,3)

XD

11( 2

,3)

XD

12(2

,3)

XD

13(2

,3)

XD

14( 2

,3)

XD

15( 2

,3)

XA

0(2

,3)

XA1

(2,3

)X

A2

( 2,3

)X

A3( 2

,3)

XA

4(2

,3)

XA5

(2,3

)X

A6

(2,3

)X

A7(2

,3)

XA

8(2

,3)

XA9

(2,3

)X

A10

(2,3

)X

A11

(2,3

)X

A12

(2,3

)X

A13

(2,3

)X

A14

(2,3

)X

A15

(2,3

)

XR

EA

DY

(2)

XR

nW(2

)X

WE

n(2

,3)

XR

Dn

(2,3

)

VR

EFL

O(2

)

T2P

WM

_T2C

MP

(2)

T CLK

INA

( 2)

PW

M7

(2)

PW

M9

(2)

PW

M11

(2)

CA

P4_

QE

P3

( 2)

T3C

TR

IP_P

DP

INTB

n(2

)

DS

P_R

Sn

(5)

SC

ITX

DA

( 2)

XIN

T1n_

XB

IOn

(2)

CA

P2_

QE

P2

(2)

PW

M1

( 2)

PW

M3

(2)

PW

M5

(2)

T1PW

M_T

1CM

P(2

)TD

IRA

(2)

SP

ISIM

OA

(2)

SP

ICLK

A(2

)C

AN

TXA

(2)

XC

LKO

UT

(2)

PW

M8

(2)

PW

M10

(2)

PW

M12

(2)

T1C

TR

IP_P

DP

INTA

n(2

)

XN

MIn

_XIN

T3(2

)

XIN

T1n_

XB

IOn

( 2)

XH

OLD

An

( 2)

XA

16(2

,3)

XA

18(2

)X

A17

(2,3

)X

HO

LDn

(2)

XTE

STS

EL(2

,3,5

,6)

AD

CIN

A0

(2)

AD

CIN

A1

(2)

AD

CIN

A2

(2)

AD

CIN

A3

(2)

AD

CIN

A4

(2)

AD

CIN

A5

( 2)

AD

CIN

A6

(2)

AD

CIN

A7

( 2)

AD

CIN

B0

(2)

AD

CIN

B1

(2)

AD

CIN

B2

(2)

AD

CIN

B3

(2)

AD

CIN

B4

(2)

AD

CIN

B5

(2)

AD

CIN

B6

( 2)

AD

CIN

B7

(2)

MC

LKR

A( 2

)M

CLK

XA

(2)

MD

X A( 2

)M

DR

A(2

)

MFS

RA

(2)

MFS

XA

( 2)XIN

T2n_

AD

CS

OC

( 2)

CA

P5_

QE

P4

(2)

CA

P6_

QE

PI2

(2) T3P

WM

_T3C

MP

(2)

T4P

WM

_T4C

MP

(2)

TDIR

B(2

)T C

LKIN

B( 2

)X

F_X

PLL

DIS

n(2

)S

CIT

XD

B( 2

)S

CIR

XD

B(2

)

XF_

XP

LLD

ISn

( 2)

XMP

_MC

n(2

)

SPIC

LKA

(2)

SP

IST

EA(2

)

MD

XA

( 2)

SCIT

XD

A(2

)

C1T

RIP

n(2

)C

2TR

IPn

( 2)

C3T

RIP

n(2

)

C4T

RIP

n( 2

)C

5TR

IPn

(2)

C6T

RIP

n( 2

)T4

TRIP

n_E

VB

SO

Cn

(2)

T 2C

TR

IPn_

EV

AS

OC

n( 2

)

GN

D(2

,3,5

,6)

AD

CR

EFP

(2)

AD

CR

EFM

(2)

AG

ND

(2,3

,5,6

)

XZC

S2n

(2)

XZC

S0A

ND

1n(2

)

X1_

CLK

IN(2

)

MC

LK(5

)

1.8V

(2,6

)

3 .3V

3 .3V

3.3V

3.3V

3.3V

3.3V

3.3V

+ 5V

3.3V

3.3V

+ 5V

P7

1 2 3 4 5 6 7 8 9 10

J P12

JUM

PE

R3B

1 32

R39

1 0K

R36

2 .2K

JP9

JUM

PE

R3B

1 32

R42

10K

R41

2.2K

R6

10K

R5

10K

JP11

JUM

PE

R3B

1 32

R35

2.2K

R38

10K

JP8

JUM

PE

R3B

1 32

R37

2.2K

R40

10K

JP7

JUM

PE

R3B

1 32

R30

2.2K

R31

10K

P4

1 2 3 4 5 6 7 8 9 10 11 1 2 13 14 15 16 17 18 19 20

P9

12

34

56

78

910

1112

1314

1516

1718

1920

P5

1 2 3 4 5 6 7 8 9 10

P8

12

34

56

78

91 0

1112

1314

1 51 6

1718

1 92 0

2122

2 32 4

2526

2728

2930

3132

3 33 4

3536

3 73 8

3940

U14 SN

74LV

C1G

14

24

35

P2

HE

AD

ER

30X

2

12

34

56

78

91 0

1112

1314

1 51 6

1718

1 92 0

2122

2 32 4

2526

2728

2930

3132

3 33 4

3536

3 73 8

3940

4 14 2

4344

4 54 6

4748

4950

5152

5354

5 55 6

5758

5 96 0

DS

2LT

ST-C

150G

KT

GR

EEN

JP4

JUM

PE

R3_

SM

T

1

2

3AB

C

JP5

JUM

PE

R3_

SMT

12

3AB

C

R1

100

JP3

JUM

PE

R3_

SM

T

1

2

3A

BC

C62

.1uF

U12

SN74

AH

C1G

14

3

4

5

2

R43 22

0

U11

NO

-PO

P

1 4

8 5

OFF

n

GN

D

VC

C

CLK

C43

0.1u

F

JP1

J UM

PE

R3B

1 32

L1 BLM

21P

2 21S

N

R29

100

C42 33

pF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

XD

S510

PP E

MU

LATI

ON

HEA

DER

PLAC

E N

EAR

EA

CH

MO

UN

TIN

G H

OLE

OPE

N-DR

AIN

CR

OS

S C

OU

PLE

IN T

O OU

T

EXT_

VER

001

10-0

01

XR

Sn is

logi

cal A

ND

of P

ON

RSn

IN a

ndem

ulat

or c

ontro

lled

rese

t. P

ower

on

defa

ult

is P

ON

RnI

N c

ontro

ls X

RS

n.

PPEM

U0/

1 C

ON

NEC

T D

IREC

TLY

TO F

2812

FO

REM

ULA

TOR

WAI

T-IN

-RES

ET S

UPP

OR

T

CBL

V-3C

-30.

000

IF U

13 IS

INST

ALLE

D T

HEN

REM

OVE

R49

AN

D R

48.

Loca

te R

7,R

54, C

70 a

t the

DSP

XR

Sn p

info

r bes

t EM

I/ES

D n

oise

imm

unity

.

To/fr

om e

xpan

sion

hea

der

SPEC

TRU

M D

IGIT

AL IN

CORP

ORA

TED

5062

62C

TMS

320F

2812

EzD

SP

C

56

Wed

nesd

ay, J

une

04, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:Sh

eet

of

PPBU

SD

IRPP

BUS

ENn

XPPS

4XP

PS5

XPPS

7nXP

PS3

PPD

1PP

INIT

n

PPD

3PP

SELn

P PAL

E n

PPER

Rn

P PST

RBn

PPD

2

PPD

0

5V PPT

DO

PPT

CK

PPT

MS

PPT

DI

XPP

D6X

PPD5

XPP

D4X

PPD3

XPP

D2X

PPD1

XPP

D0

XPPS

3XP

PS4

XPPS

5

XPPS

7n

PPBUSENn

PPBUSDIR

XPPC3nXPPC2XPPC1nXPPC0n

PPTRSTnXTRSTn

XEVNT0

XTDI

PPTMSXTMS

XTDO

3.3V

XEV

NT1

TPOWLOSSnPONRSnIN

PPTDI

XPPC

3n

X PPC

2

XPPC

0n

XTC

K

PPTC

K

PPTD

O

IPPTCK

IPPTDO

X EVN

T1

XEVN

T0

XTC

K

XTD

O

XTD

I

XTM

S

XTR

STn

PON

RS

nIN

T PO

WLO

S Sn

XPP

D7

ALT_MCLKVCCRVCCR

5 V

PPT

RS

Tn

PPD

4

GN

D

XTCKI

GND

EM

UO

FF

GN

D

FPGA_VCCA

P PD

7

PPSL

CT

GN

D

3.3V

PP A

CKn

FPG

A_V

CC

A

P PD

6

GND

JCLK

3.3V

FPGA_VCCA

3.3V

3.3V

GND

3.3V

P PD

5

PPPE

GN

D

GN

D

GN

D

3.3V

GN

D

GN

D

GN

D

GN

D

GND

GND GND

GND

GN

D3.

3VFPG

A_V

CC

A

GN

D

XPP

D0

XPP

D7

XPP

D2

XPP

D 6

XPP

D1

XPP

D3

XPP

D5X

PPD4

PPBS

Y

XPPC

1n

5V

5V

MCLK

3.3V

3.3V

GND

GND

GN

D

3.3V

EMUOFF

PP E

MU

1

PP E

MU

0

5V

FPG

A_V

CC

A

VC

CR

DSP

_RSn

P ON

RS

nIN

( 6)

GN

D(2

,3,4

,6)

C28

_TR

STn

(2)

C28

_EM

U1

(2)

C28

_EM

U0

( 2)

C28

_TC

K( 2

)

C28

_TM

S(2

)

C28

_TD

I( 2

)

C28

_TD

O( 2

)

X RS n

( 2)

MC

LK(4

)

DSP

_RSn

(4)

3.3V

3.3V

3.3V

3.3V

3 .3V

3.3V

3.3V

+5V

3.3V

+5V

R54

100

C70

22nF

C47

0.1u

F

C14

0.1u

F C13

0.1u

F

C24

0.1u

F

C26

0.1u

FC

250.

1uF

C11

0.1u

FC

450.

1uF

C23

0.1u

F

C49

0.1u

F

C68

1uF

U10

30 M

Hz

1 4

8 5

OFF

n

GN

D

VCC

CLKL2 BL

M21

P221

SNC

48

0.1u

F

R51 40

.2K

1%

R50 41

.2K

1%

R48

0

U13 TP

S722

01

1 2 345

IN GN

D

ENN

C/F

B

OU

T

C27

.1uF

C28

.001

uF

R9

33

R47

1M

C67

.001

uF

C16

.001

uF

RN

4D33

413

AB

RN

4H33

89

AB

RN

4A33

116

AB

RN

4B3 3

215

AB

RN

4C33

314

AB

R12

1 0K

RN

4E33

512

AB

RN

4F33

611

AB

RN

4G33

71 0

AB

RN

3A33

116

AB

C50

.1uF

R11

10K

R22

10K

RN

3E33

512

AB

RN

3D33

413

AB

RN

3C33

314

AB

RN

3B3 3

215

AB

R8

33

RN

3H33

89

AB

RN

3G33

71 0

AB

RN

3F33

611

AB

U2

74A

BT24

5PW

2 3 4 5 6 7 8 9 19 1

18 17 16 15 1 4 13 1 2 11 1020

A1

A2

A3

A4

A5

A6

A7

A8

G DIR

B1

B2

B3

B4

B5

B6

B7

B8

GN

D

VC

C

RN

1H33

89

AB

RN

1D33

413

AB

R10

33

RN

1G33

71 0

AB

RN

1C33

314

AB

RN

1F33

611

AB

RN

1B33

215

AB

R25

1 00

R23

10K

RN

1A33

116

AB

RN

1E33

51 2

AB

C30

3 3pf

P3 DB

25_S

HIE

LD13 25 12 24 1 1 23 1 0 22 9 21 8 20 7 19 6 18 5 17 4 1 6 3 1 5 2 14 1

A

B

R19

1M

C15

33pf

R24

1 00

R15

100

C34

3 3pf

U5

74A

BT24

5PW

2 3 4 5 6 7 8 9 19 1

18 17 16 15 14 13 1 2 11 1 020

A1

A2

A3

A4

A5

A6

A7

A8

G DIR

B1 B2 B 3 B4 B5 B6 B7 B8

GN

D

VCC

R16

10K

R17

10K

C17

33pf

C52

33pf

R18

100

P1

HE

ADER

7X2

12

34

56

78

91 0

1112

1314

R13

10K

C54

33pf

C53

3 3pf

R14

10K

R20

100

C29

33pfC

55

33pf

C33

33pf

EMBE

DD

ED P

P JT

AG C

ONTR

OLLE

RSP

ECTR

UM

DIG

ITAL

INC

.

5060

53-0

001B

U6

5060

53-0

001B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

515253545556575859606162636465666768697071727 37475

767778798081828384858687888990919293949596979899100

GN

DR

SV1_

TDI_

IOEM

UO

FFXE

VN

T1PP

EMU

1R

SV2

RSV

3_TM

S_IO

VCC

IG

ND

XPPD

0XP

PD1

XPPD

2XP

PD3

XPPD

4XP

PD5

XPPD

6XP

PD7

RSV

4R

SV5

VCC

IXP

PS3

XPPS

4XP

PS5

XPPS

6XP

PS7n

PPBUSENnRSV6PPBUSDIRRSV7XPPC3nXPPC2XPPC1nXPPC0nRSV8_PRB_IOVCCAGNDVCCR_NCALT_MCLKHCLKRSV9PONRSnTPOWLOSSnVFUNC_ENVCCIEXT_VER7EXT_VER6EXT_VER5EXT_VER4EXT_VER3EXT_VER2

GN

DEX

T_VE

R1

EXT_

VER

0V

POW

ER_O

Nn

VPO

WE

R_B

LEE

DVB

US_

ENn

VCC

AV

CC

IXB

ITIN

3XB

ITIN

2XB

ITIN

1XB

ITIN

0XB

ITO

UT3

XBIT

OU

T2XB

ITO

UT1

XBIT

OU

T0VC

CA

GN

DG

ND

EXTE

RN

_RST

nM

CLK

OU

T2E

NM

CLK

OU

T2M

CLK

OU

TEN

MC

LKO

UT

DSP

_RS

n

EMUOFF_1ODEMU1_SRCODEMU0_SRC

ODEMU1nODEMU0n

PPTDIVCCI

XTDOPPTMS

XTMSJCLK

RSV10XTCKI

VCCR_NCVCCAGND

RSV11_PRA_IOPPTDO

XTDIPPTCK

PPTRSTnXTRSTnPPEMU0XEVNT0

RSV13_TCK_IO

C31

33pf

C32

33pf

R32

33

R7

1.5K

C51

.001

uF

R49

0

C46 NO

-PO

P


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+5V

Max

16.9

K 1.

848V

15.0

K 1.7

7 3V

13.7

K 1.

722V

PO

NR

SnI

N, G

OE

S H

IGH

> 2

00m

s A

FTE

R A

LL P

OW

ER

IS S

TA

BLE

.

3.3V

TH

EN

1.8

V

PO

WE

R O

N S

EQ

UE

NC

E N

OTE

S

3.3V

SU

PP

LY, V

DD

IOV

DD

3VFL

, VD

DA

1,V

DD

A2

1.8V

SU

PP

LY

2.2V

140m

s-28

0ms

Q3

PO

NR

SnI

N

VO

LTA

GE

SU

PP

LY

M

AX

CU

RR

EN

T

T

PS

767D

301

PD

1.8V

3.3V

333m

A

307m

A

1065

mW

521m

W

PD

(max

) = (T

j(max

) - T

a)/R

ja

= (1

25 -

35)/2

7.9

= 32

55m

W

TP

S76

7D30

1 R

ATI

NG

S

MA

X Io

ut P

ER

CH

AN

NE

L IS

1A

TPS

767D

301

PD

= (V

in-V

out)*

Iout

1586

mW

Tot

al

TIE

TP

S76

7D30

1 P

OW

ER

PA

D T

O G

ND

PLA

NE

(TI

-SLM

A00

2)

SE

T Q

3 TO

TU

RN

ON

WH

EN

3.3

V S

UP

PLY

ISG

RE

AT

ER

TH

EN 2

.2 V

OLT

S.

RE

GU

LAT

OR

TU

RN

ON

DE

LAY

AN

D R

AM

P R

ATE

WIL

LE

NS

UR

E T

HA

T 3.

3V S

UP

PLY

IS A

T 2.

5 V

OLT

SO

R H

IGH

ER

BE

FOR

E T

HE

1.8

V S

UP

PLY

RE

AC

HE

S 0

.3 V

OLT

S.

18.2

K 1.8

9 9V

U16

WIL

L TU

RN

OFF

TH

E 1

.8V

SU

PP

LY W

HE

NIN

PU

T P

OW

ER

FA

LLS

BE

LOW

2.9

4V.

TH

IS S

PE

ED

SU

P T

HE

1.8

V S

UP

PLY

TU

RN

OF

F.

RE

SE

Tn o

f TP

S38

38 is

ope

n-dr

ain.

U16

was

add

ed fo

r tes

ting

but n

otpo

pula

ted

on p

rodu

ctio

n bo

ards

.

SPEC

TRU

M D

IGIT

AL IN

CO

RPO

RAT

ED

5062

62C

TMS

320F

2812

EzD

SP

B

66

Wed

nesd

ay, J

une

04, 2

003

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

1.8V

ON

n1.

8V(2

,4)

1.8V

(2,4

)

PO

NR

SnI

N(5

)

VD

D3V

FL(2

)

GN

D(2

,3,4

,5)

+5V

3.3V

3.3V

3.3V

3.3V

R2 10

K

TP1

GN

D1

C8

0.1 u

FC

50.

1 uF

C41

0.1 u

FC

180.

1 uF

C21

0.1 u

FC

190.

1 uF

C40

0.1 u

FC

610.

1 uF

R46

10K

C39

0.1u

FC

600.

1uF

C9

0.1u

FC

200.

1uF

C6

0.1u

F

R4 5

30.1

K, 1

%

C65

0.1u

F

C66

0.1u

FR

3316

. 9K

, 1%

+C

T3

22uF

C64

0.1u

F

C63

0.1u

F+

CT4

22u F

U9

TPS

767D

301

5 6 4 3 11 12 10 9 1 2 7 8 13 14

15 16 20 21 26 2728 23 24 25 22 17 18 19

1IN

1IN

1EN

1GN

D

2IN

2IN

2EN

2GN

D

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

1RES

ET

1OU

T1O

UT

1FB

/SE

NS

E

2RES

ET

2OU

T2O

UT

2SE

NS

E

THERMAL_PAD

+C

T1

22u F

+C

T5

22u F

+C

T2

47uF

C7

.1u F

C1

1uF

P6

C59

0.1 u

F

R53 1.

5K 1

%

U16 TP

S38

38K

33D

BV

1 2 3

45C

T

GN

D

MR

n

RE

SE

Tn

VD

DQ

3B

SS

138

G

D S

R44

220

R34 2.

0K 1

%

R52

0

DS1

LTS

T-C

150G

KT

GR

EE

N

+C

T622

u F



B-1

Appendix B

eZdspTM F2812 MechanicaI Information

This appendix contains the mechanical information about the socketed and

unsocketed versions of the eZdspTM F2812


B-2 eZdspTM F2812 Technical Reference

Th

is d

raw

ing

is n

ot

to s

cale


B-3

Th

is d

raw

ing

is n

ot

to s

cale


B-4 eZdspTM F2812 Technical Reference

Printed in U.S.A., September 2003506265-0001 Rev. F