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TMS320C6455 DSK Technical Reference
508555-0001 Rev. C September 2006
SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.
Copyright © 2006 Spectrum Digital, Inc.
Contents
1 Introduction to the TMS320C6455 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6455 DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Bootmode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6455 DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.7 MISC2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7 I2C ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.9 DSP and EMIFA Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.10 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-103 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6455 DSK and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1 J1301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2 J1303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.3 J1304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.4 J1302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.6.1 J1201, USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.6.2 J8, 14 Pin External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.6.3 J7, 60 Pin Advanced Emulation Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.6.4 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.6.5 J9, AMCC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.6.6 P1102, Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.7 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.8 SW2, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C6455 DSKB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C6455 DSK
About This Manual
This document describes the board level operations of the TMS320C6455 DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6455 Digital Signal Processor.
The TMS320C6455 DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C6455 DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6455 DSK will sometimes be referred to as the DSK, C6455 DSK, orTMS320C6455 DSK.
Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.
equations!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C64xx DSP CPU Reference GuideTexas Instruments TMS320C64xx DSP Peripherals Reference Guide
Table 1: Manual History
Revision History
A Initial Release
B Changed CLKIN to 50 Mhz.Fixed swizzle on daughter card interrupts
C Corrected connector documentationReplaced sheets 4,5 of schematics
1-1
Chapter 1
Introduction to the TMS320C6455 DSK
Chapter One provides a description of the TMS320C6455 DSK alongwith the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Bootmode Configurations 1-71.7 Power Supply 1-8
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1-2 TMS320C6455 DSK Module Technical Reference
1.1 Key Features
The C6455 DSK is a high performance standalone development platform that enablesusers to evaluate and develop applications for the TI C64xx DSP family. The DSK alsoserves as a hardware reference design for the TMS320C6455 DSP. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.
The DSK comes with a full compliment of on-board devices that suit a wide variety ofapplication environments. Key features include:
• A Texas Instruments TMS320C6455 DSP operating at 1 Gigahertz.
• An AIC23 stereo codec
• 128 Mbytes of DDR2 memory
• 4M bytes of non-volatile Flash memory
• 10/100 MBPs ethernet interface
• I2C Serial ROM
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configured boot options and clock input selection
• Standard expansion connectors for daughter card use
Figure 1-1, Block Diagram C6455 DSK
EN
DIA
NB
OO
T0
BO
OT
1B
OO
T2
BO
OT
3S
PA
RE
1S
PA
RE
2S
PA
RE
3PHY
MIC
IN
LIN
E O
UT
HP
OU
T
LIN
E IN
LED
DIP
SerialRapid I/O
McBSPs
JTAG
0 1 2 3
I²C Bus
Mez
zan
ine
1.8V I/O Power Supply
PW
R
US
B
DDR2
Memory Exp
FlashEMIFA
PC
I/HP
I
1 2 3 4
DDR2
MezzaninePower
Ext.JTAG
1.2V Core Power Supply
3.3V I/O Power Supply
ENET
AIC23Codec
Peripheral Exp
I²CROM
5 6 7 8
CPLD
64
32
6455DSP
MII
On-BoardJTAG
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1-3
• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator
• Single voltage power supply (+5V)
1.2 Functional Overview of the TMS320C6455 DSK
The DSP on the C6455 DSK interfaces to on-board peripherals through the 64-bit wideEMIFA configured for 32 bit accesses. The CPLD and daughter card expansionconnectors are connected to EMIFA. The DDR2 memory is on its own dedicated EMIF.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals.
I2C is used for the codec control interface and McBSP1 is used for data. AnalogI/O is done through four 3.5mm audio jacks that correspond to microphone input, lineinput, line output and headphone output. The codec can select the microphone or theline input as the active input. The analog output is driven to both the line out (fixedgain) and headphone (adjustable gain) connectors. McBSP0 and McBSP1 can be re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that tiesthe board components together. The CPLD also has a register based user interfacethat lets the user configure the board by reading and writing to the CPLD registers.
A Flash memory is mapped into CE3 space. The Flash contains power on self test asshipped, or can be programmed for user programs.
The DSK has a 10/100 mbit Phy which is connected to the DSP’s on board EMAC.
The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide theuser with interactive feedback. Both are accessed by reading and writing to the CPLDregisters.
An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the 1.2V DSP core voltage, 1.8V for DDR, and 3.3V I/Osupplies. The board is held in reset until these supplies are within operatingspecifications.
Code Composer communicates with the DSK through an embedded JTAG emulatorwith a USB host interface. The DSK can also be used with an external emulatorthrough the external 60 pin and 14 pin JTAG connectors.
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1-4 TMS320C6455 DSK Module Technical Reference
1.3 Basic Operation
The DSK is designed to work with TI’s Code Composer Studio developmentenvironment and ships with a version specifically tailored to work with the board.Code Composer communicates with the board through the on-board JTAG emulator.To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation anddrivers.
After the install is complete, follow these steps to run Code Composer. The DSK mustbe fully connected to launch the DSK version of Code Composer.
1) Connect the included power supply to the DSK.
2) Connect the DSK to your PC with a standard USB cable (also included).
3) Launch Code Composer from its icon on your desktop.
Detailed information about the DSK including a tutorial, examples and referencematerial is available in the DSK’s help file.
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1-5
1.4 Memory Map
The C64xx family of DSPs has a large byte addressable address space. Program codeand data can be placed anywhere in the unified address space. Addresses are always32-bits wide.
The memory map shows the address space of a generic 6455 processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.
EMIFA (External Memory Interface A) has 4 separate addressable regions calledchip enable spaces (CE2-CE5). The DDR2 occupies CE0 of DDR2 Memory bus.The CPLD and Flash are mapped to CE2 and CE3 of EMIFA respectively. Daughtercards use CE4 and CE5 of EMIFA.
Figure 1-2, Memory Map, C6455 DSK
CPLD
Flash
DRR2
Reservedor
Peripheral
InternalMemoryInternal Memory
Reserved Spaceor
Peripheral Regs
EMIFA CE2
EMIFA CE3
EMIFA CE4
EMIFA CE5
DDR2 CE0
6455 DSKGeneric 6455
Address SpaceAddress
0x00000000
0x00100000
0xA0000000
0xB0000000
0xC0000000
0xD0000000
0xE0000000
Daughter
Card
Memory
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1-6 TMS320C6455 DSK Module Technical Reference
1.5 Configuration Switch Settings
The DSK has 8 configuration switches that allows users to control the operational stateof the DSP when it is released from reset. The configuration switch block is labeledSW3 on the DSK board, next to the reset switch.
Configuration switch 1 controls the endianness of the DSP. The factory default is littleendian.The settings of switch 1 are shown in the table below.
* Default
Switches 2-5 configure the boot mode that will be used when the DSP starts executing. These boot modes are shown in the table below. The default boot mode is EMIFA 8 bitROM Boot.
** Default
Table 1: Endian Configuration Switch Settings
SW3-1 Configuration Description
Off Little endian *
On Big endian
Table 2: Boot Load Configuration Switch Settings
SW3-5AE19
SW3-4 *AE18
SW3-3AE17
SW3-2AE16
Configuration Description
Off Off Off Off No Boot
Off Off Off On Host Boot HPI
Off Off On Off Reserved
Off Off On On Reserved
Off On Off Off EMIFA 8 bit ROM Boot *
Off On Off On I2C Boot Master
Off On On Off I2C slave
Off On On On Host Boot PCI
On x x xSerial Rapid I/O Boot
see DSP data sheet for more details
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1-7
On revision “C” and newer boards the switch positions 6-8 are spare switches. TheCLKIN frequency is now set to a fixed 50 Mhz. oscillator.
1.6 Bootmode Configurations
The C6455 uses the address lines to configure the device configuration at RESET.Although many of these configurations can be changed in software via internal DSPconfiguration registers, the defaults for the DSK are shown in the table below.
Table 3: Bootmode Configurations
Config Pin
NameFunction Controlled By
AE19 Boot Mode 3 SW3-5
AE18 Boot Mode 2 SW3-4
AE17 Boot Mode 1 SW3-3
AE16 Boot Mode 0 SW3-2
AE15 AECLKIN Selected Resistor Strap
AE14 HPI 32 bit Mode Selected Resistor Strap
AE13 Endian Mode SW3-1
AE12 Ethernet MAC Enabled Resistor Strap
AE11 Reserved Resistor Strap
AE10 EMAC MDIO/MII Mode Resistor Strap
AE9 EMAC MDIO/MII Mode Resistor Strap
AE8 PCI I2C ROM Enable Resistor Strap
AE7 Reserved Resistor Strap
AE6 PCI 33 Mhz. Resistor Strap
AE5 McBSP1 Enabled Resistor Strap
AE4 SYSCLK4 Output Resistor Strap
AE3 Reserved Resistor Strap
AE2 CFGGP2 Resistor Strap
AE1 CFGGP1 Resistor Strap
AE0 CFGGP0 Resistor Strap
ABA1 EMIFA Enabled Resistor Strap
ABA0 DDR Enabled Resistor Strap
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1-8 TMS320C6455 DSK Module Technical Reference
1.7 Power Supply
The DSK operates from a single +5V external power supply connected to the mainpower input (J5). Internally, the +5V input is converted into +1.5, +1.8V and +3.3Vusing multiple voltage regulators. The +1.2V supply is used for the DSP core while the+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The+1.8 volt supply is used to support DDR2 memories. The power connector is a 2.5mmbarrel-type plug.
The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derivedfrom the +5V power source via the main +3.3 volt regulator. It is also possible toprovide the daughter card with +12V and -12V when the external power connector (J6)is used.
2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components onthe TMS320C6455 DSK.
Topic Page
2.1 CPLD (Programmable Logic) 2-22.1.1 CPLD Overview 2-22.1.2 CPLD Registers 2-32.1.3 USER_REG Register 2-32.1.4 DC_REG Register 2-42.1.5 Version Register 2-42.1.6 MISC Register 2-52.1.7 MISC2 Register 2-52.2 AIC23 Codec 2-62.3 DDR2 Memory 2-72.4 Flash Memory 2-72.5 LEDs and DIP Switches 2-72.6 Ethernet Interface 2-72.7 I2C ROM 2-82.8 Daughter Card Interface 2-82.9 DSP and EMIFA Clock Generation 2-82.10 JTAG Interfaces 2-10
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2-2 TMS320C6455 DSK Module Technical Reference
2.1 CPLD (Programmable Logic)
The C6455 DSK uses an Altera EPM3128TC100-10 Complex Programmable LogicDevice (CPLD) device to implement:
• 5 Memory-mapped control/status registers that allow software control of various board features.
• Address decode and memory access logic.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your ownhardware designs will likely implement a completely different set of functions or takeadvantage of the DSPs high level of integration for system design and avoid the use of external logic completely.
The CPLD implements simple random logic functions that eliminate the need foradditional discrete devices. In particular, the CPLD aggregates the various resetsignals coming from the reset button and power supervisors and generates a globalreset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industrystandard VHDL (Hardware Design Language) and included with the DSK.
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2.1.2 CPLD Registers
The 5 CPLD memory-mapped registers allows users to control CPLD functions insoftware. On the C6455 DSK the registers are primarily used to access the LEDs andDIP switches and control the daughter card interface. The registers are mapped intoCE2 data space at address 0xA0000000. They appear as 8-bit registers with asimple asynchronous memory interface. The following table gives a high leveloverview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 5 registers in CPLD.
2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on oroff to allow the user to interact with the DSK. The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 1: CPLD Register Definitions
Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 USER_REG USR_SW3R
USR_SW2R
USR_SW1R
USR_SW0R
USR_LED3R/W
0(Off)
USR_LED2R/W
0(Off)
USR_LED1R/W
0(Off)
USR_LED0R/W
0(Off)
1 DC_REG DC_DETR
0 DC_STAT1R
DC_STAT0R
DC_RSTR
0(No reset)
0 DC_CNTL1R/W
0(low)
DC_CNTL0R/W
0(low)
4 VERSION CPLD_VER[3.0]R
0 BOARD VERSION[2.0]R
6
MISCMcBSP2_EN
R(MCBSP2enabled)
Spare3 Spare2 Spare1 Spare0Resv
0Resv
0
McBSP1ON/OFF
BoardR/W
0(Onboard)
7MISC2
DSPARSTST(Reset Status)
Resv0
Resv0
Resv0
HURRSTEN
Ethernet PHYRST
CPUBEnable
CPUBPRSNT
Table 2: CPLD USER_REG Register
Bit Name R/W Description
7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)
6 USER_SW2 R User DIP Switch 2(1 = Off, 0 = On)
5 USER_SW1 R User DIP Switch 1(1 = Off, 0 = On)
4 USER_SW0 R User DIP Switch 0(1 = Off, 0 = On)
3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)
2 USER_LED2 R/W User-defined LED 2 Control (0 = Off, 1 = On)
1 USER_LED1 R/W User-defined LED 1 Control (0 = Off, 1 = On)
0 USER_LED0 R/W User-defined LED 0 Control (0 = Off, 1 = On)
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2-4 TMS320C6455 DSK Module Technical Reference
2.1.4 DC_REG Register
DC_REG is used to monitor and control the daughter card interface. DC_DET detectsthe presence of a daughter card. DC_STAT and DC_CNTL provide simplecommunications with the daughter card through readable status lines and writablecontrol lines.
The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.
2.1.5 VERSION Register
The VERSION register contains two read only fields that indicate the BOARD andCPLD versions. This register will allow your software to differentiate betweenproduction releases of the DSK and account for any variances. This register is notexpected to change often, if at all.
Table 3: DC_REG Register
Bit Name R/W Description
7 DC_DET R Daughter Card Detect (1= Board detected)
6 0 R Always 0
5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)
4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)
3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)
2 0 R Always zero
1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)
0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)
Table 4: Version Register Bit Definitions
Bit # Name R/W Description
7 CPLD_VER3 R Most Significant CPLD Version Bit
6 CPLD_VER2 R CPLD Version Bit
5 CPLD_VER1 R CPLD Version Bit
4 CPLD_VER0 R Least Significant CPLD Version Bit
3 0 R Always 0
2 DSK_VER2 R Most Significant DSK Board Version Bit
1 DSK_VER1 R DSK Board Version Bit
0 DSK_VER0 R Least Significant DSK Board Version Bit
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2.1.6 MISC Register
The MISC register is used to provide software control for miscellaneous boardfunctions. On the C6455 DSK, the MISC register controls how auxiliary signals arebrought out to the daughter-card connectors.
McBSP1 is usually used as the control and data port of the on-board AIC23 codec. The power-on state of this bit (0) represents that configuration. Set MCBSP0SEL toroute the McBSP1 to the daughter card connectors rather than the codec.
The scratch bits are unused. They can be set to any value.
Table 5: MISC Register
Bit Name R/W Description
7 Reserved R
6 Spare3 R Spare switch
5 Spare2 R Spare switch
4 Spare1 R Spare switch
3 Spare0 R Spare switch
2 Reserved R
1 Reserved R
0 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)
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2.1.7 MISC2 Register
MISC2 register is used for factory test and EVM functions when a C64xx AMCCmezzanine card is used.
This register also contains a bit for resetting the on board PHY.
Bits 0 and 1 are used for EVM configurations. Bit 0 is used to detect that a mezzaninecard is plugged into the AMCC slot which is not populated on a DSK. Bit 1 enables theAMCC mezzanine card. When driven to a zero the AMCC card is enabled.
Bit 3 provides a mechanism to reset the ethernet PHY. Writing as 1 resets the on boardethernet PHY.
Bits 4 and 7 are used for factory tests, and the remaining bits are reserved for futureuse.
Table 6: MISC2 Register
Bit Name R/W Description
7 DSPA RSTST W DSP A Reset Status (0 = Not in reset, 1 = In Reset), Factory Test
6 Reserved R Not Used
5 Reserved R Not Used
4 Reserved R Not Used
3 Reserved R User-defined LED 3 Control (0 = Off, 1 = On)
2 Ethernet PHY RST
R/W Ethernet PHY reset Enable (0 = Not Reset, 1 = Reset)
1 CPUB Enable W CPU B Reset (0 = Not Reset, 1 = Reset)
0 CPUB PRSNT R CPU B Present (0 = Not present, 1 = Present)
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2.2 AIC23 Codec
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for inputand output of audio signals. The codec samples analog signals on the microphone orline inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples backinto analog signals on the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internalconfiguration registers and one to send and receive digital audio samples. The
C6455’s I2C interface is used as the unidirectional control channel. The control channelis only used when configuring the codec, it is generally idle when audio data is beingtransmitted,
McBSP1 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The DSK examples generallyuse a 55-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side. Thepreferred serial format is DSP mode which is designed specifically to operate with theMcBSP ports on TI DSPs.
The codec has a 12MHz system clock. The 12MHz system clock corresponds to USBsample rate mode, named because many USB systems use a 12MHz clock and canuse the same clock for both the codec and USB controller. The internal sample rategenerate subdivides the 12MHz clock to generate common frequencies such as48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATEregister. The figure below shows the codec interface on the C6455 DSK.
Figure 2-1, TMS320C6455 DSK CODEC INTERFACE
MIC IN
LINE IN
LINE OUT
HP OUT
ADC
DAC
McBSP
DSP Format
0 LEFTINVOL1 RIGHTINVOL2 LEFTHPVOL3 RIGHTHPVOL4 ANAPATH5 DIGPATH6 POWERDOWN7 DIGIF8 SAMPLERATE9 DIGACT15 RESET
Con
trol
Reg
iste
rs
LRCINBCLK
DIN
DOUTLRCOUT
FSX
DX
CLKXFSR
CLKR
DR
AIC23 Codec
Digital Analog
MIC IN
LINE IN
LINE OUT
HP OUT
SCLKSDIN
I2CControlSCL
SDAI2C Format
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2-8 TMS320C6455 DSK Module Technical Reference
2.3 DDR2 Memory
The DSK uses a pair of industry standard 512 megabit DDR2 in CE0. The two devicesare used in parallel to create a 32-bit wide interface. Total available memory is128 megabytes, and is accessible from addresses 0xE0000 0000 to 0xE800 0000.
The DSK uses a factory setting DDR2 clock at 250 MHz. The integrated DDR2controller is started by configuring the EMIF in software. Timings can be found in theDDR2 data sheet and the DSK help file.
2.4 Flash Memory
The DSK uses a 4 Mbyte external Flash as a boot option. It is connected to CE3 ofEMIFA with an 8-bit interface, and is accessible from addresses 0xB0000 0000 to0xB01F FFFF. Flash is a type of memory which does not lose its contents when thepower is turned off. When read it looks like a simple asynchronous read-only memory(ROM). Flash can be erased in large blocks commonly referred to as sectors or pages. Once a block has been erased each word can be programmed once through a specialcommand sequence. After that the entire block must be erased again to change thecontents.
2.5 LEDs and DIP Switches
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) thatprovide the user a simple form of input/output. Both are accessed through the CPLDUSER_REG register.
2.6 Ethernet Interface
An Intel LTX971ACE 10/100 Mbps PHY is connected to the DSP’s internal EMACcontroller. There are 2 status LEDs which detail the status of the ethernet link.
2.7 I2C ROM
The DSK incorporates a 1 Mbit I2C ROM. The ROM can be used for general storageor configured as a boot device for the DSP.
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2.8 Daughter Card Interface
The DSK provides three expansion connectors that can be used to accept plug-indaughter cards. The daughter card allows users to build on their DSK platform toextend its capabilities and provide customer and application specific I/O. Theexpansion connectors are for memory, peripherals, and the Host Port Interface (HPI)
The memory connector provides access to the DSP’s asynchronous EMIF signals tointerface with memories and memory mapped devices. It supports byte addressing on32 bit boundaries. The peripheral connector brings out the DSP’s peripheral signalslike McBSPs, timers, and clocks. Both connectors provide power and ground to thedaughter card.
The HPI is a high speed interface that can be used to allow multiple DSPs tocommunicate and cooperate on a given task. The HPI connector brings out the HPIspecific control signals as well as a PCI multiplexed interface.
Most of the expansion connector signals are buffered so that the daughter card cannotdirectly influence the operation of the DSK board. The use of TI low voltage, 5V tolerantbuffers, and CBT interface devices allows the use of either +5V or +3.3V devices to beused on the daughter card.
Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET andDC_DET exist and are accessible through the CPLD DC_REG register. The DSKalso multiplexes the McBSP1 for on board or external use. This function is controlledthrough the CPLD MISC register.
2.9 DSP and EMIFA Clock Generation
The C6455 DSK uses the internal DSP divides to select the user PLL frequency, andmultiple oscillators. This allows the DSK to support 600, 725, 850, 1000, and 1200megahertz CPU clocks. However, the default configuration is 1 gigahertz and thesoftware shipped with the DSK assumes the default configuration.
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2-10 TMS320C6455 DSK Module Technical Reference
2.10 JTAG Interfaces
The DSK supports embedded emulation controller as its primary debug channel.However it has an option to support 14 pin and 60 pin TI style JTAG connections forexternal emulators. When either the 14 pin or 60 pin interface is plugged into the DSKthe on board embedded emulator is disabled. The 60 pin interface also supports tracefunctions when used with the appropriate trace emulation platform.
3-1
Chapter 3
Physical Description
This chapter describes the physical layout of the TMS320C6455 DSKand its connectors.
Topic Page
3.1 Board Layout 3-23.2 Connector Index 3-33.3 Expansion Connectors 3-33.3.1 J4, Memory Expansion Connector 3-43.3.2 J3, Peripheral Expansion Connector 3-53.3.3 J1, PCI Expansion Connector 3-63.3.4 J1, Used as HPI Expansion Connector 3-63.4 Audio Connectors 3-83.4.1 J1301, Microphone Connector 3-83.4.2 J1303, Audio Line In Connector 3-83.4.3 J1304, Audio Line Out Connector 3-93.4.4 J1302, Headphone Connector 3-93.5 Power Connectors 3-103.5.1 J5, +5 Volt Connector 3-103.5.2 J6, Optional Power Connector 3-103.6 Miscellaneous Connectors 3-113.6.1 J1201, USB Connector 3-113.6.2 J8, 14 Pin External JTAG Connector 3-123.6.3 J7, 60 Pin Advanced Emulation Connector 3-133.6.4 JP3, PLD Programming Connector 3-133.6.5 J9, AMCC Connector 3-133.6.6 P1102, Ethernet Connector 3-143.7 System LEDs 3-143.8 SW2, Reset Switch 3-14
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3-2 TMS320C6455 DSK Module Technical Reference
3.1 Board Layout
The C6455 DSK is a 10.0 x 4.5 inch (254 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6455 DSK.
Figure 3-1, TMS320C6455 DSK
J4
J5J6
J1302
J8SW1 SW2D7-10
J3 J1 J9J1304J1301 J1303
P1102 SW3 J7 J1201
JP3
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3.2 Connector Index
The TMS320C6455 DSK has many connectors which provide the user accessto the various signals on the DSK.
Note: “*” Not populated
3.3 Expansion Connectors
The TMS320C6455 DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.
The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profileconnectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectorsare designed for high speed interconnections because they have low propagationdelay, capacitance, and cross talk. The connectors present a small foot print on theDSK. Each connector includes multiple ground, +5V, and +3.3V power signals so thatthe daughter card can obtain power directly from the DSK. The peripheral expansionconnector additionally provides both +12V and -12V to the daughter card. Therecommended mating connector, whose part number is TFM-140-32-S-D-LC, is asurface mount connector that provides a 0.465” mated height.
Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
Table 1: TMS320C6455 DSK Connectors
Connector # Pins Function
J4 80 Memory
J3 80 Peripheral
J1 80 HPI
J1301 3 Microphone
J1303 3 Line In
J1304 3 Line Out
J1302 3 Headphone
J5 2 +5 Volt
J6 * 4 Optional Power Connector
J7 80 Enhanced JTAG Connector
J8 14 External JTAG
J1201 5 USB Port
JP3 4 CPLD Programming
P1102 8 Ethernet
SW3 8 DSP Configuration Switch
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3-4 TMS320C6455 DSK Module Technical Reference
3.3.1 J4, Memory Expansion Connector
Table 2: J4, Memory Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin
3 AEA19 O EMIF address pin 21 4 AEA18 O EMIF address pin 20
5 AEA17 O EMIF address pin 19 6 AEA16 O EMIF address pin 18
7 AEA15 O EMIF address pin 17 8 AEA14 O EMIF address pin 16
9 AEA13 O EMIF address pin 15 10 AEA12 O EMIF address pin 14
11 GND Vss System ground 12 GND Vss System ground
13 AEA11 O EMIF address pin 13 14 AEA10 O EMIF address pin 12
15 AEA9 O EMIF address pin 11 16 AEA8 O EMIF address pin 10
17 AEA7 O EMIF address pin 9 18 AEA6 O EMIF address pin 8
19 AEA5 O EMIF address pin 7 20 AEA4 O EMIF address pin 6
21 5V Vcc 5V voltage supply pin 22 5V Vcc 5V voltage supply pin
23 AEA3 O EMIF address pin 5 24 AEA2 O EMIF address pin 4
25 AEA1 O EMIF address pin 3 26 AEA0 O EMIF address pin 2
27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2
29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0
31 GND Vss System ground 32 GND Vss System ground
33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30
35 AED29 I/O EMIF data pin 29 36 AED28 I/O EMIF data pin 28
37 AED27 I/O EMIF data pin 27 38 AED26 I/O EMIF data pin 26
39 AED25 I/O EMIF data pin 25 40 AED24 I/O EMIF data pin 24
41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
43 AED23 I/O EMIF data pin 23 44 AED22 I/O EMIF data pin 22
45 AED21 I/O EMIF data pin 21 46 AED20 I/O EMIF data pin 20
47 AED19 I/O EMIF data pin 19 48 AED18 I/O EMIF data pin 18
49 AED17 I/O EMIF data pin 17 50 AED16 I/O EMIF data pin 16
51 GND Vss System ground 52 GND Vss System ground
53 AED15 I/O EMIF data pin 15 54 AED14 I/O EMIF data pin 14
55 AED13 I/O EMIF data pin 13 56 AED12 I/O EMIF data pin 12
57 AED11 I/O EMIF data pin 11 58 AED10 I/O EMIF data pin 10
59 AED9 I/O EMIF data pin 9 60 AED8 I/O EMIF data pin 8
61 GND Vss System ground 62 GND Vss System ground
63 AED7 I/O EMIF data pin 7 64 AED6 I/O EMIF data pin 6
65 AED5 I/O EMIF data pin 5 66 AED4 I/O EMIF data pin 4
67 AED3 I/O EMIF data pin 3 68 AED2 I/O EMIF data pin 2
69 AED1 I/O EMIF data pin 1 70 AED0 I/O EMIF data pin 0
71 GND Vss System ground 72 GND Vss System ground
73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable
75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready
77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2
79 GND Vss System ground 80 GND Vss System ground
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3.3.2 J3, Peripheral Expansion Connector
Table 3: J3, Peripheral Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin
3 GND Vss System ground 4 GND Vss System ground
5 5V Vcc 5V voltage supply pin 6 5V Vcc 5V voltage supply pin
7 GND Vss System ground 8 GND Vss System ground
9 5V Vcc 5V voltage supply pin 10 5V Vcc 5V voltage supply pin
11 N/C - No connect 12 N/C - No connect
13 N/C - No connect 14 N/C - No connect
15 N/C - No connect 16 N/C - No connect
17 N/C - No connect 18 N/C - No connect
19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin
21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source
23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data
25 GND Vss System ground 26 GND Vss System ground
27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect
29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data
31 GND Vss System ground 32 GND Vss System ground
33 CLKX2 I/O McBSP2 transmit clock 34 CLKS2 I McBSP2 clock source
35 FSX2 I/O McBSP2 transmit frame sync 36 DX2 O McBSP2 transmit data
37 GND Vss System ground 38 GND Vss System ground
39 CLKR2 I/O McBSP2 receive clock 40 N/C - No connect
41 FSR2 I/O McBSP2 receive frame sync 42 DR2 I McBSP2 receive data
43 GND Vss System ground 44 GND Vss System ground
45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input
47 N/C - No connect 48 EXT_INT5 I External interrupt 5
49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input
51 GND Vss System ground 52 GND Vss System ground
53 EXT_INT4 I External interrupt 4 54 N/C - No connect
55 N/C - No connect 56 N/C - No connect
57 N/C - No connect 58 N/C - No connect
59 RESET O System reset 60 N/C - No connect
61 GND Vss System ground 62 GND Vss System ground
63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control
65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status
67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7
69 ACE3# O Chip enable 3 70 N/C - No connect
71 N/C - No connect 72 N/C - No connect
73 N/C - No connect 74 N/C - No connect
75 DC_DET# Vss System ground 76 GND Vss System ground
77 GND Vss System ground 78 ECL KOUT O EMIF Clock
79 GND Vss System ground 80 GND Vss System ground
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3.3.3 J1, PCI Expansion Connector
Table 4: J1, PCI Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 PCI_EN I PCI enable 2 Resv N/C Resv
3 GND Vss System ground 4 HPI_RS# I HPI reset
5 Resv N/C Resv 6 Resv N/C Resv
7 GND Vss System ground 8 GND Vss System ground
9 AD1 I/O PCI address/data 1 10 GP[2] I/O General purpose I/O
11 AD3 I/O PCI address/data 3 12 AD0 I/O PCI address/data 0
13 AD5 I/O PCI address/data 5 14 AD2 I/O PCI address/data 2
15 AD7 I/O PCI address/data 7 16 AD4 I/O PCI address/data 4
17 GND System ground 18 AD6 I/O PCI address/data 6
19 AD8 I/O PCI address/data 8 20 GND Vss System ground
21 AD10 I/O PCI address/data 10 22 AD9 I/O PCI address/data 9
23 AD12 I/O PCI address/data 12 24 AD11 I/O PCI address/data 11
25 AD14 I/O PCI address/data 14 26 AD13 I/O PCI address/data 13
27 GND Vss System ground 28 AD15 I/O PCI address/data 15
29 PCBE1# I/O PCI command/byte ena 1 30 GND Vss System ground
31 GND Vss System ground 32 PPAR I/O PCI parity
33 PSERR# I/O PCI system error 34 GND Vss System ground
35 GND Vss System ground 36 PSTOP# I/O PCI stop
37 PPERR# I/O PCI parity error 38 GND Vss System ground
39 GND Vss System ground 40 Resv None
41 PDEVSEL# I/O PCI device select 42 GND Vss System ground
43 GND Vss System ground 44 PFRAME# I/O PCI Frame
45 PIRDY# I/O PCI initiator ready 46 GND Vss System ground
47 GND Vss System ground 48 AD16 I/O PCI address/data 16
49 PCBE2# I/O PCI command/byte ena 2 50 AD18 I/O PCI address/data 18
51 AD17 I/O PCI address/data 17 52 AD20 I/O PCI address/data 20
53 AD19 I/O PCI address/data 19 54 AD22 I/O PCI address/data 22
55 AD21 I/O PCI address/data 21 56 GND Vss System ground
57 AD23 I/O PCI address/data 23 58 Resv None
59 Resv None 60 AD24 I/O PCI address/data 24
61 GND Vss System ground 62 AD26 I/O PCI address/data 26
63 AD25 I/O PCI address/data 25 64 AD28 I/O PCI address/data 28
65 AD27 I/O PCI address/data 27 66 AD30 I/O PCI address/data 30
67 AD29 I/O PCI address/data 29 68 GP[12] I/O General purpose I/O
69 AD31 I/O PCI address/data 31 70 GND Vss System ground
71 GND Vss System ground 72 GP[13] I/O General purpose I/O
73 GP[15] I/O General purpose I/O 74 GND Vss System ground
75 GND Vss System ground 76 GP[14] I/O General purpose I/O
77 PCLK I PCI Clock 78 GND Vss System ground
79 GND Vss System ground 80 N/C - No connect
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3.3.4 J1, Used As HPI Expansion Connector
Table 5: J1, Used as HPI Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 PCI_EN I PCI enable 2 Resv N/C Resv
3 GND Vss System ground 4 HPI_RS# I HPI reset
5 Resv N/C Resv 6 Resv N/C Resv
7 GND Vss System ground 8 GND Vss System ground
9 HD1 I/O Host data 1 10 PCBE0# I/O PCI command/byte ena 0
11 HD3 I/O Host data 3 12 HD0 I/O Host data 0
13 HD5 I/O Host data 5 14 HD2 I/O Host data 2
15 HD7 I/O Host data 7 16 HD4 I/O Host data 4
17 GND System ground 18 HD6 I/O Host data 6
19 HD8 I/O Host data 8 20 GND Vss System ground
21 HD10 I/O Host data 10 22 HD9 I/O Host data 9
23 HD12 I/O Host data 12 24 HD11 I/O Host data 11
25 HD14 I/O Host data 14 26 HD13 I/O Host data 13
27 GND Vss System ground 28 HD15 I/O Host data 15
29 HDS2# I/O Host data strobe 2 30 GND Vss System ground
31 GND Vss System ground 32 HAS# I/O Host address strobe
33 HDS1# I/O Host data strobe 1 34 GND Vss System ground
35 GND Vss System ground 36 HCNTL0 I/O Host Control 0
37 HCS# I/O Host chip select 38 GND Vss System ground
39 GND Vss System ground 40 PTRDY# I/O PCI target ready
41 HCNTL1 I/O Host Control 1 42 GND Vss System ground
43 GND Vss System ground 44 HINT# I/O Host Interrupt
45 HRDY# I/O Host ready 46 GND Vss System ground
47 GND Vss System ground 48 HD16 I/O Host data 16
49 HR/W# I/O Host Read/Write 50 HD18 I/O Host data 18
51 HD17 I/O Host data 17 52 HD20 I/O Host data 20
53 HD19 I/O Host data 19 54 HD22 I/O Host data 22
55 HD21 I/O Host data 21 56 GND Vss System ground
57 HD23 I/O Host data 23 58 Resv Resv
59 Resv Resv 60 HD24 I/O Host data 24
61 GND Vss System ground 62 HD26 I/O Host data 26
63 HD25 I/O Host data 25 64 HD28 I/O Host data 28
65 HD27 I/O Host data 27 66 HD30 I/O Host data 30
67 HD29 I/O Host data 29 68 PGNT# I PCI bus grant
69 HD31 I/O Host data 31 70 GND Vss System ground
71 GND Vss System ground 72 Resv Resv
73 Resv Resv 74 GND Vss System ground
75 GND Vss System ground 76 Resv Resv
77 Resv Resv 78 GND Vss System ground
79 GND Vss System ground 80 N/C - No connect
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3-8 TMS320C6455 DSK Module Technical Reference
3.4 Audio Connectors
The C6455 DSK has 4 audio connectors. They are described in the followingsections.
3.4.1 J1301, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.
3.4.2 J1303, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
Microphone In
Ground
Figure 3-2, Microphone Stereo Jack
Microphone Bias
Left Line In
Ground
Figure 3-3, Audio Line In Stereo Jack
Right Line In
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3.4.3 J1304, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
3.4.4 J1302, Headphone Connector
Connector J1302 is a headphone/speaker jack. It can drive standard headphones or ahigh impedance speaker directly. The standard 3.5 mm jack is shown in the figurebelow.
Left Line Out
Ground
Figure 3-4, Audio Line Out Stereo Jack
Right Line Out
Left Headphone
Ground
Figure 3-5, Headphone Jack
Right Headphone
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3.5 Power Connectors
The C6455 DSK has 2 power connectors. They are described in the followingsections.
3.5.1 J5, +5 Volt Connector
Power (+5 volts) is brought onto the TMS320C6455 DSK via connector J5. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheA diagram of J5 is shown below.
3.5.2 J6, Optional Power Connector
Connector J6 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15109-0410 orTyco #174552-1. The table below shows the voltages on the respective pins.
Table 6: J6, Optional Power Connector
Pin # Voltage Level
1 +12 Volts
2 -12 Volts
3 Ground
4 +5 Volts
PC Board
J5+5V
Ground
Front ViewFigure 3-6, TMS320C6455 DSK Power Connector
WARNING !Do not plug into J5 and J6 at the same time.
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3.6 Miscellaneous Connectors
The C6455 DSK has 6 additional connectors to aid the user in developing with thisproduct. They are described in the following sections.
3.6.1 J1201, USB Connector
Connector J1201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.
Table 7: J1201, USB Connector
Pin # USB Signal Name
1 USBVdd
2 D+
3 D-
4 USB Vss
5 Shield
6 Shield
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3.6.2 J8, 14 Pin External JTAG Connector
The TMS320C6455 DSK is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown figure 3-6 below.
The signal names for each pin are shown in the table below.
Table 8: J8, JTAG Interface
Pin # Signal Name
1 TMS
2 TRST-
3 TDI
4 GND
5 PD
6 no pin
7 TDO
8 GND
9 TCK-RET
10 GND
11 TCK
12 GND
13 EMU0
14 EMU1
1 23 4
5 67 89 1011 1213 14
TMSTDI
PD (+3.3V)TDO
TCK-RET
TCKEMU0
TRST-GNDno pin (key)GNDGND
GNDEMU1
Header Dimensions
Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
Figure 3-7, JTAG INTERFACE
Spectrum Digital, Inc
3-13
3.6.3 J7, 60 Pin Advanced Emulation Connector
The 60 pin emulation connector is mounted on the side of the board near the 14 pinJTAG connector. This connector is for advanced emulation capability. The signals onthis connector are 4 columns by 15 rows as shown in the table below
3.6.4 JP3, PLD Programming Connector
This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.
3.6.5 J9, AMCC Connector
This connector provides a high speed Serial Rapid I/O to other platforms. Thisconnector has 170 pins. This connector is not populated on DSK platforms.
Table 9: J7, 60 Pin Emulation Connector
Row #Column A
Signal NameColumn B
Signal NameColumn C
Signal NameColumn D
Signal Name
1 Ground IDO ID2 Ground
2 Ground TMS EMU18 Ground
3 Ground EMU17 TRSTn Ground
4 Ground TDI EMU16 Ground
5 Ground EMU14 EMU15 Ground
6 Ground EMU12 EMU13 Ground
7 Ground TDO EMU11 Ground
8 TYPE0 TVD TCLKRTN TYPE1
9 Ground EMU9 EMU10 Ground
10 Ground EMU7 EMU8 Ground
11 Ground EMU5 EMU6 Ground
12 Ground TCLK EMU4 Ground
13 Ground EMU2 EMU3 Ground
14 Ground EMU0 EMU1 Ground
15 Ground ID1 ID3 Ground
Spectrum Digital, Inc
3-14 TMS320C6455 DSK Module Technical Reference
3.6.6 P1102, Ethernet Connector
Connector P1102 is a standard RJ-45 ethernet connector. The connector pin out isshown below.
3.7 System LEDs
TheTMS320C6455 DSK has six system light emitting diodes (LEDs). These LEDsindicate various conditions on the DSK. These function of each LED is shown in thetable below.
3.8 SW2, Reset Switch
There are three resets on the TMS320C6455 DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320C6455.
External sources which control the reset are push button SW2, and the on boardembedded USB JTAG emulator.
Table 10: P1102 Connector Pin Out
Pin # Signal Name
1 TXD+
2 TXD-
3 RXD+
4 TXD-CT
5 Not Used
6 RXD-
7 NC
8 Ground
Table 11: System LEDs
Reference Designator Color Function On Signal
State
D4 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.
1
D3 Green +5 Volt present 1
D6 Orange RESET Active 1
DS201 Green USB Active, Blinks during USB data transfer 1
DS1101 Yellow Ethernet status 0
DS1102 Green Ethernet Status 0
Spectrum Digital, Inc
A-2 TMS320C6455 DSK Module Technical Reference
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
C
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Mo
nd
ay,
Jun
e 2
6,
200
61
34
B
TM
S32
0C6
455
DS
K
Titl
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lock
SC
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MA
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CO
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EN
TS
:
1 C
OV
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SH
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T2
US
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OP
TIO
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3 C
lock
Inp
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4 6
45X
DD
R2
Inte
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DD
R2
Mem
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645
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MIF
A
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LD9
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SH
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MO
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10 6
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MII
INT
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FA
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11 M
CB
SP
INT
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12 6
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HO
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PO
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INT
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FA
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13 6
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SR
IO IN
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RF
AC
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DA
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RD
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645
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19 6
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EM
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RF
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20 E
MU
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INT
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21 H
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L B
LOC
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22 6
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RG
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23 6
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CO
UP
LIN
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AP
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24 6
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CO
UP
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25 P
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UT
26 A
IC23
CO
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C27
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PH
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DS
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29 D
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PO
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ES
II
30-3
4 E
mbe
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Em
ulat
ion
Not
Incl
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AA
AA
AA
AA
DATE
DATE
DATE
DATE
RLSE
ENGR-MGR
USED ON
QA
DATE
NEXT ASSY
APPLICATION
MFG
CHK
DATE
ENGR
DATE
DWN
R.R
.P.
R.R
.P.
T.M
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C.M
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R.R
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J.T
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AU
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1,2
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AU
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1,2
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AU
G 0
1,2
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AU
G 0
1,2
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AU
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C.M
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REV
SH
REV
SH
SH
REV
15
A 12
34
56
79
10
111
213
14
CC
AA
AA
A
AA
AA
AA
A
1617
1819
20
2123
2425
2627
2829
8AA
A
22
A
AA
REVISION STATUS OF SHEETS
Spectrum Digital, Inc
A-3
US
ER
_L
ED
1
US
ER
_L
ED
0
US
ER
_L
ED
3
US
ER
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ED
2
PW
B_R
EV
2
PW
B_R
EV
1
PW
B_R
EV
0
DS
P_
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LED
3.3
V
DG
ND
3.3
V
DG
ND
3.3
V
US
ER
_L
ED
28
US
ER
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ED
08
US
ER
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ED
18
US
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ED
38D
SP
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Sn_
LE
D8
US
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W3
8
US
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W1
8U
SE
R_
SW
08
US
ER
_S
W2
8
PW
B_R
EV
28
PW
B_R
EV
18
PW
B_R
EV
08
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
C
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Mo
nd
ay,
Ju
ne
26
, 2
00
62
34
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TM
S32
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455
DS
K
Op
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PA
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SW
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H
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D8
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25
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1 2 3 45678
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1KR
54
1K
R3
4N
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R5
3N
O-P
OP
Spectrum Digital, Inc
A-4 TMS320C6455 DSK Module Technical Reference
DS
PA
.CL
KIN
2
DS
PA
_E
MIF
A_
CLK
DS
P_E
MU
13D
SP
_EM
U12
DS
P_E
MU
14D
SP
_EM
U15
DS
P_E
MU
16D
SP
_EM
U17
DS
P_E
MU
18
DS
P_E
MU
2
DS
P_E
MU
5
DS
P_E
MU
9
DS
P_E
MU
3D
SP
_EM
U4
DS
P_E
MU
6D
SP
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U7
DS
P_E
MU
8
DS
P_E
MU
11D
SP
_EM
U10
DS
P_E
MU
1D
SP
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U0
DS
PA
_I2
C_S
DA
DS
PA
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C_
SC
L
DS
PA
.CL
KIN
1
DG
ND
3.3
V
DG
ND
DG
ND
3.3
V3
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3.3
V
DG
ND
DG
ND
3.3
V
DG
ND
DG
ND
3.3
V
3.3
V
DG
ND
DG
ND
EM
IF_P
LL_
CL
K8
DS
PA
_E
MIF
A_
CLK
6
DS
PA
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04
11D
SP
A.G
P0
511
DS
PA
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06
11D
SP
A.G
P0
711
DS
P_
EM
U1
19D
SP
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MU
219
DS
P_
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U3
19D
SP
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MU
419
DS
P_
EM
U5
19D
SP
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MU
619
DS
P_
EM
U7
19D
SP
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MU
819
DS
P_
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U9
19D
SP
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U1
019
DS
P_E
MU
11
19D
SP
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U1
219
DS
P_E
MU
13
19D
SP
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U1
419
DS
P_E
MU
18
19D
SP
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U1
719
DS
P_E
MU
16
19D
SP
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U1
519
DS
PA
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9,2
0
DS
P_
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19
DS
PA
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C_
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DS
PA
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C_
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A9
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DS
PA
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Tz
8
DS
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9,2
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9,2
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PA
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9,20
HU
R_
TC
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0
DS
PA
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KR
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DS
PA
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KX
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DS
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A.F
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111
DS
PA
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11
DS
PA
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011
DS
PA
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UT
111
DS
PA
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P1
11
DS
PA
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P0
11
DS
PA
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TS
TA
Tn
8
DS
PA
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Rz
8
HU
R_
TC
KR
TN
19
,20
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
Sh
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of
Titl
e:
Pa
ge
Co
nte
nts
:
C
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Th
urs
da
y, J
un
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2,
20
06
334
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TM
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CK
IN
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S1
S0
00
0 0
0 01 1
111
OP
EN
OP
EN
OP
EN
OP
EN
OP
EN
OP
EN
1
100
MH
z
125
MH
z
133.25 MHz
62.5 MHz
50 MHz
83.25 MHz
150 MHz
75 MHz
200 MHz
MU
LT
IPL
YOUTPUT
3X
5.33X
8X
2.5X
3.33X
6X
2X
4X
5X
Ru
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all
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HU
R_T
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MH
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OF
Fn
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R9
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0
C1
380
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C1
330
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8
25
MH
z
OF
Fn
1
GN
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CLK
3
R6
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K
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R4
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R1
211
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C1
340
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U1
0C
tmx3
20
c64
55z
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CLK
R1/
GP
[0]
AF
4
EM
U9
AH
13
NM
IA
H4
EM
U8
AF
11E
MU
7A
F12
EM
U6
AG
8E
MU
5A
E12
CLK
IN2
G3
EM
U4
AF
9
CLK
IN1
N28
EM
U3
AF
10E
MU
2A
G9
EM
U1
AE
11E
MU
0A
F7
TR
ST
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H7
TD
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TM
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[6]
AG
3
EM
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AE
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TD
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AH
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MU
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U14
AF
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MU
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D8
EM
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AE
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MU
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D12
EM
U10
AD
10
DR
1/G
P[8
]A
H5
FS
R1/
GP
[10]
AE
5
PO
R*
AF
14
SD
AA
F26
CLK
X1/
GP
[3]
AF
5
DX
1/G
P[9
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UT
L1L
AG
7
TO
UT
L0A
F8
GP
[5]
AJ2
TC
KA
J9
RE
SE
T*
AG
14
FS
X1/
GP
[11]
AG
4
SC
LA
G26
TIN
PL1
AJ6
SY
SC
LK3/
GP
[1]
AJ1
3
TIN
PL0
AH
6
RE
SE
TS
TA
T*
AE
14
GP
[4]
AH
2
GP
[7]
AG
2
C1
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L10
Fe
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R4
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R1
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2
C1
37
0.1
R4
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R4
81
NO
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U3
1
ICS
51
2
X1/
CLK
1
VD
D2
GN
D3
RE
F4
CLK
5
S0
6
S1
7
X2
8
TP
111
R4
09
0
R41
233
R4
11
NO
-PO
P
L7
BLM
21P
221S
N
L9
Fe
rrite
Chi
p
R6
310
K
Spectrum Digital, Inc
A-5
DS
PA
_T
BE
CLK
OU
TP
DS
PA
_TB
EC
LKO
UT
N
DS
PA
_T
BE
A1
0
DS
PA
_T
BC
Ez
DS
PA
_T
BE
A1
2D
SP
A_
TB
EA
13
DS
PA
_T
BE
A7
DS
PA
_T
BE
A8
DS
PA
_T
BE
A1
DS
PA
_T
BE
A2
DS
PA
_T
BE
A1
1
DS
PA
_G
AT
E0_
1
DS
PA
_G
AT
E2_
3
DS
PA
_TB
SD
CA
Sz
DS
PA
_T
BE
A6
DS
PA
_T
BE
A5
DS
PA
_T
BE
A4
DS
PA
_T
BE
A3
DS
PA
_T
BE
A0
DS
PA
_T
BE
A9
DS
PA
_TB
SD
CK
Ez
DS
PA
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BS
DW
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DS
PA
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BB
A2
DS
PA
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BB
A1
DS
PA
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SD
RA
Sz
DS
PA
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BB
A0
DS
PA
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SD
DQ
M2
DS
PA
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SD
DQ
M3
DS
PA
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SD
DQ
M0
DS
PA
_TB
SD
DQ
M1
DS
PA
_T
BE
D2
4D
SP
A_
TB
ED
25
DS
PA
_T
BE
D2
6D
SP
A_
TB
ED
27
DS
PA
_T
BE
D2
8D
SP
A_
TB
ED
29
DS
PA
_T
BE
D3
0D
SP
A_
TB
ED
31
DS
PA
_T
BE
D1
6D
SP
A_
TB
ED
17
DS
PA
_T
BE
D1
8D
SP
A_
TB
ED
19
DS
PA
_T
BE
D2
0D
SP
A_
TB
ED
21
DS
PA
_T
BE
D2
2D
SP
A_
TB
ED
23
DS
PA
_TB
ED
0
DS
PA
_T
BE
D1
0D
SP
A_
TB
ED
11
DS
PA
_T
BE
D1
2D
SP
A_
TB
ED
13
DS
PA
_T
BE
D1
4D
SP
A_
TB
ED
15
DS
PA
_TB
ED
1D
SP
A_T
BE
D2
DS
PA
_TB
ED
3D
SP
A_T
BE
D4
DS
PA
_TB
ED
5D
SP
A_T
BE
D6
DS
PA
_TB
ED
7D
SP
A_T
BE
D8
DS
PA
_TB
ED
9
DS
PA
_T
BE
D[0
:31
]
DS
PA
_T
BB
A[0
:2]
5
DS
PA
_T
BC
Ez
5
DS
PA
_T
BS
DC
AS
z5
DS
PA
_T
BS
DW
Ez
5
DS
PA
_T
BS
DC
KE
z5
DS
PA
_T
BE
CLK
OU
TP
5D
SP
A_T
BE
CLK
OU
TN
5
DS
PA
_T
BE
A[0
:13]
5
DS
PA
_T
BS
DR
AS
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DS
PA
_T
BD
DQ
M0
5D
SP
A_
TB
DD
QM
15
DS
PA
_T
BD
DQ
M2
5D
SP
A_
TB
DD
QM
35
DS
PA
_T
BS
DD
QS
0P
5
DS
PA
_T
BS
DD
QS
3N
5
DS
PA
_T
BS
DD
QS
1P
5
DS
PA
_T
BS
DD
QS
2P
5
DS
PA
_T
BS
DD
QS
3P
5
DS
PA
_T
BS
DD
QS
0N
5
DS
PA
_T
BS
DD
QS
1N
5
DS
PA
_T
BS
DD
QS
2N
5
DS
PA
_T
BE
D[0
:31
]5
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
Sh
ee
to
f
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-
0001
Thur
sday
, Sep
tem
ber 2
1, 2
006
434
B
TM
S32
0C
64
55 D
SK
64
55
DD
R I
nte
rfa
ce
NOTE: DSDDQGATE0 signals needs to route
to DDR memories near D15-D0 and back to DSDDQGATE1.
NOTE: DSDDQGATE2 signals needs to route
to DDR memories near D31-D16 and back to DSDDQGATE3.
U1
0B
tmx3
20
c64
55zt
z
DS
DR
AS
*C
13
DE
D21
B21
DE
D20
A21
DE
A9
C16
DE
A8
D16
DE
D9
D9
DE
A7
B17
DE
A6
C17
DE
D8
C9
DE
A5
D17
DE
D7
D10
DE
A4
E17
DE
D6
C10
DE
A3
A18
DE
D5
B10
DE
A2
B18
DE
D4
A10
DE
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Spectrum Digital, Inc
A-8 TMS320C6455 DSK Module Technical Reference
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PIN
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PIN
99
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1313
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1414
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PIN
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1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
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2424
PIN
2525
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PIN
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PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
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3535
PIN
3636
PIN
3737
GNDINT1 38
VCCINT139
PIN
4040
PIN
4141
PIN
4242
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PIN
4444
PIN
4545
PIN
4646
PIN
4747
PIN
4848
PIN
4949
PIN
5050
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PIN
5252
GNDIO5 53
PIN
5454
PIN
5555
PIN
5656
PIN
5757
PIN
5858
GNDIO6 59
PIN
6060
PIN
6161
TC
K62
PIN
6363
PIN
6464
GNDIO7 65
VCCIO566
PIN
6767
PIN
6868
PIN
6969
PIN
7070
PIN
7171
PIN
7272
TD
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GNDIO8 74
PIN
7575
PIN
7676
PIN
7777
GNDIO9 78
PIN
7979
PIN
8080
PIN
8181
VCCIO682
PIN
8383
PIN
8484
PIN
8585
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IN/G
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187
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9292
PIN
9393
PIN
9494
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PIN
9696
PIN
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PIN
9898
PIN
9999
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100
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Spectrum Digital, Inc
A-10 TMS320C6455 DSK Module Technical Reference
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A-14 TMS320C6455 DSK Module Technical Reference
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A-16 TMS320C6455 DSK Module Technical Reference
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Spectrum Digital, Inc
A-18 TMS320C6455 DSK Module Technical Reference
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A-19
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0.1
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0.1
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0.1
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5
560
pF
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60
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4
560
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40
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4
56
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70
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59
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3
56
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560
pF
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90
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0.1
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50
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192
470
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60
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50
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193
47
0uF
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2
56
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60
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470
uF
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560
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120
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100
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80
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191
47
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C2
550
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60
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79
0.1
Spectrum Digital, Inc
A-24 TMS320C6455 DSK Module Technical Reference
VC
C_
1.5
V
DV
DD
_1
.8V
SR
IO_
VC
C1.
2
DG
ND
DG
ND
DG
ND
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
She
et
of
Titl
e:
Pa
ge
Con
ten
ts:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Mo
nd
ay,
Ju
ne 2
6,
200
623
34
B
TM
S32
0C
645
5 D
SK
De
cou
plin
g C
ap
s II
7
20
9
C2
36
560
pF
C2
03
0.1
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C2
21
0.1
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C2
12
560
pF
C2
04
0.1
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C19
8
0.1
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C2
23
0.1
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C2
37
560
pF
C1
97
0.1
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C2
13
560
pF
C2
05
0.1
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C2
20
0.1
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C2
22
0.1
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C23
8
560
pF
+C
196
47
0uF
C21
4
56
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C20
6
0.1
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C2
25
0.1
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C2
31
0.1
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C2
15
56
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C2
07
0.1
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C22
4
0.1
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C2
33
0.1
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C1
99
0.1
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19
54
70u
FC
216
560
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08
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C2
26
56
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217
10
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C2
32
0.1
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C2
00
0.1
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C2
09
56
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C2
28
56
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C2
35
560
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C2
01
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229
10u
F
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21
9
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F
C21
0
56
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34
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C20
2
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C22
7
56
0pF
+C
218
10
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C2
11
56
0pF
+C
23
0
10
uF
Spectrum Digital, Inc
A-25
5V
-12V
12V
DG
ND
DG
ND
DG
ND
DG
ND
3.3
V
DG
ND
DG
ND
DG
ND
3.3
V
DG
ND
PU
SH
B_
RS
n21
PU
SH
B_
RS
8
Siz
e:
Da
te:
DW
G N
OR
ev
isio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Mo
nd
ay,
Jun
e 2
6,
200
624
34
B
TM
S32
0C6
455
DS
K
Po
we
r In
put
0.0
25
OH
MS
FO
R P
OW
ER
ME
AS
UR
EM
EN
T
WARNING:
DO NOT SUPPLY POWER TO BOTH
POWER CONNECTORS AT THE
SAME TIME!
TO
BE
PO
PU
LAT
ED
BY
TH
E U
SE
R I
F
NE
ED
ED
.
Mo
lex
15-2
4-4
041
2.5
MM
JA
CK
PO
WE
R IN
PUT
SY
ST
EM
PO
WE
R M
EA
SU
RE
ME
NT
PO
INT
S.
R I
S 2
51
2 B
OD
Y,
6 V
IAS
FR
OM
PA
D T
O P
LA
NE
DA
UG
HTE
RC
AR
D S
TAN
DO
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RO
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DIN
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EP
TR
AC
ES
A M
INIM
UM
OF
0.0
70
IN
CH
ES
FR
OM
TH
ES
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ES
.
RE
SE
T
TP
71
C1
19
0.1
uF
TP
81
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NO
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P
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1-1
22
GN
D3
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4
JP4
NO
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P
12
M4
12
5_P
H
TP
91
M2
125
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TP
32
TP
R5
222
0
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5
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74
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TP
31
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414
8
13
TP
41
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N
TP
51
R8
41
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TP
61
SW
2
PU
SH
BU
TT
ON
AA
AB
BB
R9
90
Spectrum Digital, Inc
A-26 TMS320C6455 DSK Module Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
LL
INE
_O
UT
RL
INE
_O
UT
AIC
23
LR
CIN
AIC
23C
S
AIC
23
CLK
AIC
23
CL
K
CT
L_C
LK
3,9
,14
CT
L_C
S21
CT
L_D
AT
A3
,9,1
4
DA
TA
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IN11 D
AT
A_S
YN
CIN
11D
AT
A_B
CL
K1
1D
AT
A_D
OU
T1
1
DA
TA
_S
YN
CO
UT
11
AIC
3.3
V1
5,1
7,1
8,2
0,2
1,2
6,2
8,3
2
GN
D3
,15
,19
,20
,21
,24
,26
,27
,28
,30,
32,3
4
CT
L_M
OD
E21
CO
DE
C_
SY
SC
LK
21
3.3
VA
3.3
VA
AIC
3.3
V
AIC
3.3
V
AIC
3.3
V
AIC
3.3
VA
IC3
.3V
DG
ND
DG
ND
AIC
3.3
V
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Fri
da
y, M
ay
19
, 2
00
625
34
B
TM
S32
0C
6455
DS
K
Aic
23
Au
dio
Con
tro
l Po
rt
J13
03
Lin
e I
n
3 4 2 1C
1334
470
nF
R1
342
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338
470
nF
C13
41
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0510
0
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04
Lin
e O
ut
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29N
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OP
+
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315
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F
R13
364
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374.
7K
+
C1
325
10
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R1
328
NO
PO
PC
132
20
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F
R1
343
0
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0410
0
C13
16
NO
PO
P
C1
344
NO
PO
P
L13
06B
LM21
P22
1S
N
L13
04B
LM
21
P22
1SN
L130
9B
LM2
1P22
1SN
PW Package
U13
07 TLV
320
AIC
23
MO
DE
22
AV
dd14
HP
GN
D11
AG
ND
15
XT
I/MC
LK25
BC
LK3
DIN
4
LRC
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CS
21
SC
LK24
SD
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RH
PO
UT
10
LHP
OU
T9
DG
ND
28
VM
ID16
MIC
_BIA
S17
MIC
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18
LLIN
E_I
N20
RLI
NE
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19
XT
O26
RLI
NE
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T13
LLIN
E_O
UT
12
HP
Vdd
8
BV
dd1
DO
UT
6
LRC
OU
T7
CLK
OU
T2
DV
dd27
R13
270
R1
340
100
R1
344
2.2
RN
13
14
10K
1 2 3 45678
L13
03B
LM
21P
221S
N
C1
336
NO
PO
P
L13
02B
LM
21P
221S
N
+
C1
347
10u
F
L13
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LM21
P22
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N
C1
337
470
nF
C13
334
70nF
R1
332
47K
RN
13
15
10K
1 2 3 45678
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01
Mic
rop
hon
e In
3 4 2 1
R1
345
33
R1
333
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L131
8
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N
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02
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ho
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323
220
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341
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+
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311
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C13
30
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PO
P R1
335
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K
+
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19
10
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1326
0.1
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C1
350
0.1
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R1
339
100
R1
334
4.7
K
R1
326
4.7
K
R1
325
2.2
K
C13
27
NO
PO
P
+C1
324
220
uF
C1
345
NO
PO
P
C1
340
NO
PO
P
C13
39
NO
PO
P
C1
317
NO
PO
PC
132
1
47
pF
C1
320
NO
PO
P
L130
1H
Z08
05
E6
01R
RN
13
16
33
1 2 3 45678
C1
318
NO
PO
P
U13
01
12
MH
z
OF
Fn
1
GN
D2
VC
C4
CLK
3
L13
05B
LM
21
P22
1SN
L130
8B
LM
21P
221
SN
C1
328
NO
PO
P
+
C1
346
10u
F
C1
335
NO
PO
P
R1
312
0
R13
310
R1
338
0
+
C1
343
10
uF
C1
332
0.1
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C13
42
0.1
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Spectrum Digital, Inc
A-27
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
LX
T_R
DM
LXT_TDCT
LXT
_TD
P
T_M
II_R
XD
V
T_
MII
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RS
T_
MII_
MD
IO
T_M
II_R
XD
3
T_M
II_
RC
LK
RB
IAS
T_M
II_R
DX
2MII_
MT
XD
3LX
T_R
DP
_c
T_M
II_R
XD
1MII_
MT
XE
N
MII_
MT
XD
2M
II_M
TX
D1
LXT
_R
DM
_c
T_M
II_R
XD
0
T_M
DIN
T_T
P
MII_
MT
XD
0
PW
RD
WN
SLE
EP
MII_
MT
XE
RR
T_M
II_C
OL
T_M
II_R
XE
R
T_M
II_M
DC
LK
PA
US
ETX
SLE
W1
TXS
LEW
0
LIN
KL
ED
-
LE
D1-
LXT
_TD
M
PW
RD
WN
SL
EE
PP
AU
SE
TX
SLE
W1
TX
SLE
W0
LE
D1
-
LIN
KL
ED
-
LXT
_R
DP
LE
D1
-
LIN
KL
ED
-
MII_
TX
EN
10
MII_
TX
CLK
10
MII
_TX
ER
R21
MII_
TX
D0
10
MII_
TX
D1
10
MII_
TX
D2
10
MII_
TX
D3
10
MII
_C
OL
10
MII
_R
XC
LK
10
MII
_R
XE
RR
10
MII
_C
RS
10
MII
_R
XD
V10
MII
_RE
SE
T8
MII
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DIO
10M
II_M
DC
10
MII
_R
XD
210
MII
_R
XD
010
MII
_R
XD
310
MII
_R
XD
110
PH
Y_3
.3V
15,
17
,18
,20
,21
,25
,28,
32
PH
Y_G
ND
3,1
5,1
9,2
0,2
1,2
4,2
5,2
7,2
8,3
0,32
,34
AV
CC
3.3
AV
CC
3.3
AV
CC
3.3
VC
C_
3.3V
VC
C_
3.3
V
VC
C_
3.3
V
VC
C_3
.3V
VC
C_
3.3
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VC
C_
3.3
V
VC
C_
3.3
V
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Th
urs
day
, Ju
ne
22
, 2
006
2634
B
TM
S32
0C
6455
DS
K
ET
HE
RN
ET
IN
TE
RF
AC
E
DUPLEX
STATUS
COLLISION/
LINK/
SPEED
ACTIVITY
Ro
ute
pai
rs t
oget
her
,p
airs
are
(3 a
nd
6)
and
(1 a
nd
2).
Pla
ce te
rmin
atio
ns
clo
se to
PH
Y s
ou
rce
pin
s.
YE
LL
OW
LE
D I
S O
N L
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GR
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IS
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HT
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R11
07
22
C11
761
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RN
11
01
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AC
K4-
33
12345 6 7 8
D11
01
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OW
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R11
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OP
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1E
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100
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171
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115
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02
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21
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17
GN
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TX
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1
TX
D-
2
RX
D+
3
RX
D-
6R
XD
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5
S0 14S1 13
LED
1+9
LED
1-10
LED
2-12
LED
2+11
C1
163
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F
R1
109
0
R11
821
0k
L115
7
BLM
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G2
21S
N1D
12
C11
73
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F
R1
184
22
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C11
670
.01
uF
R1
101
22
R11
7510
0
R11
890
R11
04
22
C11
690
.01
uF
R11
781
0k
R11
02
0E
IA04
02
R11
05
22
R1
158
49.9
C11
781
0pF
L115
6
BLM
21P
G2
21S
N1D
12
C1
166
.1u
F
U11
58
LXT
971A
LE
TX
_CLK
55
TX
D0
57
TX
D1
58
TX
D2
59
TX
D3
60
TX
_EN
56
TX
_ER
54
CO
L62
CR
S63
RX
_CLK
52
RX
D0
48
RX
D1
47
RX
D2
46
RX
D3
45
RX
_DV
49
RX
_ER
53
MD
DIS
3
MD
C43
MD
IO42
MD
INT
#64
TD
I27
TD
O28
TP
FO
P19
TP
FO
N20
TP
FIP
23
TP
FIN
24
LED
/CF
G1
38
LED
/CF
G2
37
LED
/CF
G3
36
AD
DR
012
AD
DR
113
AD
DR
214
AD
DR
315
AD
DR
416
XO
2R
EF
CLK
/XI
1
PW
RD
WN
39
RB
IAS
17
TE
ST
135
RE
SE
T#
4
TE
ST
034
VC
CA
22
GN
D25
SD
/TP
#26
GND1 7
GND2 11
GND3 18
GND4 41
GND5 50
GND6 61
VCCD51
VCCIO18
VCCIO240
VCCA21
TM
S29
TC
K30
TR
ST
#31
TxS
LEW
05
TxS
LEW
16
PA
US
E33
SLE
EP
32
N/C
19
N/C
210
N/C
344
C11
74
270
pF
R11
81N
O P
OP
R11
08
22
R1
188
49.9
R1
177
100
R11
03
0E
IA04
02
R11
87
10k
R11
831
0k
Spectrum Digital, Inc
A-28 TMS320C6455 DSK Module Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
+5_
VO
LTS
GR
OU
ND
3,1
5,1
9,2
0,2
1,2
4,2
5,2
6,2
8,30
,32
,34
VC
C_
1.8
V17
,18
VC
C_
1.5
VIO
17,1
8
VC
C_
1.2
SR
IO17
RE
SE
T_
SW
21
PS
_P
OR
z8
VC
C_
1.8
V
AG
ND
VC
C_
5V
1.5
VIO
VC
C_
1.8
V
VC
C_
5V
VC
C_
5V
VC
C_
1.8
V
VC
C_
1.2
SR
IO
VC
C_
1.8
V
VC
C_
5V
VIO
_3
.3V
CC
_5V
VC
C_5
V
VC
C_
5V
VC
C_
5V
VC
C_
1.8
V1
.5V
IOV
CC
_1
.2S
RIO
PG
_1
.2V
28P
G_
3.3
V28
PG
_1.2
V2
8
SY
NC
_S
128
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Fri
da
y, M
ay
19
, 2
00
627
34
B
TM
S32
0C
6455
DS
K
PO
WE
R S
UP
PL
Y
3.3 sq in AGND,
min
thermal pad
Connect
at pin
1
1.2
VO
LT
SE
NS
E
1.5
VO
LT
SE
NS
E
L703
4.7
uH
R7
161
0K
1%
R71
71
0K
1%
C7
312
200
pF
C7
36
0.1
uF
C74
0
NO
-PO
P
C7
430
.1uF
R8
02
10K
C7
95
0.1
uF
C7
98
0.1
uF
C7
41
10
uF
U7
08B
74
HC
21P
W
9 128
10 13
11
R7
24
10K
U7
03
TP
S54
610P
WP
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
115
PG
ND
216
PG
ND
317
VIN
120
VIN
221
VIN
322
VB
IAS
25
SS
/EN
A26
SY
NC
27R
T28
PWRPAD 29
PH
611
PH
712
PH
813
PH
914
PG
ND
418
PG
ND
519
VIN
423
VIN
524
L70
7B
LM41
P75
0SP
T
+
C7
381
00
uF
R7
90
10K
+
C7
25
10
0u
F
+C
710
33
0uF
U7
09
UC
385
TD
KT
TT
-AD
J
VO
UT
4
GN
D.1
3
VB
1
VIN
2
GN
D.2
6
AD
J5
R7
18
9.7
6K
1%
C7
290
.04
7uF
C73
4
1u
F
C7
27
3300
pF
+
C7
301
00
uF
R7
61
0
TP
704
1
R8
041
0K
C7
990
.1u
F
C7
440
.1u
F
U7
08A
74
HC
21P
W
1 46
14 7
2 5
3
C7
33
0.0
39
uF
TP
703
1
C7
09
.1u
F
R7
218
.06
K 1
%
U7
07T
PS
736
15D
RB
OU
T1
EN
5
IN8
NC
.37
NC
.26
NC
.12
FB
3G
ND
4
PWRPAD 9
R7
23N
O-P
OP
L70
4B
LM41
P75
0SP
T
C73
9
NO
-PO
P
R8
00
10K
U7
05
TP
S38
08
G01
DB
VR
VD
D6
MR
3
SE
NS
E1
5
CT
4
GN
D2
RE
SE
T1
R8
03
10K
+C
728
10
uF
LE
SR
R7
20N
O-P
OP
C7
35
1u
F
R8
01
10K
C7
420
.1u
F
R8
051
0K
R7
9110
K
U7
04
TP
S38
08G
01D
BV
R
VD
D6
MR
3
SE
NS
E1
5
CT
4
GN
D2
RE
SE
T1
C7
46
10
uF
R7
09
71
.5K
1%
TP
705
1
C73
7
NO
-PO
P
R7
99
NO
-PO
P
U7
06
TP
S38
08
G01
DB
VR
VD
D6
MR
3
SE
NS
E1
5
CT
4
GN
D2
RE
SE
T1
R7
9710
K
R71
93
83
1%
R7
221
0K
1%
C7
26
120p
F
C7
32
NO
-PO
P
R7
29
0
Spectrum Digital, Inc
A-29
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
VIO
_1.
2V17
,18
VIO
_3.
3V15
,17
,18
,20
,21
,25
VIO
_1.2
V
AG
ND
VC
C_
5V
VIO
_3.
3
AG
ND
VC
C_
5V
VC
C_5
V
VIO
_3
.3V
IO_
1.2
V
PG
_1.2
V27
PG
_3
.3V
27
SY
NC
_S
127
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5085
52-0
001
Fri
da
y, M
ay
19
, 2
00
628
34
B
TM
S32
0C
6455
DS
K
PO
WE
R S
UP
PL
Y
3.3 sq in AGND,
minthermal pad
Connect
at pin
1
3.3 sq in AGND,
minthermal pad
Connect
at pin
1
C70
2
.1u
F
+
C7
03
33
0uF
R78
51
0K
1%
C72
43
300
pF
C7
171
00p
F
L705
BLM
41P
750S
PT
R70
2
71
.5K
1%
R7
30N
O-P
OP
C7
06
0.0
39
uF
TP
702
1
+
C7
08
330
uF
R7
04N
O-P
OP
R7
82
NO
-PO
P
R7
073
.74
K 1
%
U7
02T
PS
5461
0PW
P
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
115
PG
ND
216
PG
ND
317
VIN
120
VIN
221
VIN
322
VB
IAS
25
SS
/EN
A26
SY
NC
27R
T28
PWRPAD 29
PH
611
PH
712
PH
813
PH
914
PG
ND
418
PG
ND
519
VIN
423
VIN
524
R7
111
9.6
K 1
%
C7
13N
O-P
OP
C7
23
100
0pF
R7
77
21
.5K
1% C7
14N
O-P
OP
C7
840
.1u
F
R7
15
10K
1%
R7
08
28
.7K
1%
+C
70
5
10u
F L
ES
R
+
C72
01
00
uF
+
C72
21
00
uF
R7
270
C7
07
0.0
39
uF
C7
835
60pF
+C
72
1
100
uF
R7
01
71
.5K
1%
L70
6B
LM41
P7
50S
PT
C7
181
500p
F
C7
65
0.1
uF
L70
24
.7 u
H
R7
121
.3K
1%
C70
4
.1u
F
L701
4.7
uH
+C
719
100
uF
R7
136
98
1%
C7
12
0.0
47
uF D7
01N
O-P
OP
+C
70
1
10
uF
LE
SR
C7
110
.04
7uF
TP
701
1
L70
9B
LM41
P7
50S
PT
C7
87
0.1
uF
L708
BLM
41P
750S
PT
C7
154
7p
F
C7
860
.1u
F
R7
280
U7
01
TP
S54
110P
WP
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
111
PG
ND
212
PG
ND
313
VIN
114
VIN
215
VIN
316
VB
IAS
17S
S/E
NA
18S
YN
C19
RT
20P
OW
ER
PA
D21
R70
5N
O-P
OP
R7
06
NO
-PO
P
R7
031
0K
1%
R71
41
0K
1%
B-1
Appendix B
Mechanical Information
This appendix contains the mechanical information about theTMS320C6455 DSK produced by Spectrum Digital.
Spectrum Digital, Inc
B-2 TMS320C6455 DSK Module Technical Reference
TH
IS D
RA
WIN
G IS
NO
T T
O S
CA
LE