Experiment #1 Sequential Ckt

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Polytechnic University of PhilippinesCollege of Engineering

Computer Engineering Department

COEN 3174

Advanced Logic Circuits Design

Sequential Circuit

BSCOE 4-1

T/F 7:30-10:30 AM

Alangcao, Aldren A.Clavio, Sarah Jane P.

Espallardo, Aaron Kevin V.Muya, Mark Anthony D.San Diego, Khrystal T.

Date Performed: October 13, 2012Date Submitted: October 13, 2012

Engr. Remedios G. Ado


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Design a 3-bit Binary Counter Using JK (74LS76) & D (74LS74) Flip-flop.

The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following

character of the clocked D flip-flop but has two inputs, traditionally labeled J and K. If J and

K are different then the output Q takes the value of J at the next clock edge. If J and K are

both low then no change occurs. If J and K are both high at the clock edge, then the output

will toggle from one state to the other. It can perform the functions of the set/reset flip-flop

and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to

accomplish toggling action if J and K are tied together. This toggle application finds

extensive use in binary counters.

The 76 contains two independent J-K flip-flops with individual J-K, clock, preset, and

clear inputs. The 76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master

while the clock is high and transferred to the slave on the high-to-low transition. For these

devices the J and K inputs must be stable while the clock is high.

Clear Flip-flopPrevious Stateusing RESET

Switch

Clock triggersFlip-flops Count


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The SN5476 and the SN54LS76A are characterized for operation over the full military

temperature range of -55C to 125C. The SN7476 and SN74LS76A is characterized for

operation from 0C to 70C.

The D flip-flop tracks the input, making transitions with match those of the input D. The D

stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of

as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to

the reset through an inverter. The result may be clocked.


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The LM555 is a highly stable device for

generating accurate time delays or oscillation.

Additional terminals are provided for triggering or

resetting if desired. In the time delay mode of

operation, the time is precisely controlled by one

external resistor and capacitor. For astable operation

as an oscillator, the free running frequency and duty

cycle are accurately controlled with two external

resistors and one capacitor. The circuit may be

triggered and reset on falling waveforms, and the

output circuit can source or sink up to 200mA or drive TTL circuits.

The 46A and 47A feature active-low outputs designed for

driving common-anode LEDs or incandescent indicators directly.

All of the circuits have full ripple-blanking input/output controls

and a lamp test input. Segment identification and resultant

displays are shown on a following page. Display patterns for BCD

input counts above nine are unique symbols to authenticate input

conditions.

All of the circuits incorporate automatic leading and/or trailing-

edge, zero-blanking control (RBI and RBO). Lamp test (LT) of

these devices may be performed at any time when the BI/RBO

node is at a high logic level. All types contain an overriding

blanking input (BI) which can be used to control the lamp intensity (by pulsing) or to inhibit

the outputs.


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The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and

Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock.

A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The

SN54/74LS107A is the same as the SN54/74LS73A but has corner power pins.

1pc Breadboard

1pc 2-input OR Gate

1pc 2-input XOR Gate 74LS86

1pc 3-input AND gate 74LS11

2pcs Dual D Flip-flops 74LS74

2pcs Dual JK Flip-flops 74LS76

1pc Dual JK Flip-flops 74LS107

RESISTORS

CAPACITORS

2pcs 7-segment Decoder and Driver 74LS47

2pcs 7-segment display

Connecting Wires


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000

111

110

101

100

011

010

001

PS NS

D1 D2 D3

0

1

2

3

4

5

6

7


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PS NS A B C

0

1

2

3

4

5

6

7

AB

C 00 01 11 10

0

1

AB

C 00 01 11 10

0

1

AB

C 00 01 11 10

0

1


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AB

C 00 01 11 10

0

1

AB

C 00 01 11 10

0

1

AB

C 00 01 11 10

0

1

AB

C00

01 11 10

0

1

AB

C 00 01 11 10

0

1

AB

C 00 01 11 10

0

1


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Experiment #1 Sequential Ckt