exp2report.pdf

Embed Size (px)

Citation preview

  • 7/30/2019 exp2report.pdf

    1/5

    Experiment #2Function GeneratorFarzin Akbar

    810188407

    [email protected]

    Isaac Kargar

    810188254

    [email protected]

    Abstract The importance of function generators in digital

    electronics is out of question. This experiment focuses on the

    implementation of a function generator that is able to produce

    different waveforms such as square, sawtooth, triangle, and sine

    waveforms. Also, it has the ability to generate an arbitrary signal

    which is a digitalized voice. The function generator is implemented

    in QUARTUS and consists of a PWM, a digital to analogue

    converter, a digital function generator, and amplitude and

    frequency selectors. Finally the codes were uploaded on an Altera

    Board and the board itself functioned as a function generator.

    KeywordsPWM, Function generator, DAC, Altera,QUARTUSS

    I. INTRODUCTIONAs function generators play an important role in the world of

    digital electronics, it is of great importance to get to know the

    fundamental blocks that make the function generator and the

    way to implement them via Verilog programming language

    which is a hardware description language through QUARTUS

    programme. Perhaps the most important part of the Function

    Generator is the PWM that makes the generation of different

    pulses possible. Another aim of this experiment was to

    familiarize us with the register transfer level design and

    implementation, hardware realization of mathematical

    equations and the use of passive low pass filter for producing

    analogue outputs. Each will be described in detail in the

    following sections.

    II. METHODOLOGYTo initiate the project, we first needed to implement a PWM

    which is more of a method than a building block. Its a method

    of varying the duty cycle to regulate motor speed and is known

    as pulse width modulation (PWM). Period of PWM has to be

    small enough so that it has little effect of on/off switching on

    load. Pulse Width (PW) determines the amount of power whichis fed to the load. In this experiment, period of PWM is fixed

    at 256 clocks and its pulse width is the value on 8-bit input of

    module. Figure 1 shows sample PWM waves and figure 2

    illustrates the Verilog code that was written to implement a

    PWM in QUARTUS hardware description program.

    Figure 1. Sample PWM waveforms.

    Figure 2. Verilog code to implement the PWM module.

    DAC is the next important building block of the function

    generator that converts the digital signal to the analogue

    signal. Its presence is a matter of importance because it makesthe signal sensible for humans and other analogue systems.

    DACs can be implemented with different methods. The

    easiest one is the PWM method. A stable voltage is switched

    into a low-pass analogue filter with a duration determined by

    the digital input code. Figure 3 shows a schematic of this low-

    pass filter.

  • 7/30/2019 exp2report.pdf

    2/5

    Figure 3. Low pass filter.

    In this experiment this low pass filter was loaded on thebread board and in the final step the output of the altera board

    was applied to it. In this implementation resolution of DAC is

    equal to resolution of the PWM and its maximum sampling

    rate is switching frequency (1/period) of PWM. Output value

    of this DAC can be approximated by Duty Cycle of PWM

    signal multiplied by Vcc value.

    The third important part of this project is the digital function

    generator itself. The function generator produces desired

    functions over time and waves generated by this module havethe fixed period of 256 clocks. It is worth noting that the

    output of the function generator is an 8-bit digital signal

    representing the amplitude of the signal. One must bear in

    mind that due to characteristics of implemented DAC, valid

    range of the output is between Vcc and Gnd. The waveforms

    that the function generator could produce, are described next.Next the code of different waveforms that the function

    generator must have been able to produce was written and each

    ones waveform was checked for verification. Figure 3 shows

    the code that was written for the sawtooth waveform.

    Figure 4. Code written to implement the sawtooth

    waveform.Figure 4, 5, and 6 illustrate the codes for the square wave,

    triangle wave, and sine wave outputs, respectively.

    Figure 5. Code written for square waveform

    Figure 6. Code written for triangle waveform

    Figure 7. Code written for the sine waveform.

    Writing codes for different waveforms was a matter of simply

    except for the sine wave in which some points must have beenkept in mind. In order to increase the accuracy of the

    mathematical operations they were all done in 16-bit fixed

    point. We considered a period of about 256 clocks equation

  • 7/30/2019 exp2report.pdf

    3/5

    turn to (assuming value between -32768 to 32767 for Sin and

    Cos):Cos(n)=Cos (n-1) - 1/64 Sin (n-1)

    Sin(n)=Sin (n-1) + 1/64 Cos (n-1)

    output of these calculations will be signed. But as PWM cant

    handle negative values, it should be biased in unsigned range

    and its 8 most significant bits can be used as output. The most

    important point was that the sine and cosine must have beensign extended.

    Another code that was written was the ampsel code that was

    used to change the amplitude of the digital output waveform byshifting its bits. Figure 8 shows the code of this module.

    Just like ampsel, a module was written for changing the

    frequency of the output waveform and its name was freqs. It

    gives us the ability to choose between 4 frequencies for the

    output wave form. Figure 8 shows its code.

    Figure 8. Code written for frequency selector function.

    All of our modules were verified to work correctly by the Lab Assistant.

    Next, the code of all waveforms and modules were merged

    and we wrote a code named funcsel which could be seen in

    Appendix1. It included all the waveforms and was controlled

    by some control signals so that the user could choose the output

    waveform type and its amplitude and frequency. Another

    waveform that was later added was the arbitrary waveform was

    a voice file sampled at 8 KHz and it could be heard via twospeakers.

    Finally the codes were uploaded on the Altera board and its

    output was applied to a low pass filter which acted as an ADC.

    The output of the ADC was visualized via the oscilloscopeavailable in the FPGA lab. Figures 9 to 12 show the visualized

    waveforms on the screen of the oscilloscope.

    Figure 9. Square waveform

    Figure 10. Sawtooth waveform

  • 7/30/2019 exp2report.pdf

    4/5

    Figure 11. Triangle waveform

    Figure 12. Sine waveform.

    III.CONCLUSIONSThe function generator implementation was done in this

    experiment. It was found that PWM plays an important role in

    the implementation of a function generator. We also found that

    we could upload the code of the function generator on theAltera board so that it could be used as a function generator.

    The necessity of a DAC was also surveyed as it changes thedigital signal to analogue signals that could be detected by

    human senses and other analog systems.

    Figure 13. Overview of the function generator.

    REFERENCES

    [1] Experiment#2, Digital Logic Design Lab, Semester Spring 1392,University of Tehran.

    APPENDIX

    Appendix1

    module funcsel(input [2:0]func, input clk, input rst, output

    reg [7:0] out);reg [7:0] cnt = 0;

    reg [14:0] cnt2 = 0;

    wire [15:0]sin1,cos1;

    reg [15:0] sin,cos;

    reg a=0;

    wire[7:0]q;isaac s1(cnt2,clk,q);

    assign sin1 = sin +

    {cos[15],cos[15],cos[15],cos[15],cos[15],cos[15],cos[15:6]};

    assign cos1 = cos -

    {sin1[15],sin1[15],sin1[15],sin1[15],sin1[15],sin1[15],sin1[15

    :6]};

    always @(posedge clk) begin

    if(rst == 1) begin

    out

  • 7/30/2019 exp2report.pdf

    5/5

    end

    endelse if(func == 3) begin

    out